JP4035751B2 - Encoder signal processing circuit and signal processing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to the signal processing of an encoder that outputs a two-phase rectangular wave signal that is 90 degrees out of phase with respect to the displacement of a detected object, and particularly eliminates jitter generated at the edge of the rectangular wave signal. And a signal processing method thereof.
[0002]
[Prior art]
As a noise removal circuit for an encoder signal, there is a method using a delay filter (conventional example 1). FIG. 3 is a block diagram of a conventional noise removal circuit. The input signal is sampled at the rising edge of the clock. The 3-input AND or 3-input OR gate section detects whether the encoder signal changes during 3 consecutive clocks. That is, these gate section outputs are output only when the same state is maintained for the rising edges of the three clocks. As a result, instantaneous noise spikes generated at the edge and jitter shorter than two clock cycles are eliminated.
Another conventional example is JP-A-9-257516 (conventional example 2). FIG. 7 shows the connection diagram. FIG. 8 is a waveform diagram for explaining the operation. A peak-hold circuit that supplies one phase PA of the two-phase rectangular wave signal having jitter at the edge to the D input terminal of the D flip-flop, and the other one-phase PB is composed of a diode D1, a capacitor C1, and a resistor R3. To supply. The jitter at the edge portion is removed by this peak hold circuit, resulting in a waveform as shown by PD in FIG. This output signal PD is supplied to the clock input of the D flip-flop circuit through the waveform shaping circuit. A signal Qc in the direction of displacement can be extracted from the output of the D flip-flop circuit, and a signal PE with a displacement amount not including jitter can be extracted from the output of the waveform shaping circuit.
[0003]
[Problems to be solved by the invention]
An electrical interpolation circuit is used to increase the resolution of the encoder signal. This interpolation circuit converts a two-phase sine wave signal obtained from the sensor signal into a digital signal having a certain number of bits. FIG. 4 shows the relationship between the two-phase sine wave signals SA and SB input to the interpolation circuit and the digital signal outputs B0 to B7. FIG. 5 is an enlarged view of the least significant bit B0 and the bit B1 that is one bit higher in the digital signal output shown in FIG. 4 in the horizontal axis direction. Since the sensor signal is a signal having a certain S / N, as shown in FIG. 5, in the digital signal output, the H / L of the signal has an uncertain part at the bit switching point.
On the other hand, in order to facilitate signal processing and reduce the number of output signals, conversion to a two-phase rectangular wave signal using B0 and B1 is also performed. An exclusive OR of B0 and B1 is used to generate an A signal of a two-phase rectangular wave signal, and a B signal that is 90 degrees out of phase with the A signal using B1. FIG. 6 shows the A signal and B signal generated. As shown in FIG. 6, the uncertain part of the digital signal appears at the edge of the two-phase rectangular wave signal (A signal, B signal). The jitter part generated due to the above-described reason has a characteristic that it becomes longer in proportion to the longer period of the sensor signal, and there is a problem that it cannot be removed by the delay type filter of Conventional Example 1.
In the prior art 2, the peak hold circuit is used to remove the jitter, and time is required for discharging the capacitor used in this circuit. If the discharge time is lengthened, the high frequency input signal cannot be dealt with, and if the discharge time is shortened, the peak hold characteristic is deteriorated and the input signal in a wide frequency range cannot be dealt with.
The present invention has been made in view of such a problem, and a jitter removal circuit capable of dealing with an input signal in a wide frequency range that cannot be dealt with by a jitter removal method using a delay filter or a peak hold circuit, and a signal processing method therefor The purpose is to provide.
In particular, when the detection signals having different phases of 90 degrees of the encoder are made to have a high resolution by using an electric interpolation circuit, the jitter can be removed while keeping the phase difference of the detection signals at 90 degrees.
[0004]
[Means for Solving the Problems]
In order to solve the above-described problem, the invention according to claim 1 is generated at the edge portion of the rectangular wave signal of the encoder that outputs two-phase rectangular wave signals that are 90 degrees out of phase with respect to the displacement of the detection object. In the signal processing circuit of the encoder for removing jitter, the two-phase rectangular wave signal and the inverted signal of the rectangular wave signal are used as input signals of four sets of RS flip-flops, and two of the outputs of the four sets of RS flip-flops By taking the AND signal of the output of the pair of RS flip-flops and taking the AND signal of the output of two different sets of RS flip-flops different from the above two sets, two phases that are 90 degrees out of phase with no jitter at the edge portion. It comprises means for outputting a rectangular wave signal.
According to the second aspect of the present invention, the jitter generated at the edge portions of the A-phase and B-phase signals of the encoder that outputs the A-phase and B-phase signals that are 90 degrees out of phase with respect to the displacement of the detected object. In the signal processing circuit of the encoder to be removed, the A phase signal is input to the S input, the B phase signal is input to the first RS flip-flop, the B phase inverted signal is input to the S input, and the A phase A second RS flip-flop to which an inverted signal is input, an A-phase inverted signal to the S input, a third RS flip-flop to which the B-phase signal is input to R, and the B-phase inverted signal to A first AND circuit that takes a logical product of the fourth RS flip-flop to which the A-phase signal is R-inputted to the S input, and the first RS flip-flop output signal and the second RS flip-flop signal And the third R It is obtained by a second AND circuit taking the logical product of the flip-flop output signal fourth RS flip-flop output signal.
The invention according to claim 3 is characterized in that the jitter generated at the edge portions of the A-phase and B-phase signals of the encoder that outputs the A-phase and B-phase signals that are 90 degrees out of phase with respect to the displacement of the detected object. In the signal processing method of the encoder to be removed, the A phase signal is input to the S input of the first RS flip-flop, the B phase signal is input to the R input, and the B input is input to the S input of the second RS flip flop. A phase inversion signal, the A phase inversion signal are input to the R input, the A phase inversion signal, the B phase signal to the R input, the third RS flip-flop to the S input, 4, the B phase inversion signal, the A phase signal to the R input, and the logic of the first RS flip flop output signal and the second RS flip flop signal. The product signal is the true phase A No. and then, in which a signal of the logical product of said third RS flip-flop output signal and the fourth RS flip-flop output signal and the true B-phase signal.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a signal processing circuit diagram according to an embodiment of the present invention. FIG. 2 is a signal waveform diagram showing the operation of each part.
In FIG. 1, 1-4 are RS flip-flops composed of NAND gates.
The S input S1 of the RS flip-flop 1 has an A signal in the two-phase rectangular wave signal having jitter at the edge portion shown in FIG. 2a, and the R input R1 shows the A signal in FIG. 2b. The B signal is input.
A B-signal which is an inverted signal of the B signal shown by d in FIG. 2 is applied to the S input S2 of the RS flip-flop 2, and an A signal which is an inverted signal of the A signal shown in FIG. 2c is applied to the R input R2. -A signal is input.
Further, the S input S3 of the RS flip-flop 3 has an A- signal, the R input R3 has a B signal, the S input S4 of the RS flip-flop 4 has a B-signal, and the R input R4 has an A signal. Is entered.
A waveform indicated by e in FIG. 2 is output to the output Q1 ′ of the RS flip-flop 1, and a waveform indicated by f in FIG. 2 is output to the output Q2 ′ of the RS flip-flop 2. When both AND signals are taken by the AND gate 5, an output Ao having no jitter at the edge portion indicated by i in FIG. 2 is obtained.
2 is output at the output Q3 of the RS flip-flop 3, and the waveform indicated by h in FIG. 2 is output at the output Q4 of the RS flip-flop 4.
When both AND signals are taken by the AND gate 6, an output Bo having no jitter at the edge portion indicated by j in FIG. 2 is obtained. Ao and Bo are rectangular wave signals that are 90 degrees out of phase with each other.
The combination of the input signal and the output signal to the RS flip-flop is not limited to the above embodiment. It is clear that the same function as that of the embodiment can be obtained even if the RS flip-flop is constituted by an OR gate.
[0006]
【The invention's effect】
The present invention provides an encoder signal processing circuit for removing jitter generated at an edge portion of the rectangular wave signal of an encoder that outputs a two-phase rectangular wave signal having a phase difference of 90 degrees with respect to a displacement of a detection object. The two-phase rectangular wave signal and the inverted signal of the rectangular wave signal are input signals of four sets of RS flip-flops, and the AND signals of the outputs of two sets of RS flip-flops among the outputs of the four sets of RS flip-flops. And means for outputting a two-phase rectangular wave signal having a phase difference of 90 degrees and having no jitter at the edge portion by taking an AND signal of outputs of two different sets of RS flip-flops different from the two sets. Therefore, a jitter removal circuit that can handle an input signal in a wide frequency range that cannot be handled by a delay filter or a jitter removal method using a peak hold circuit, and its signal. It can provide a processing method.
In particular, when high-resolution detection signals having a 90-degree phase difference of the encoder are made high-resolution using an electrical interpolation circuit, jitter can be reliably removed while maintaining the phase difference of the detection signals at 90-degree. realizable.
[Brief description of the drawings]
FIG. 1 is a signal processing circuit diagram according to an embodiment of the present invention.
FIG. 2 is a signal waveform diagram of each part showing the operation of the signal processing circuit of the present invention.
FIG. 3 is a block diagram of a conventional noise removal circuit (conventional example 1).
FIG. 4 is a diagram showing input / output signals of an interpolation circuit.
5 is an enlarged view of the least significant bit B0 shown in FIG. 4 and the bit B1 that is one bit higher in the horizontal axis direction.
FIG. 6 is a diagram illustrating a two-phase rectangular wave signal having jitter at an edge portion.
FIG. 7 is a connection diagram of a conventional jitter removal circuit (conventional example 2).
FIG. 8 is a signal waveform diagram of each part showing the operation of Conventional Example 2;
[Explanation of symbols]
1 to 4 RS flip-flops 5 to 6 NAND gate a A signal b B signal c A-signal d B-signal e Output Q1 ′ signal RS of RS flip-flop 1 Signal g2 of output Q2 ′ of RS flip-flop 2 RS flip-flop 3 output Q3 signal h RS flip-flop 4 output Q4 signal i Ao signal j Bo signal

Claims (3)

In the signal processing circuit of the encoder for removing jitter generated at the edge portion of the rectangular wave signal of the encoder that outputs a two-phase rectangular wave signal having a phase difference of 90 degrees with respect to the displacement of the detection object, the two-phase The rectangular wave signal and the inverted signal of the rectangular wave signal are input signals of four sets of RS flip-flops, and the AND signals of the outputs of two sets of RS flip-flops among the outputs of the four sets of RS flip-flops. It is characterized by comprising means for outputting a two-phase rectangular wave signal having a phase difference of 90 degrees and having no jitter at the edge portion by taking an AND signal of outputs of two sets of RS flip-flops different from the set. Encoder signal processing circuit. In the encoder signal processing circuit for removing jitter generated at the edge portions of the A-phase and B-phase signals of the encoder that outputs the A-phase and B-phase signals that are 90 degrees out of phase with respect to the detected object,
A first RS flip-flop that receives the A-phase signal as an S input and the B-phase signal as an R input;
A second RS flip-flop to which the inverted B-phase signal is input to the S input and the inverted A-phase signal is input to the R;
A third RS flip-flop to which the inverted signal of the A phase is input to the S input and the B phase signal is input to the R;
A fourth RS flip-flop to which the B phase inverted signal is input to the S input and the A phase signal is input to the R;
A first AND circuit that takes a logical product of the first RS flip-flop output signal and the second RS flip-flop output signal;
An encoder signal processing circuit comprising: a second AND circuit that takes a logical product of the third RS flip-flop output signal and the fourth RS flip-flop output signal. In the encoder signal processing method for removing jitter generated at the edge portions of the A-phase and B-phase signals of the encoder that outputs the A-phase and B-phase signals whose phases are 90 degrees different from each other with respect to the displacement of the detection object,
The A phase signal is input to the S input of the first RS flip-flop, and the B phase signal is input to the R input.
Input the B phase inversion signal to the S input of the second RS flip-flop, the A phase inversion signal to the R input,
Input the A phase inversion signal and the B phase signal to the R input to the S input of the third RS flip-flop,
The B phase inverted signal is input to the S input of the fourth RS flip-flop, and the A phase signal is input to the R input.
A signal obtained by ANDing the first RS flip-flop output signal and the second RS flip-flop output signal is a true A-phase signal,
A signal processing method for an encoder, wherein a signal obtained by logical product of the third RS flip-flop output signal and the fourth RS flip-flop output signal is a true B-phase signal.

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