JP2567166B2 - False tooth sensor circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to detect a rotational position by cutting a part of a gear that is attached to a rotary shaft for detecting a rotational position of an engine or the like and generates a pulse signal in accordance with the rotation. A circuit for a false tooth sensor.

[0002]

2. Description of the Related Art FIG. 10 is a diagram showing the structure of a false tooth sensor. A current is excited in an iron core 12 as a gear 11 mounted on a rotary shaft rotates. Output as a signal. If a part of the teeth of the gear 11 is cut out, a pulse signal is not output at that part, so the position of the false tooth of the gear 11 is detected. In the example of the false tooth sensor used in the engine, two of the 32 teeth are cut out, which will be described below as an example.

The discontinuous portion of the output pulse signal is the position of the false tooth, and it is necessary to detect the discontinuity of the pulse signal in order to detect the false tooth position. This detection is easy if the gear rotates at a constant speed, but when it is used to detect the rotational position of the engine, the rotation speed of the gear changes in a very wide range. The false tooth position is detected by a false tooth sensor circuit using an up / down counter.

[0004] The operating principle of the circuit of Figure 1 1, first counts up from an initial value in the first clock signal by one period of the pulse signal at the up / down counter, longer than the first clock signal at the next interval period The second clock signal is used to count down. Then, the operation is repeated immediately after resetting with the next pulse signal. If it is not a false tooth portion, the next pulse signal comes and is reset before it becomes less than the initial value even if it counts down, but if it is a false tooth portion, it will be less than the initial value. I know the position of. However, in this case, two pulse signals make one operation, and therefore two similar up / down counters are provided to operate in opposite phases.

In FIG. 11, the pulse signal from the false tooth sensor 1 has an unstable pulse width and is divided into ½ by the D-type flip-flop, and the two up / down counters 35 and 36 count up. Becomes a down count switching signal. Inverted switching signals are applied to the two up / down counters 35 and 36 so that they operate in opposite phases. 61 and 62 are up / down counters 35 and 36.
Is a one-shot circuit that generates a reset signal for returning to the initial value after the down-count operation. Reference numeral 5 is a clock generation circuit that generates a clock signal. This clock signal becomes the clock signal for up-counting,
D-type flip-flop 51 halves this clock signal
The signal divided by is the clock signal for down counting. Reference numerals 52 and 53 are selectors for selecting clock signals to be applied during up-counting and down-counting.

FIG. 12 shows a time chart of each part of the circuit of FIG. At the false tooth portion, the first counter 35 is down-counting and is down-counted by the clock signal having a double cycle, so that the false tooth signal is generated at the second false tooth.

[0007]

The pulse signal output from the false tooth sensor has a pulse interval that changes in accordance with the rotation, so it is determined whether or not it is a false tooth portion unless it is compared with the preceding and following pulse intervals. Can not. Therefore, conventionally
Circuits have been used that combine two up / down counters as shown in FIG.

However, as is widely known, the up / down counter has a complicated circuit to enable switching between up count and down count. FIG. 13 is a diagram showing a configuration example of a typical up / down counter and a simple up counter. As shown in FIG. 13A, the up / down counter has a gate circuit for switching between up-counting and down-counting, and the gate circuit becomes more complicated as the number of stages of the counter increases.

FIG. 13B shows an example of an up counter, and what this circuit can tolerate is D compared with a clock signal.
This is a case where the operation speed of the type flip-flop is sufficiently fast, but the configuration is far simpler than that of FIG. SUMMARY OF THE INVENTION It is an object of the present invention to realize a false tooth sensor circuit by using an up counter having a simple structure instead of an up / down counter which has a complicated circuit structure and becomes costly, thereby reducing the manufacturing cost.

[0010]

A circuit for a false tooth sensor according to the present invention has a basic structure as shown in FIG. 1 in order to achieve the above object. That is, the false tooth sensor circuit of the present invention is a false tooth sensor circuit that is capable of detecting a rotational position by cutting out a part of a gear that is attached to a rotary shaft and generates a pulse signal with rotation, The frequency dividing means 2 for dividing the pulse signal from the false tooth sensor 1 by 2 to generate a switching signal, the first up counter 3, the second up counter 4, the first up counter 3 and the second up counter 4. Clock generation means 5 for supplying a clock signal,
Counter control means 6 for controlling the first up-counter 3 and the second up-counter 4 so as to count up in reverse phase with respect to the switching signal, hold the count value, and repeat the operation in the order of reset, first up-counter 3 of the count value obtained by doubling the value and the first coincidence detecting means 7 count value of the second up counter 4 outputs a coincidence signal when a match when the count operation of the second counter, and a count of the second up counter 4 A second coincidence detecting means 8 is provided which outputs a coincidence signal when the value obtained by doubling the value and the count value of the first up counter 3 coincide with each other during the counting operation of the first up counter 3, and a combined signal of both coincidence signals. Is output as a false tooth position signal.

[0011]

The first up counter 3 and the second up counter repeat the counting operation, the protection of the count value, and the reset in the opposite phase with respect to the switching signal. Therefore, the value counted in the section of the previous pulse signal is held in the next section.
Then, the held count value is shifted upward by one bit, that is, doubled and compared with the value of the other up counter. If it is not a false tooth portion, the switching signal changes when the count value of the other up counter is counted up to a value substantially equal to the held count value. Therefore, the held value is never doubled, and the false tooth signal is not generated.

If it is a false tooth portion, since the switching signal does not change for three pulse signals, the up counter is up-counted as it is, which is twice the count value held in the other up-counter. The coincidence detecting means detects the coincidence, and the false tooth signal is generated.
The two up counters and the coincidence detecting means respectively perform complementary operations, and alternately detect the false tooth portions in accordance with the section of the pulse signal, that is, the change of the switching signal.

In the case of a false tooth in which only two teeth are cut out from 32 teeth, the coincidence detecting means that once generates a false tooth signal always generates a false tooth signal. However, which one is to generate the false tooth signal is determined by the false tooth position at the first power-on reset.

[0014]

EXAMPLE An example of the present invention is shown in FIG. A D-type flip-flop 2 divides the pulse signal from the false tooth sensor to generate a switching signal. 31 to 33 are D-type flip-flops forming the first up counter,
Further, the number of stages corresponding to the counters is connected. 41 to 43 are for the second up counter. Here, these D-type flip-flops are required to operate at sufficiently high speed with respect to the clock signal. In the false tooth sensor for the engine, the pulse signal is about 5 KHz at the maximum, and the delay time of the flip-flop is about 30 ns, so there is almost no problem.

Reference numerals 61 and 62 denote, when the holding operation of the count value of the up counter is ended in response to the change of the switching signal,
It is a part that generates a reset signal for resetting to zero. Reference numerals 63 and 64 denote gates that control the supply of the clock signal to each counter according to the switching signal, supply the clock signal at the time of counting, and then stop the supply of the clock signal and hold the count value.

Reference numerals 8 1 to 8 3 constitute a coincidence detector that compares a value obtained by shifting the value of the first up-counter by 1 bit and the value of the second up-count, and includes gates 8 4, 8 5 and a D-type flip-flop. A false tooth signal is output by the amplifier 86 only when the counts of the second up counter coincide with each other.
The same applies to the second match detection circuit composed of 7 1 to 7 6. EXOR gates of each coincidence detection circuit are required for the number of stages of the up counter.

The time chart of FIG. 3 shows the change of the up counter in the circuit of FIG. In FIG. 3, the false tooth portion is in contact with the counting operation of the second up counter, and the false tooth signal is output when the count value a held at the first up counter is doubled at that time. In the time chart of FIG. 3, since the clock signal is constant, the up counter needs to count a tripled value in the false tooth portion, and the number of stages of the counter needs to be increased accordingly. In addition, it may be desirable to adjust the timing for determining the false tooth portion in consideration of mechanical errors and the like. For the purpose described above, FIG. 4 shows an up counter in the case where the clock signal is switched to a clock signal with a longer cycle when the value held in one up counter becomes equal to the value in the other counter. It is a figure which shows the time chart of. As a result, the timing of generation of the false tooth signal is delayed, and the maximum count value of the up counter is also reduced.

FIG. 5 shows a circuit configuration for switching the clock signal during the counting operation as shown in FIG. As is apparent from comparison with FIG. 1, a third match detection means 51 is further provided in FIG. The third coincidence detecting means 51 detects whether or not the values held in one of the first up counter and the second up counter and up counted in the other coincide with each other, and when the coincidence is detected, the clock is correspondingly detected. The generating means 5 switches the clock signal. The third match detection means 51 can use the match detection circuit shown in FIG. 2 as it is, and compare the count values of the same stage of the first and second up counters.

When changing the clock signal, it is necessary to change the cycle of the clock signal to be between 1 and 2 times, and a decimal multiple clock circuit for generating such a clock will be described. Even in the conventional false tooth sensor circuit using the up / down counter shown in FIG. 11, it is desirable to count down by a clock signal whose cycle is changed to an appropriate value between 2 and 3 times during down counting. Such a fractional clock circuit can be used.

FIG. 6 is a diagram for explaining the principle of the fractional multiple clock circuit. Basically, an original clock signal having a frequency sufficiently higher than that of the clock signal is generated, and the original clock signal is divided to obtain a clock signal. Then, in order to obtain the clock signal of 1.1 times, the output of the original clock signal is stopped for one count while the original clock signal is counted 11 times. The original clock signal output in this way is divided to obtain a clock signal whose period is 1.1 times. Similarly, 1.
In the case of doubling, 2 counts are removed from 12 counts, and a decimal multiple clock signal is obtained.

FIG. 7 shows an example of the configuration of such a circuit for multiplying a decimal fraction of a clock signal. Reference numeral 101 denotes an original clock generation circuit, which divides the original clock signal by a frequency divider circuit 106 to obtain a normal clock signal. Reference numeral 102 is a counter for counting the original clock signal, and the counter cycle setting circuit 10
3 outputs a signal for resetting the counter 102 when the count value reaches 11, which is a predetermined value, for example, 1.1 times. As a result, the counter 102 repeats counting up to a predetermined value.

Clock removal setting circuits 104 and 105 output a match signal when the count value of the counter 102 reaches a predetermined value, and when the match signal is output, the gate 107 divides the original clock signal. The output to the circuit 106 is stopped. In the case of 1.1 times, one count may be excluded from the 11 counts, so that only one clock removal setting circuit is required. However, in order to obtain a clock signal of 1.6 times, it is basically necessary to set the counter period setting circuit 103 to 16 and to provide 6 clock removal setting circuits to exclude 6 counts.

FIG. 8 shows an example of a circuit for obtaining a 1.1-fold clock signal. Here, the setting of the counter cycle and the setting of removal of the original clock signal are common, and
When the value of the 4-stage counter constituted by 02d reaches 10, that is, when the binary code reaches 1010, the output of the next original clock signal is stopped and the counter is reset.

FIG. 8 shows a circuit for obtaining a clock signal of 1.1 times. Since only one count of the original clock needs to be removed from 11 counts, the cycle setting of the counter and the removal setting of the original clock can be made common. 9 shows an example of a circuit which is more generalized and can arbitrarily obtain up to 1.6 times. Reference numeral 111 is a four-stage counter using a D-type flip-flop.
Reference numeral 2 is a coincidence detection comparator that determines the cycle of the counter 111. If an appropriate value is set to the terminal, the counter 11
1 repeats counting at an arbitrary cycle. 113 to 11
Reference numeral 5 is a coincidence detection comparator for setting a count value for stopping the output of the original clock. Comparator 1
13 to 115 detect the coincidence of only the lower 3 bits of the counter 111. This will be described with reference to FIG.

To obtain a clock signal of 1.1 times,
If 10 is set in the comparator 112, the counter 111
Repeats the operation of counting from 0 to 10, that is, counting the original clock signal by 11. When the binary code 011 is set to the comparator 113, that is, 3 is set, the lower 3 bits of the counter 111 become 011 only once, and only 1 count is removed from 11 counts. Therefore, in the case of 1.1 times, the comparators 114 and 115 are not necessary.

In the case of 1.2 times, the setting of the comparator 112 is simply changed to 11. Then, even when the counter value is 11, that is, at the 12th place, the lower 3 bits of the counter value becomes 011 and the output of the original clock signal is stopped. Therefore, even in the case of 1.2 times, the comparators 114 and 115 are not necessary. Similarly, in the case of 1.3 times to 1.6 times, if the value corresponding to the period is set in the comparator 112 and the values shown in FIG. Is obtained.

[0027]

According to the present invention, it is possible to realize a circuit for a false tooth sensor which can be constituted only by an up counter without using a complicated up / down counter, and the circuit can be simplified and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a false tooth sensor circuit of the present invention.

FIG. 2 is a diagram showing a circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing a time chart in the circuit of FIG.

FIG. 4 is a diagram illustrating an effect of changing a clock signal in the middle of counting up.

FIG. 5 is a diagram showing a circuit configuration for changing a clock signal.

FIG. 6 is a diagram showing the principle of a circuit for multiplying the period of a clock signal by a decimal.

FIG. 7 is a diagram showing a configuration of a circuit for multiplying a cycle of a clock signal by a decimal.

FIG. 8 is a diagram showing an example of a circuit for multiplying a cycle of a clock signal by a decimal.

FIG. 9 is a diagram showing another example of a circuit for multiplying the period of a clock signal by a decimal.

FIG. 10 is a diagram showing a configuration of a false tooth sensor.

FIG. 11 is a diagram showing a configuration of a conventional false tooth sensor circuit using an up / down counter.

12 is a diagram showing a time chart of the circuit of FIG. 11. FIG.

FIG. 13 is a diagram showing a difference in configuration between an up / down counter and an up counter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... False tooth sensor 2 ... Dividing means 3 ... 1st up counter 4 ... 2nd up counter 5 ... Clock generation means 6 ... Counter control means 7 ... 1st coincidence detection means 8 ... 2nd coincidence detection means

Claims (3)

(57) [Claims] 1. A false tooth sensor circuit, which is attached to a rotary shaft and is capable of detecting a rotational position by cutting out a part of a gear that generates a pulse signal in accordance with rotation, said false tooth sensor ( Frequency dividing means (2) for frequency-dividing the pulse signal from 1) to generate a switching signal, first up counter (3), second up counter (4), first up counter (3) And clock generating means (5) for supplying a clock signal to the second up counter (4), and the first up counter (3) and the second up counter (4) are respectively in anti-phase with the switching signal. Counter control means (6) for controlling to repeat operations in the order of up-counting, holding of count value, and resetting, a value obtained by doubling the count value of the first up-counter (3), and the second up-counter ( Four ), The count value of the second up counter (4) is doubled , and the first match detection means (7) that outputs a match signal when the count value of the second counter (4) matches during counting operation. A second match detection means (8) is provided for outputting a match signal when the value and the count value of the first up counter (3) match during the counting operation of the first counter (3). A circuit for a false tooth sensor in which the combined signal becomes a signal indicating the false tooth position. 2. A third coincidence detecting means (51) for detecting that the values of the first up counter (3) and the second up counter (4) coincide with each other, and the clock generating means (5). ) after a possible supply resets the second clock signal having a <br/> periodic ranging from 1.1 times 1.9 times the first clock signal and said first period of the first cycle The first clock signal is supplied, and when the third match detection means (51) detects a match, the clock signal supplied from the clock generation means (5) is changed from the first clock signal to the second clock signal. The false tooth sensor circuit according to claim 1, which is switched to. 3. The clock generating means (5) comprises the first and second clock generators.
And an original clock generation means (101) for generating an original clock signal having a frequency sufficiently higher than the second clock signal , a counter (102) for counting the original clock signal, and the counter (102) for the first clock signal and the second
Counter cycle setting means (1) for outputting a reset signal for performing a reset operation for returning the counter (102) to the initial value again when the value reaches the value corresponding to the cycle ratio of the clock signal.
03), the count value of the counter (102) is the first clock
A plurality of signals corresponding to the ratio of the period of the signal and the second clock signal
Clock removing means (104, 105) for stopping the output of the original clock signal when the existing predetermined value is reached, and frequency dividing means (10) for dividing the output original clock signal.
6. The circuit for a false tooth sensor according to claim 2, comprising 6).