JPS59201518A - Two-phase oscillating circuit - Google Patents

Abstract

PURPOSE:To obtain a two-phase oscillation circuit not affected by the 1st change in an output signal of an oscillator by using the 1st and 2nd gate circuits and a trigger flip-flop so as to eliminate the need for resetting to the initial state. CONSTITUTION:A rectangular wave signal S1 outputted from the oscillator 1 is applied to a clock terminal CK of a D-FF2 and the 2nd input terminal of the 1st gate circuit EX-OR 8, a signal obtained at an output terminal Q of the D-FF2 is applied to the 1st input terminal of the 1st gate circuit EX-OR8 and outputted as the 1st pulse signal P11, an output signal S3 of the 1st gate circuit EX- OR8 and a phase designation signal H are applied respectively to the 1st and 2nd input terminals of the 2nd gate circuit EX-OR9, and further an output signal of the 2nd gate circuit EX-OR9 is outputted as the 2nd pulse signal P12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a two-phase oscillation circuit that outputs first and first Norse signals whose phases are shifted by Oo.

This type of oscillation circuit is used in speed control of electric motors and in various other fields. FIG. 7 is a circuit diagram showing a configuration example of a conventional co-phase oscillation circuit. In this figure, reference numeral 1 is an oscillator that generates a rectangular wave signal S1 shown in Fig.
It is supplied to the clock terminal CK of D-FF (abbreviated as D-FF) 2, and also supplied to the clock terminal CK of D-FF 4 via the inverter 3. D-FF2 and D-FF4 each have their input terminals connected to their output terminals Q, and serve as trigger flip-flops that are triggered at the rising edge of the signal supplied to the clock terminal CK, and the output terminal of D-FF2 The signal obtained from QK is output as the first pulse signal P1 (see port C in Figure 1)), and the signal S2 output from the output terminal Q of D-FF4 (see e → in Figure 1) is an exclusive logic signal. Sum gate (hereinafter abbreviated as EX-OR) 5
is supplied to one input end of the . Further, a reset signal R is supplied to each reset terminal of D-FFs 2 and 4. EX-OR5 is a circuit that takes the exclusive OR of the signal s2 and the phase designation signal H (see Figure 2), and its output signal is the first pulse signal P2 (see Figure 2 (E)). reference)
is output as

Thus, in the initial state, the reset signal R is supplied (see time to shown in FIG. 2), and then the output signal Sl of the oscillator 1 rises. From then on, each pulse shown in FIG. are sequentially output, the seventh pulse signal P1 shown in FIG.
As shown in c), a signal S2 whose phase is delayed by o0 from the seventh pulse signal P1 is output. Here, if the phase designation signal H is at the 90'' signal, the signal s2 (see FIG. 2) and the second pulse signal P2 are the same, and therefore the second pulse signal P2 Figure (E)) shows a signal whose phase is delayed by 20? from the first pulse signal P1. Next, when the phase designation signal H becomes a 91" signal, the second pulse signal P2 becomes a signal obtained by inverting the signal S2. becomes. As a result,
As shown in FIG. 2 (e), the second pulse signal P2 is
This is a signal whose phase is advanced from that of the pulse signal P1. In this way, the circuit shown in FIG. 1 has different phases θ0.
It is possible to output the shifted 1X-second pulse signals P1 and P2, respectively, and also output whichever pulse signal P1. Whether or not to advance the phase of P2 can be designated by the phase designation signal H.

By the way, the above-mentioned conventional two-phase oscillation circuit has the disadvantage that each of the D-FFs 2.4 must be reset in the initial state, and the first change in the output signal S1 of the oscillator 1 must be taken as a rising edge. be. That is, for example, if the first change of the Ibo 81 in the initial state is a fall as shown in FIG.
When the first pulse signal P1 and the signal S2 are as shown in FIGS. 2(G) and 2(E), respectively, the phase of the signal S2 leads the phase of the first pulse signal P1 by O degrees.

As a result, when the phase designation signal H is 0 "i" which designates the delayed phase of the second pulse signal P2, the phase of the second pulse signal P2 becomes 7 as shown in FIG. When the phase designation signal H is an 11" signal specifying a leading phase, the second pulse No. 48 P has a phase lead of 20 and a lag of θ0. Therefore, in the two-phase oscillation circuit described above, the first change in the signal Sl in the initial state must always be a rising edge.
It is especially important to make the first change in oscillator 1 a rising edge.
However, this is very difficult in the case of a V/F (i-striking force/frequency) converter.

Therefore, this invention does not require resetting in the initial state and is not affected by the initial change in the output signal of the oscillator! The circuit provides a phase oscillation circuit, and includes a trigger flip-flop triggered by a rectangular wave signal output from an oscillator, and a seventh gate that takes an exclusive OR of the output of the trigger flip-flop and the rectangular wave signal. The first gate circuit calculates the exclusive OR of the output of the first gate circuit and a phase designation symbol that designates phase lead or delay.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a circuit IA showing the configuration of a two-phase oscillation circuit according to the present invention. In this figure, the rectangular wave signal Sl output from the oscillator 1 is supplied to the clock terminal CK of D-FF2 (see FIG. 7) and the first input terminal of EX-OR8, and the output terminal QK of D-FF2. The signal obtained is EX-
It is supplied to the input terminal of OR8, and is also output as the seventh pulse signal P11, and is the output signal S of EX-OR8.
3 and phase designation signal H are the 11th of EX-Ofζ9, respectively.
The output signal of EX-OR9 is supplied to the second input terminal, and the output signal of EX-OR9 is output as the second pulse signal P12.

In the above configuration, when the signal S1 whose first change is a rising edge is output from the oscillator 1 as shown in FIG. As shown in (b) and (c), the signal S3 becomes a signal with a phase lag O0 behind the seventh pulse signal pH. As a result, as shown in Figures ≠) and (E), if the signal H to the phase designation is the "0" signal, the !nohalus signal P)12 is the first pulse signal P11 and the "0" signal. If the phase designation signal H is a 91" signal, O
The signal becomes a 0-advanced phase signal.

In addition, as shown in FIG. 7(F), when the first change of the signal Sl is a falling edge, the seventh pulse signal Pli and signal S3 are as shown in FIGS. 7(G) and (E), respectively. Then,
In this case as well, as in the case described above, the signal S3 is a signal with a phase delay of 900 compared to the first pulse signal pH. As a result, as shown in FIG.
2 is a signal with a phase delayed by θ0 from the first pulse signal Pix, and conversely, when the phase designation signal H is a "1" signal, the signal is a signal with a phase leading by O0.

In this way, in the circuit shown in FIG. 3, the signal S3 is the same as the seventh pulse signal pH, regardless of the initial state of change of the signal S1. . As a result, the phase of the second pulse signal P12 is always equal to the phase designation signal H.
The phase corresponds to .

Note that in the initial state, the output terminal Q of D-FF2 is
Even in the case where the seventh pulse signal pH is in the signal S3, the relationship between the seventh pulse signal pH and the signal S3 is the same as that in Fig. There is no need to reset D-FF2.

As explained above, the two-phase oscillation circuit according to the present invention is
an excavator that outputs a square wave signal, a trigger flip-flop that is triggered by the square wave signal output from the oscillator, and an output of the trigger flip-flop and m
a seventh gate circuit that takes the exclusive OR of the rectangular wave signals listed in J; and a second gate circuit that takes the exclusive OR of the output of the seventh gate circuit and a phase designation signal that specifies the lead or lag of the phase. Since the gate circuit has the following gate circuit, there is an advantage that there is no need to perform an initial reset, and an OII point that is not affected by the initial phase of the output signal of the excavator can be obtained.

[Brief explanation of the drawing]

FIG. 7 is a circuit diagram showing an example of the configuration of a conventional two-phase oscillation circuit, FIG. 2 is a timing chart for explaining the operation of the two-phase oscillation circuit, and FIG. 3 is a configuration example of an embodiment of the present invention. The circuit diagram shown in FIG. 7 is a timing chart for explaining the operation of the same embodiment. 1...Oscillator, 2...D-FF ()
8... exclusive OR gate (seventh gate circuit), 9... exclusive OR gate (second gate circuit).

Claims (1)

[Claims] A first pulse signal and a second pulse signal having a phase shift σ0 different from the seventh pulse signal are each output! In the phase oscillation circuit, an oscillator that outputs a rectangular wave signal, a trigger flip-flop triggered by the rectangular wave signal output from this oscillator, and an exclusive OR of the output of this trigger flip-flop and the rectangular wave signal are calculated. It comprises a seventh gate circuit, and a second gate circuit that takes an exclusive OR of the output of the seventh gate circuit and a phase designation signal that designates a phase lead or a delay, and A co-phase oscillation circuit characterized in that the output signal and the output signal of the first gate circuit are output as the seventh and first pulse signals, respectively.