JPS61225933A - Reference signal generating circuit for detecting 3 frequency tone signal - Google Patents

Abstract

PURPOSE:To form three kinds of reference signals for detecting SAT by providing a pulse inserting/extracting circuit forming a signal inserted with one pulse, a signal extracted by one pulse and a signal without any pulse insertion/ extraction at each period when an output signal of a frequency division counter is obtained. CONSTITUTION:A prescribed number of pulses a counted by a frequency division counter 2, from which a signal is outputted at each count. The pulse inserting/ extracting circuit 4 forms three kinds of signals, a signal inserted by one pulse, a signal extracted by one pulse, and a signal without any pulse insertion/ extraction at each prescribed time by means of the logical processing between an output signal of a frequency division circuit 1 and an output signal of a delay circuit 3. The three kinds of signals having frequencies of F(m+1)/m, F(m-1)/m are formed and outputted from the circuit 4, where (m) is a prescribed number of the counter 2 and F is a frequency of a master clock, they are selected by an identification code and become a reference signal for a digital phase synchronizing signal. Thus, whether or not a signal is a 3-frequency tone signal is identified easily.

Description

[Detailed Description of the Invention] [Summary] A pulse insertion/removal circuit generates three types of signals: a signal with one pulse inserted from the master clock every predetermined period, a signal with one pulse removed, and a signal without pulse insertion/removal. The output signal of the pulse insertion/extraction circuit is selected according to the identification code, and is added to the digital phase synchronization circuit as a reference signal for SAT detection. It is possible to form three types of reference signals for detection.

[Industrial application field]

The present invention is applicable to a car telephone system: 5AT (Sup
Standards corresponding to the identification code are used in a digital phase locked circuit (DPLL) that is phase-synchronized with a 3-frequency tone signal such as an audio tone signal and detects whether the tone signal is specified by the identification code. The present invention relates to a reference signal generation circuit for detecting a three-frequency tone signal to which signals are added.

For example, SAT signals in a car telephone system are used to identify each system zone distributed in a cellular manner, and this system is called a cellular system. The SAT signal in this cellular system has three types of frequencies, for example, 5970Hz, 6000Hz, and 60Hz.
30Hz is used.

In each cell, data is transmitted and received between the base station existing in that cell and the automobile terminal device, and the S
The frequency of the AT signal is notified to the automobile terminal device using an identification code. The automobile terminal device that receives the identification code detects whether the received SAT signal is the SAT signal specified by the identification code or not, and if it determines that it is the specified SAT signal, it activates the specified channel. If it is determined that the SAT signal is not the specified SAT signal, the specified channel is invalidated and the SAT signal reception detection process is performed again. This is to prevent

[Conventional technology]

The conventional receiving section for SAT signals in automobile terminal equipment is
For example, it has the configuration shown in FIG.
The AT signal is applied to a phase comparator circuit 51 and a DPLL section (digital phase locked circuit section) 55, and is divided into a signal obtained by dividing the output signal of the voltage controlled oscillator 53 by a frequency divider 54 and a received SA signal.
The phase with the T signal is compared by a phase comparator 51, and a signal corresponding to the phase difference is passed through a loop filter 52 and becomes a control voltage for a voltage controlled oscillator 53. Therefore, the voltage controlled oscillator 5
The output signal No. 3 is a signal phase-synchronized with the received SAT signal. This signal is added as the DPLLPLL part 5 signal to obtain an output signal phase synchronized with the received SAT signal.

This DPLLPLL part 5 signal is 1, and even if there is a momentary interruption of the received SAT signal due to fading etc., the SA
Since it is output as a T signal, 3AT in that cell
According to the identification code that specifies the frequency of the signal, the DPLL
The frequencies of the PLL section 5 signals are compared, and if they match, it is determined that the correct SAT signal is being received.

[Problem that the invention seeks to solve]

The conventional example has a dual phase control loop including a phase control loop including the voltage controlled oscillator 53 and a control loop for the DPLL section 5.
It is not possible to determine that a correct SAT signal has been received just by performing phase synchronization pull-in, but a separate means is required to identify whether or not the SAT signal corresponds to the identification code. . Therefore, the circuit scale becomes large and it is difficult to integrate the circuit.

Also, prepare a type of reference signal that corresponds to the type of SAT signal, select it according to the received identification code, and send it to the DP.
Although it is conceivable to use five LLPLL section signals, it is necessary to provide an oscillator for generating reference signals of different frequencies, which has the drawback of increasing the size and cost.

SUMMARY OF THE INVENTION An object of the present invention is to form, with a simple configuration, reference signals of different frequencies necessary for reception and detection of SAT signals using a single mask crotter.

[Means for solving problems]

The reference signal generation circuit for SAT detection of the present invention will be explained with reference to the principle block diagram shown in FIG. a frequency division counter 2 that counts a predetermined number of master clocks and outputs a signal; a delay circuit 3 that delays the output signal of the frequency division counter 2 by a period of 1/2 of the period of the master clock; and a frequency division circuit 1. and the output signal of the delay circuit 3 to obtain the output signal of the frequency division counter 2. For each period, a signal with one pulse inserted, a signal with one pulse removed, and a signal without pulse insertion/removal are obtained. It is equipped with a pulse insertion/removal circuit 4 that forms three types of signals, and a selector 5 that decodes the identification code with a decoder 6 and selects the output signal of the pulse insertion/removal circuit 4 based on the decoded output signal. Yes, the signal selected and output by selector 5 is sent to the receiving SAT.
It is added as a reference signal for a digital phase synchronization circuit that synchronizes the phase of the signal.

[Effect]

The frequency dividing circuit 1 is for converting the master clock into a pulse with a duty of 50%, and this pulse is counted by a predetermined number by a frequency dividing counter 2, and a signal is output for each count. The pulse insertion/removal circuit 4 performs logical processing on the output signal of the frequency dividing circuit 1 and the output signal of the delay circuit 3 to generate a signal with one pulse inserted every predetermined period, a signal with pulse removed, and no pulse insertion/removal. Three types of signals are formed. If the predetermined number of the frequency dividing counter 2 is m and the frequency of the master clock is F, then from the pulse insertion/removal circuit 4, F
(m+1) A signal with a frequency of 7m and a signal with a frequency of F(m-1
) 7m frequency signal and F m / m signal.
types of signals are formed and output.

These three types of signals are selected by an identification code and serve as reference signals for the digital phase synchronization circuit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 21 is a reference signal generation circuit, 22 is a DPLL section (digital phase synchronization circuit section), and 23 is a lock detection section. The reference signal generation circuit 21 includes a master clock and an identification code DCC1D.
CC2 is added, and three types of signals are formed, a signal with one pulse inserted at every predetermined period, a signal with one pulse removed, and a signal with no pulse insertion/removal, based on the mask cross. Bit identification code DCC1, D
One of the three types of signals is selected by the CC2 and becomes a reference signal to the DPLL unit 22. That is, signals of three types of frequencies are generated from a single master clock, and one of the signals is selected by the identification codes DCCI and DCC2 and used as a reference signal.

The DPLL unit 22 synchronizes the phase of the received SAT signal with the reference signal of the frequency selected by the identification codes DCC1 and DCC2.
The output SAT signal is applied to the lock detection circuit 23,
Detection of phase synchronization in the DPLL section 22 is performed. In other words, if the received SAT signal and the output SAT signal are the same consecutively, it means that the phase synchronization is in the lock-in state, so a lock-in signal is output to indicate that the correct SAT signal has been received. Become.

FIG. 3 is a block diagram of a reference signal generation circuit according to an embodiment of the present invention, in which the same reference numerals as in FIG. 13 is an inverter, 14 is an exclusive OR circuit, and 15 is an OR circuit. The frequency dividing circuit 1 is composed of a flip-flop 11, and a master clock C is applied to a clock terminal C, and a d terminal and a data terminal are connected.
It outputs a signal a whose frequency is divided by 1/2 from the Q terminal, and the mask clock C is frequency-divided and has a duty of 50%.
signal a, which is applied to the frequency division counter 2 and the pulse insertion/removal circuit 4.

The frequency division counter 2 counts the signal a by a predetermined number and outputs the signal a.
．． If the frequency is 92MHz, the frequency is divided by 1/2 by the frequency divider circuit 1 to become a 0.96MHz signal a, which is sent to the frequency division counter 2.
If the predetermined number of the frequency division counter 2 is 200, the signal A is output every 200 counts of the signal a,
4,8 KH divided by 1/200
A pulse signal with a repetition frequency of z is obtained.

Furthermore, the delay circuit 3 includes a flip-flop 12 and an inverter 1.
3, and the master clock C is an inverter 13.
The inverted signal d is applied to the clock terminal C of the flip-flop 12, and the output signal d of the frequency division counter 4 is applied to the data terminal. Therefore, the output signal e of the Q terminal is the output signal 9b of the frequency division counter 2 delayed by a period of 1/2 of the period of the mask clock C. This signal e is applied to the pulse insertion/removal circuit 4 together with the output signal a of the frequency dividing circuit 1.

The pulse insertion/removal circuit 4 includes an exclusive OR circuit 14 and an OR circuit 1
The output signal f of the exclusive OR circuit 14 is a signal obtained by inserting one pulse for each output signal of the frequency division counter 2, and the output signal g of the OR circuit 15 is the output signal of the frequency division counter 2. The result is a signal with one pulse removed for each signal.

Furthermore, by outputting the output signal a of the frequency dividing circuit 1 as it is, a signal without insertion or removal of pulses can be obtained. Therefore, the pulse insertion/removal circuit 4 has a simple circuit configuration consisting of an exclusive OR circuit 14 and an OR circuit 15, and can generate a signal with one pulse inserted, a signal with one pulse removed, and a signal without pulse insertion/removal every predetermined period. It is possible to form and output three types of signals.

The relationship between the 2-bit identification codes DCCI and DCC2 and the SAT signal is, for example, 5970Hz due to "00",
“01” means 6000Hz, “10” means 60
A SAT signal of 30 Hz is designated, and "11" designates prohibition of sending out the reference signal, and the identification codes DCCI and DCC2 are decoded by the decoder 6. In cases other than when prohibition is indicated, the selector 5 is controlled by the output signal of the decoder 6, and one of the three types of signals from the pulse insertion/removal circuit 4 is selected and output, and the DPLL section 2
2 (see Figure 2). Further, when the identification code is "11", the output signal of the decoder is added to the prohibition circuit 7, and the output of the reference signal is prohibited.

FIG. 4 is an explanatory diagram of the operation of the embodiment of the present invention, and (a) to
(g) shows an example of signals a- and -g of each part in FIG. 1.92MHz master clock C
As shown in (C) of the figure, the frequency dividing circuit 1
The signal a of 0.96 MHz frequency-divided by 2 is as shown in (a). If this signal a is counted 200 times by the frequency division counter 2 and the signal s is output as shown in fb) of FIG. 4, the signal d inverted by the inverter 13 in the delay circuit 3 is The signal d is applied to the clock terminal C of the flip-flop 12, and the signal S applied to the data terminal rises as shown in FIG. 4(d) and (b). is shifted by 1/2 of the period T of the mask clock C. Therefore, the output signal e of the Q terminal of the flip-flop 12 is different from the output signal of the frequency division counter 2, as shown in FIG. 4(e). , is delayed by a period τ that is 1/2 of the period of the master clock C.

This signal e and the output signal a of the frequency dividing circuit 1 are applied to the pulse insertion/extraction circuit 4, and the output signal f of the exclusive OR circuit 14 is
As shown in FIG. 4(f), since the divided pulses are output, 1 pulse is output within the period in which the signal a is counted 200 times.
The signal has more pulses, and the output signal g of the OR circuit 15
As shown in Figure 4 (phantom), two consecutive pulses are output, so the signal is one pulse less in the period in which signal a is counted 200.Therefore, there is no insertion or removal of pulses. The signal is 960KHz, exclusive OR circuit 14
The output signal f is 960x201/200=964.8
KHz, the output signal g of the OR circuit 15 is 960X199
/200=955.2KHz.

In the DPLL section 22 (see Fig. 2), the reference signal and the received S
When phase synchronizing with an AT signal, when the frequency of the reference signal is an integral multiple of the received SAT signal, a frequency divider is installed to make the frequencies for phase comparison in the phase comparator the same. be. Assuming that this frequency divider divides the frequency into 1716, when the identification codes DCC1 and DCC2 are "00", the SAT signal is 5970Hz, and the selector 5 selects 955Hz from among the three types of signals in the pulse insertion/removal circuit 4. .2KH
The signal g of z is selected and becomes the reference signal of the DPLL section 22, and this 955.2 KHz reference signal is divided into 1/16 in the DPLL section 22 to become 5970 kHz.
Since it is a Hz signal, phase synchronization can be achieved with the correct received SAT signal designated by the identification code "OO".

Also, if the identification code is "01", selector 5 will set it to 960.
A KHz signal is selected and becomes the reference signal for the DPLL section 22, and this reference signal is frequency-divided to 1/16 to 6000 KHz.
Since it is a Hz signal, it is possible to achieve phase synchronization with the received SAT signal designated by the identification code "01". If the identification code is "10", use selector 5 to select 964.
The 8KHz signal f is selected and becomes the reference signal for the DPLL section 22, and the frequency is divided by 1/16 in the DPLL section 22 to give a signal f of 6kHz.
It becomes a signal of 0.030Hz. Therefore, the identification code “10”
Phase synchronization can be achieved with the received SAT signal specified by .

The pulse insertion/removal circuit 4 includes an exclusive OR circuit 14 and an OR circuit 1
5 is shown, but it is of course possible to use other logic gate circuits depending on the logic level and the like. Also, the frequency division counter 2 is divided into 1/2 depending on the relationship between the frequency of the master clock C and the frequency of the reference signal.
A frequency division ratio other than 200 can be used.

In addition, in the above-mentioned embodiment, the S
This shows the case where it is applied to AT signal detection, but 3
The present invention can be applied to any system that transmits information based on the presence or absence of a frequency tone signal.

〔Effect of the invention〕

As explained above, the present invention converts the reference signal of a digital phase synchronization circuit when receiving and detecting a three-frequency tone signal such as a SAT signal in a car telephone system, etc.
It selectively outputs signals corresponding to identification codes that specify the frequency of three-frequency tone signals such as signals, and uses a single master clock C to generate a signal r with one pulse inserted within a predetermined period, and one pulse. By forming a signal g from which a pulse is removed and a signal a without pulse insertion/extraction using the pulse insertion/extraction circuit 4, reference signals of a plurality of different frequencies can be output without providing oscillators for a plurality of mask clocks. Since it can be constructed using a digital circuit, it has the advantage that it can be easily integrated into an integrated circuit.

In addition, in the DPLL unit 22 to which the selected reference signal is applied, the 3-frequency tone such as the SAT signal specified by the identification code DCCI or DCC2 is determined depending on whether or not it is in a state of phase synchronization with the 3-frequency tone signal such as the received SAT signal. There is an advantage that it is possible to easily identify whether it is a signal or not.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of a reference signal generation circuit of an embodiment of the present invention, and FIG. 4 is a block diagram of an embodiment of the present invention. FIG. 5 is a block diagram of a conventional example. 1 is a frequency division circuit, 2 is a frequency division counter, 3 is a delay circuit, 4 is a pulse insertion/removal circuit, 5 is a selector, 6 is a decoder, 7 is an inhibition circuit, 8 is a reference signal output terminal, 11.12 is a flip-flop 13 is an inverter, 14 is an exclusive OR circuit, and 15 is an OR circuit.

Claims (1)

[Claims] A reference signal generation circuit for detecting three-frequency tone signals, which selects and adds a reference signal corresponding to an identification code to a digital phase synchronization circuit for detecting three tone signals of different frequencies. , a frequency dividing circuit (1) that divides the master clock into 1/2; a frequency dividing counter (2) that counts the output signal of the frequency dividing circuit (1) by a predetermined number and outputs a signal; Counter (2)
) is added to the output signal of the frequency dividing circuit (1) and the delay circuit (3) for delaying the output signal of the master clock by a period of 1/2 of the period of the master clock. A pulse insertion/removal circuit (4) that forms and outputs three types of signals (pulse insertion, removal, and no insertion/removal) within a predetermined period in response to the output signal of the circuit (1), and a pulse insertion/removal circuit (4) that corresponds to the identification code. A reference signal generation circuit for detecting a three-frequency tone signal, comprising a selector (5) for selectively outputting an output signal of the pulse insertion/removal circuit (4).