JPS6380615A - System clock generating circuit - Google Patents

Abstract

PURPOSE:To easily generate plural clock pulses in diverse phase relations by supplying an oscillation output to a pulse generating circuit through a DC level varying circuit and using both leading and trailing edges of an obtained pulse which is variable in duty as a phase reference. CONSTITUTION:The oscillation output of a reference oscillator 12 is supplied to the pulse generating circuit 14 through the level varying circuit 13 and a logic circuit 15 generates clock pulses of various phases on the basis of both leading and trailing edges of the variable duty pulses which are obtained by the circuit 14 as the phase reference. The level varying circuit 13 varies the output level of the reference oscillator 12 to obtain the same effect as the relative phase shifting of the slice level of the pulse generating circuit 14, so the duty of the output pulses is variable. Consequently, the phase relation between the leading and trailing edges of the output pulses of the pulse generating circuit 14 which are important to the logical processing of the logic circuit 15 are varied at any time to extremely easily generate plural clock pulses in diverse phase relations.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system clock generation circuit that can easily generate clock pulses of various phases.

[Prior Art] A read/write memory (hereinafter referred to as DRAM) that requires a memory retention operation usually uses an address multiplex method in which the address line is divided into two and inputted in sequence. The aim is to reduce the number of signal lines required for the chip. The DRAMI shown in FIG. 6 receives address data supplied from the address counter circuit 2 via, for example, eight address lines.
RA S (Row
Add, resStrobe) or CA S (C
A strobe signal such as column address 5trobe) is required. In addition, these RAS and C
In addition to strobe signals such as AS, there is also a signal W (Write En) that is required when specifying reading or writing.
signal E N (Enable) for controlling the data input circuit 3 or signal OE (Output Enable) for controlling the data output circuit 4.
etc., must be output while maintaining a certain phase relationship. Therefore, in this example, a system clock generation circuit 6 capable of generating clock pulses corresponding to the maximum clock frequency required by the system is connected to the control circuit 5 for controlling the timing of these signals. .

[Problems to be Solved by the Invention] The system clock generation circuit 6 used in the conventional DRAM circuit 7 described above generates two-phase clock pulses with the same frequency but different phases when generating RAS and CAS. φ1. It is necessary to generate φ2. However, these two types of clock pulses φ1 and φ2 have conventionally been generated by frequency-dividing the oscillation outputs of separate reference oscillators, and therefore both lock pulses φ1 and φ2 have been generated by dividing the oscillation output of separate reference oscillators. In order to adjust the phase relationship between φ2, a complicated phase control circuit must be provided, which increases the manufacturing cost due to the complicated configuration. In systems with complex relationships, the clock pulse φ
There is a problem that the wide adjustable range of I and φ2 tends to complicate the adjustment work.

[Means for Solving the Problems] The present invention solves the above problems, and includes a reference oscillator that oscillates at an oscillation frequency matching the maximum clock frequency required by the system, and a reference oscillator that receives the oscillation output. , a level variable circuit that varies the DC level, a pulse generation circuit that slices the output of this level variable circuit based on a fixed level and converts it into a square wave, and a rise and fall of the output pulse of this pulse generation circuit. This device is characterized in that it is composed of a logic circuit that generates clock pulses of various phases using both falling edges as phase references.

[Operation] This invention supplies the oscillation output of a reference oscillator with an oscillation frequency matching the maximum clock frequency required by the system to a pulse generation circuit via a level variable circuit for variable DC level, and the duty obtained there is Using both the rising and falling edges of the variable pulse as the phase reference,
Logic circuits generate clock pulses of various phases.

[Embodiments] Examples of the present invention will be described below with reference to FIGS. 1 to 5. FIG. 1 is a circuit diagram showing an embodiment of the system clock generation circuit of the present invention, and FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG.

In FIG. 1, a system clock generation circuit 11 includes a reference oscillator 12 that oscillates at an oscillation frequency corresponding to the maximum clock frequency required by the system, and a level variable that receives the oscillation output of this reference oscillator 12 and changes its DC level. circuit 13, and a pulse generation circuit I that slices the output of this level variable circuit 13 based on a constant level and converts it into a square wave.
4, and a logic circuit 15 that generates clock pulses of various phases using both the rising and falling edges of the output pulse of this pulse generating circuit I4 as phase standards. In the case of this embodiment, as the pulse generation circuit 14,
It uses a Schmitt trigger circuit with a fixed slice level. The logic circuit 15 includes a counting circuit 16 that performs a binary counting operation using the output pulse of the pulse generating circuit 14 as an operation clock, and an AND operation between the least significant bit and the bit immediately above the counting output of this counting circuit 16. The AND gate circuit 17 and the output of this AND gate circuit 17 are both used as data inputs, and the output pulses of the pulse generation circuit 14 are supplied to the clock input terminal, one directly, and the other after having its polarity inverted by the inverter circuit 18. It consists of two D flip-flop circuits 20°21.

By the way, the level variable circuit 13 includes a coupling capacitor C that blocks the DC component included in the output of the reference oscillator 12;
This coupling capacitor C consists of a pair of voltage dividing resistors Ra and Rb connected to the voltage dividing point.While the voltage dividing resistor Ra connected to the power supply +B side is a fixed resistance, the voltage dividing resistor C is connected to the ground side. Rb is composed of a variable resistor whose resistance value can be changed arbitrarily. Therefore, by changing the resistance value of the voltage dividing resistor Rh, the DC level of the oscillation output of the reference oscillator 12 can be changed, and substantially the same effect as changing the slice level in the pulse generation circuit 14 can be obtained. That is, by operating the level variable circuit 13, the duty of the operating clock of the counting circuit 16 can be changed without changing its frequency, and both the rising and falling edges of the output pulse of the pulse generating circuit 14 can be changed. This means that various clock pulses that can be used as phase references can be generated.

Now, if we pay attention to the Q output of the D flip flow rough circuits 19 and 20, we can see that the Q output of the D flip flow rough circuit 19 rises at the leading edge of the fourth operation clock, as shown in Figure 2. On the other hand, the Q of the D flip-flop circuit 20
It can be seen that the output rises at the trailing edge of the third operating clock. That is, in this case, the phase of the Q output of the D flip-flop 19 can be adjusted by moving the rising edge of the Q output of the D flip-flop circuit 20 back and forth along with the duty through the level variable operation in the level variable circuit 13. It is. In addition, by further logically processing these two Q outputs using a logic element (not shown), it is possible to generate clock pulses of many phases, and it is no exaggeration to say that it can be freely applied to various systems. . Therefore, system clock generation circuit 1
1 is applied to a conventional DRAMI, a single reference oscillator 12 can easily generate various clock pulses with various phase relationships.

In FIG. 3, 21 is the system clock generation circuit 11.
This is a DRAM circuit to which this is applied, and the signal waveform diagrams of each part of the circuit in different modes are shown in Figures 4-5. FIG. 4 shows a DRAMI read/write cycle,
Figure 5 shows the DRAM glue, modify write,
Show the cycle. In each figure, the edge portion indicated by diagonal lines is
It is shown that the phase can be adjusted by varying the voltage dividing resistor Rh in the system clock generation circuit 11.

In this way, the system clock generation circuit 11 uses the DRA
The M circuit 21 supplies the oscillation output of the reference oscillator 12 with an oscillation frequency corresponding to the maximum frequency required for the operation of the system to the pulse generation circuit 14 via the level variable circuit 13, and the duty obtained there is variable. Since the logic circuit 15 is configured to generate clock pulses of various phases using both the rising and falling edges of the pulse as phase standards, by preparing a single reference oscillator 12, various clock pulses can be generated. Moreover, by varying the output level of the reference oscillator 12 using the level variable circuit 13, it is possible to create a relatively pulse-generating circuit! You can get the same effect as changing the slice level of 4, so
without changing the frequency of the oscillation output of the reference oscillator 12.
The duty of the output pulse of the pulse generation circuit 14 can be changed, thereby arbitrarily varying the phase relationship between the rise and fall of the output pulse of the pulse generation circuit 14, which has an important meaning in the logic processing in the logic circuit 15. Multiple clock pulses with various phase relationships can be generated very easily.

[Effects of the Invention] As explained above, the present invention transmits the oscillation output of a reference oscillator having an oscillation frequency corresponding to the maximum clock frequency required by the system to a pulse generation circuit via a level variable circuit for variable DC level. Since the logic circuit is configured to generate clock pulses of various phases using both the rising and falling edges of the pulses whose duty is variable as the digit reference, it is necessary to prepare a single reference oscillator. It is possible to generate various clocks, and by varying the output level of the reference oscillator using a variable level circuit, it is possible to obtain the same effect as relatively varying the slice level of the pulse generating circuit. It is possible to change the duty of the output pulse of the pulse generation circuit without changing the frequency of the oscillation output of the reference oscillator. This provides excellent effects such as the ability to arbitrarily vary the falling phase relationship and easily generate a plurality of clock pulses having various phase relationships.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the system clock generation circuit of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is a diagram showing the signal waveforms of each part of the circuit shown in FIG. 4.5 is a circuit diagram showing a DRAM circuit to which a conventional system clock generation circuit is applied. FIG. 4.5 is a signal waveform diagram of each part of the circuit shown in FIG. 3 in different modes, and FIG. 6 is a circuit diagram showing a conventional system clock generation circuit. 1 is a circuit diagram showing an example of a DRAM circuit to which the above is applied. 11. System clock generation circuit, 12. . , reference oscillator, 13. , , level variable circuit, 14°, pulse generation circuit, 15. ,,Logic circuit.

Claims (1)

[Claims] A reference oscillator that oscillates at an oscillation frequency that matches the maximum clock frequency required by the system, a level variable circuit that receives the oscillation output of this reference oscillator and varies its DC level, and a level variable circuit that adjusts the output of this level variable circuit based on a fixed level. A system clock generation circuit consisting of a pulse generation circuit that slices and converts into a square wave, and a logic circuit that generates clock pulses of various phases using both the rising and falling edges of the output pulse of this pulse generation circuit as phase standards. .