JPS59214319A - Delay device - Google Patents

Abstract

PURPOSE:To obtain a delay time which is affected by neither variation in ambient temperature nor variation in source voltage by providing the 2nd delay circuit which has the delay amount control signal characteristics as same as the 1st delay circuit, and detecting variation in the amount of delay and performing negative feedback control. CONSTITUTION:The 2nd delay circuit 16 which has the delay control characteristics as same as the 1st delay circuit 12 is provided. Further, the amount of delay of the 2nd delay circuit 16 is equalized to the amount of delay of the 1st delay circuit 12. Further, variation in the amount of delay of the 2nd delay circuit 16 is detected by a feedback control circuit 17, and the detection output obtained at the output terminal 18 of the feedback control circuit 17 is applied to the control terminal 19 of the 2nd delay circuit 16 to hold the amount of delay of the 2nd delay circuit 16 constant. When the 1st delay circuit 12 varies in the amount of delay with temperature, the 2nd delay circuit 16 also varies in the amount of delay at the time, but this is detected by the feedback control circuit 17 to feed a control signal back so that variation in the amount of delay is compensated.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a delay device used for generating signals with accurate relative delay times such as various timing signal generators, and particularly relates to a delay device used for generating signals with accurate relative delay times, such as various timing signal generators. The aim is to ensure that the amount does not affect the amount.

<Prior Art> In the conventional delay device, as shown in Fig. 1, a plurality of gate circuits 11 are connected in series, and the desired delay amount is obtained by the sum of the delay amounts occurring in one of the gate circuits. . In other words, in the example shown in Figure 1, three dart circuits are connected in cascade,
This is a delay device for obtaining a delay amount three times the delay time of one gate circuit 11. Such conventional delay devices have the disadvantage that the amount of delay changes with changes in ambient temperature and changes in the power supply voltage applied to the gate circuit.

<Object of the Invention> An object of the invention is to provide a delay device that can obtain a delay time that is not affected by fluctuations in ambient temperature or power supply voltage.

<Summary of the Invention> According to the present invention, a second delay circuit is provided which has the same delay amount and control signal characteristics as the first delay circuit to which a delayed signal is supplied. The feedback control circuit detects the fluctuation in delay of the second delay circuit, and transmits the detected output to the second delay circuit.
The second signal is negatively fed back as a signal to control the delay amount of the delay circuit.
The delay circuit is controlled so as to always obtain a constant delay amount, and a control signal from the feedback control circuit is supplied as a control signal for controlling the delay amount of the first delay circuit. In this way, the second delay circuit is controlled to always have a constant delay amount, and the first delay circuit is similarly maintained at the same delay amount.

<Example> Next, an example according to the present invention will be described with reference to FIG. 2 and the following drawings. In FIG. 2, the first delay circuit 12 is connected in n stages in series, one end 1 is connected to the input terminal 13, the other end is connected to the output terminal 14, and these input terminals 13 and output A desired amount of delay is obtained between the terminals 14.

The amount of delay of these first delay circuits 2 is controlled by applying a control signal to each control terminal 15, and the delay amount of these delay circuits 12 is the same. For example, as shown in FIG. 3, the delay circuit 12 has a gate 53 between the input terminal 5 and the output terminal 52.
A series circuit of resistance element 53 and gate 55 is connected, and the connection point between resistance element 54 and gate 55 is a variable capacitance diode 56. It is configured to be connected to the control terminal 15 through. The resistance value of the resistance element 54 and the variable capacitance diode 56
The amount of delay depends on the capacitance value of the variable capacitance diode 56, and the capacitance value of the variable capacitance diode 56 can be changed by a control signal applied to the control terminal 15.

In the present invention, a second delay circuit 16 having the same delay control characteristics as the first delay circuit 12 is provided.

And the delay amount Td of the second delay circuit 16 is the same as that of the first delay circuit 12.
is selected to be the same as the amount of delay. Furthermore, a second delay circuit]
6 is detected by the feedback control circuit 17, and the detection output obtained at the output terminal 18 of the feedback control circuit 17 is applied to the control terminal 19 of the second delay circuit 16. The amount of delay is maintained at a constant value.

At the same time, the detection output of the output terminal 18 is transferred to the first delay circuit 12.
is applied to each control terminal 15 as a control signal. Therefore, the first delay circuit 12 can always obtain the same delay amount as the second delay circuit 16. In this example, the second delay circuit 1
Delay amount n which is 0 times the delay amount Td of 6 is terminal 13.1
It will be obtained within 4 hours.

When the delay amount of the first delay circuit 12 fluctuates due to temperature fluctuations, the delay amount of the second delay circuit 16 also fluctuates at the same time, but this is detected by the feedback control circuit 17 and the variation in the delay amount is corrected. Since the control signal is feedback-controlled, the first delay circuit 12 is also compensated for its fluctuations, so that a constant amount of delay is always obtained.

Next, a specific example of the feedback control circuit 17 for the second delay circuit 16 will be explained with reference to FIG. The clock signal from the clock generator 21 is actually frequency-divided by the frequency dividing circuit 22,
In this example, the frequency dividing circuit 22 is a case in which an OR circuit 25 is connected to the vertical terminals of D-type flip-flops 23 and 24 as a feedback circuit, and the data input of the D-type flip-flop is taken in by a clock. There is. The Q output of the D-type flip-flop 23 is supplied to the input side of the second delay circuit 16, and is also supplied to the black terminal ck of the D-type flip-flop 26.

The Q output of the D-type flip-flop 24 is applied to the set terminal 28 of the flip-flop 27, and the second delay circuit 1
The output of 6 is applied to the recent terminal 29 of the flip-flop 27.

The Q output terminal 31 of the flip-flop 27 is applied to the data terminal of the D-type flip-flop 26.
The collector of the transistor 33 is connected to the power supply terminal 35 through the resistor 34, and the emitter and the emitter are connected to the resistor 36.
It is connected to the power supply terminal 37 through. The collector of the transistor 33 is grounded through a diode 38, and the collector is connected to the output terminal 1 through a smoothing circuit 39.
8 is connected. This output terminal 18 is connected to the control terminal 15 of the first delay circuit 12 and the control terminal 19 of the second delay circuit 16, as described above.

The operation of this feedback control circuit 17 will be explained with reference to FIG. A clock signal of, for example, 16+1 seconds with a period T1 as shown in FIG. As shown in FIG. 5B, the frequency is divided into pulses with a pulse width of T1 and a period of 3T.

The Q output of the D-type flip-flop 24 is delayed by one cycle T of the clock A, as compared to the Q output of the D-type flip-flop 23, as shown in FIG. 5C. The Q output pulse B of the flip-flop 23 is supplied to the second delay circuit 16, and is delayed by a delay time Td to become a signal as shown in the fifth diagram. The delay time Td is selected to be equal to the period T1 of the clock A.

However, as shown as pulse d1 in Figure 5, if this delayed pulse dl is ahead of pulse C, that is, the output delayed pulse d from the delay circuit 16.

When the delay amount becomes smaller than T, the flip-flop 27 is reset by the rising edge 9 of this delay pulse d1, and the flip-flop 27 is set by the pulse C immediately thereafter. Therefore flip-
The output waveform of the output terminal 31 of the flop 27 is controlled by the rising edge of Noculus C as shown in FIG. The O flip-flop 26 is an emitter-coupled logic circuit, a so-called ECL circuit, and the amplitude of its output is small, and this output becomes high level as shown at time t1 in FIG. 5F. The level is converted by the circuit 32. For example, in the figure, +15V and -5V are applied to terminals 35 and 37, respectively.
, 2V is applied, and when the input voltage to the transistor 330 becomes high level, the collector of the transistor 33 changes from +15V before the transistor 33 conducts, to the voltage drop across the diode 38 as the transistor 33 conducts. , 7V, and the collector potential changes as shown in FIG. 5G. This change in collector potential is smoothed by the smoothing circuit 39, and therefore the output of the output terminal 18 is
As shown in FIG.

controlled as follows.

Next, when the delay amount Td of the second delay circuit [6] lags behind the pulse C as shown in d2 in the fifth diagram, and the delay amount Td becomes larger than the specified delay amount Tl. The flip-flop 27 is set by the pulse CK,
Immediately after the output signal d2 of the second delay circuit 16 is reset, the output of the flip-flop 27 is read by the flip-flop 26 by the pulse B. That is, a low level is read as shown at time t2 in FIG. 5, and the output of the flip-flop 26 becomes a low level as shown in FIG. 5F. Therefore, the transistor 33 is cut off and its collector is +15VK, which is the smoothing circuit 39.
The output of the terminal 18 is smoothed by the control terminal 19 and is applied to the control terminal 19, which acts to reduce the delay amount of the second delay circuit 6. When the variation is detected by the feedback control circuit 17, the feedback amount is controlled so that the delay amount Td of The delay amount Td of the delay circuit 16 is held at a constant value T.

Modifications The delay device according to the invention can also be used, for example, by being connected in series with a cascade of logic circuits to keep the overall delay of the cascade of logic circuits constant. For example, as shown in FIG. 6, for example, 10 stages of logic circuits 41 are connected in cascade between the input terminal 13 and the output terminal 14, and two stages of first delay circuits 12 are inserted in series therewith. Ru.

On the other hand, to the second delay circuit 16, one logic circuit 42 corresponding to the logic circuit 41 is vertically connected in series by an integer fraction of the logic circuit 41, for example, five stages. The delay amount including the logic circuit 42 and the second delay circuit 16 is controlled to be constant. That is, the output of the frequency divider circuit 22 in FIG.
7 is supplied to the terminal 28 of the flip 70 tube, and
The other output is supplied to one end of the logic circuit 42, the output of the second delay circuit 16 is supplied to the terminal 29 of the flip-flop of the feedback control circuit 17, and the output of this frequency dividing circuit 22 is supplied to the terminal 29 of the flip-flop in the feedback control circuit 17. It is supplied to the clock terminal ck of the D-type flip-flop 26 in FIG. The control signal from the output terminal 18 of this feedback control circuit 17 is transmitted to the control terminal 15 of the first delay circuit 12 and the control terminal 19 of the second delay circuit 16.
supplied to

In this case, the 5-stage logic circuit 42 and the second delay circuit]6 operate so that the delay amount including the second delay circuit 16 is always constant, and the control signal for controlling the second delay circuit 16 is sent to the two stages of the first delay circuit 12. Each is supplied as a regulatory (goods) signal. When the logic circuits 41 and 42 have the same number of stages, the first delay circuit 12 and the second delay circuit 16 have the same number, and in the case of 1/n of an integer as in this example, Σ If the number of stages of the logic circuit 420 is reduced, the number of the '1st delay circuits 12 will be increased by n times the above-mentioned integer, which is twice as many in this example. The variation in the amount of delay in the cascade connection of the logic circuits 41 increases as the number of stages of the logic circuits 42 increases. Therefore, the number of stages of the first delay circuit 12 may be increased accordingly. In general, even if the logic circuits 41 and 4.2 are not the same, if they are made by the same manufacturer, the number of stages can be the same or have an integer ratio relationship. 2
If the delay circuits also have the same integer ratio, it becomes possible to always control the amount of delay between the terminals 13 and 14 to approximately the desired value.

In addition, although the logic circuits 42 are connected in cascade in this manner in FIG. 6, the result is that fluctuations in the delay amount of the second delay circuit are detected and controlled to be constant. become.

<Effects> As described above, according to the delay device of the present invention, the delay amount can be kept constant without being affected by fluctuations in the amount of delay due to temperature fluctuations or fluctuations in power supply voltage. In particular, when using a predetermined relative amount of delay, it is possible to obtain this with high precision.

[Brief explanation of drawings]

Figure 1 shows a conventional delay device. FIG. 2 is a block diagram showing an example of a delay device according to the present invention, and FIG.
The figure is a connection diagram showing a specific example of the delay circuit 12, and FIG. 4 is a logic circuit diagram showing a specific example of the feedback control circuit in FIG.
FIG. 5 is a waveform diagram for explaining the operation of FIG. 4, and FIG. 6 is a block diagram showing another example of the delay device according to the present invention. 12: First delay circuit, 13: Input terminal, 14: Output terminal, 16: Second delay circuit, 17: Feedback control circuit, 15, 1
9: Control terminal, 18: Output terminal of feedback control circuit.

Claims (1)

[Claims] (],) A first delay circuit whose delay amount is controlled by a control signal, a second delay circuit having the same control characteristics as the first delay circuit, and a variation in the delay amount of the second delay circuit is detected. A delay device comprising: a feedback control circuit that negatively feeds its output back to the second delay circuit as a control signal for controlling the amount of delay, and supplies the control signal to the first delay circuit as a control signal for the amount of delay.