JPS59128821A - Duty compensating circuit - Google Patents

Abstract

PURPOSE:To attain duty compensation independently of an input clock frequency without using components with high accuracy by bringing an output of a comparator to a pulse width control potential of a pulse generating circuit and outputting a clock having a prescribed duty from an output of the pulse generating circuit. CONSTITUTION:The (n) time slot in the (m) time slot of an input clock generates an H level having a potential V0, the (m-n) time slot generates an L level, the n/m is taken as a desired duty (k) and inputted to an n/m H level generating circuit 5. In integrating 3 an output of the circuit 5, an output of the circuit 3 goes to a potential kV0. In inputting the potential kV0 to a comparator 4 as a reference potential, the potential kV0 is compared with the output potential k'V0 of the integrator 9. A potential threshold value F equivalent to a difference of them is outputted from the output, inputted to a comparator 8, a loop circuit is formed and the potentials kV0 and k'V0 are controlled to be equal. Thus, a pulse having a desired duty (k) is outputted from the output of a pulse generator 10.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a duty correction circuit that outputs a clock to the duty in synchronization with an input clock whose duty is undefined, and which is independent of the frequency of the input clock and has high accuracy. This invention relates to a duty correction circuit that does not require the use of components.

(b) Prior art and problems Figure 1 is a block diagram of a conventional duty correction circuit, Figure 2 is a time chart of waveforms of each part in Figure 1, (2) is an input clock, and (B) is a delay circuit. (O indicates the output of the flip-flop; a in FIG. 1).

This corresponds to points b and c.

In the figure, 1 indicates a flip-flop (hereinafter referred to as FF), 2 indicates a delay circuit, and τ indicates the amount of delay.

When correcting the input clock shown in FIG. 2 (5) to a data clock as shown in (Q), the input clock is
Input to the set terminal of FI, and F at the rising edge of the input clock.
The output of F1 is set to H level, and the input clock is delayed by a time τ as shown in FIG. , and at the rising edge of the output of delay circuit 2)
The output of the circuit is set to L level to obtain a clock with a desired duty as shown in FIG. 2 (0). However, in the circuit of FIG. Therefore, a delay line with a highly accurate delay amount τ is required, and if the input clock frequency changes, the delay amount τ must be changed in order to obtain a clock with the same duty.

(c) Object of the Invention In view of the above drawbacks, the object of the present invention is to provide a data correction circuit that does not require the use of high-precision components and can correct data regardless of the frequency of the input clock. (d) Structure of the Invention In order to achieve the above object, the present invention provides a pulse width amplitude V which is synchronized with an input clock and determined by a pulse width control potential. A pulse generating circuit that generates a pulse, an integrating circuit that calculates the average potential of the output of the pulse generating circuit, and the output potential of the integrating circuit and a reference potential kvo (where k is duty).
The output of the comparator is used as a pulse width control potential of the pulse generation circuit, and a clock for the duty cycle is output from the output of the pulse generation circuit.

(e) Embodiment of the Invention An embodiment of the invention will be described below with reference to the drawings. FIG. 3 is a block diagram of a data-tie correction circuit according to an embodiment of the invention, and FIG. 4 shows various parts of the circuit of FIG. 3. (3) is the input clock, (B) is the input clock slightly delayed and inverted by the delay circuit 6, (C') is the output of the AND circuit 7, and (D) is the time chart of the waveform. The potential across the capacitor C, (6) indicates the output clock, and the third
These correspond to points a, b, c, d, and e in the figure.

Further, the threshold voltage F in FIG. 4(2) is the output potential of the comparator circuit 4 and corresponds to point f in FIG. 3.

In the figure, 10 is a pulse generation circuit, 3 and 9 are integration circuits, and 4.8
5 is a comparator, 5 is an n/mH level generation circuit that generates an H level in n time slots out of m time slots, 6 is a delay circuit, 7 is an AND circuit, Tr is a transistor, c, c
,, ct is a capacitor, R, R+.

R1 is the resistance, and vCC is the DC voltage.0'Figure 4 (2)
The input clock shown in FIG. 4 is input to the AND circuit 7 and also to the delay circuit 6, and is slightly delayed and inverted as shown in FIG. 4(B) before being input to the AND circuit 7. Then AND circuit 7
The output of the transistor Tγ emits a pulse synchronized with the input clock having a very narrow pulse width as shown in FIG. The transistor Tγ is not conductive when the input pulse is at H level, and sets the potential of the capacitor C charged with the voltage Vcc to 0. When the pulse input to the transistor Tγ becomes L level, the transistor Tγ becomes open and the capacitor C is charged with the voltage Vcc. Therefore, the potential of the capacitor C is input to the comparator 8 in the form of a sawtooth pulse as shown in FIG. The other input of the comparator 8 receives the threshold potential F of the output of the comparator 4, and the comparator 8 compares the potential of the sawtooth pulse with the threshold potential F. As shown in Figure 4 ■, if the potential of the sawtooth pulse is higher than the threshold potential F, the potential v
If it is 0, if it is lower than the threshold potential F, it becomes 0 level. When the pulse shown in FIG. 4(g) is integrated by the integrating circuit 9, the output potential is k'Vo, where the duty of the pulse shown in FIG. 4(g) is 2'.

- In the universal clock, n time slots out of m time slots have a potential of V. The FIL-n time slot generates an H level, and the FIL-n time slot generates an L level, which is input to the n/mH level generation circuit 5 with a desired duty of n/m. When the output is integrated by the integrating circuit 3, the output of the integrating circuit 3 becomes a potential of kVo. The potential of this kVo is input to the comparator 4' as a reference potential. The comparator 4 compares this reference potential kVo with the output potential k'Vo of the integrator 9, outputs the potential threshold potential F of the difference from the output, and inputs it to the comparator 8 to create a loop circuit. Potential kVo and potential 'V. are controlled so that they are equal. By this control, the output of the comparator 8, that is, the pulse generating circuit 10, outputs a pulse with a desired duty. In the case of Figure 3, it is sufficient that the time constant determined by the capacitors C, Ct and Rt of the integrating circuits 9 and 3 is sufficiently large compared to the period of the input clock, and in the circuit of Figure 3, the data is determined. However, since it does not depend on the accuracy of each component and there is no part particularly affected by the frequency of the input clock, it is independent of the frequency of the input clock and there is no need to use high precision components.

(f) Effects of the Invention As explained in detail above, according to the present invention, there is an effect that high-precision parts are not required and a duty correction circuit that is independent of the frequency of the input clock can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional duty correction circuit, FIG. 2 is a time chart of waveforms of each part in FIG. 1, FIG. 3 is a block diagram of a duty correction circuit according to an embodiment of the present invention, and FIG. 4 is a time chart of waveforms at various parts in FIG. 3. FIG. In the figure, 1 is a flip-flop, and 2 and 6 are delay circuits. 3.9 is an integration circuit, 4.8 is a comparator, 5 is an n/mH level generation circuit, 7 is an AND circuit, 10 is a pulse generation circuit,
Tr is a transistor, C9C+, Ct is a capacitor =
R9Rt-Rt indicates resistance. v-1 figure number? closed

Claims (1)

[Claims] In a duty correction circuit that outputs a duty clock synchronized with an input clock, the amplitude V in a pulse is synchronized with the input clock and determined by a pulse width control potential. A pulse generating circuit that generates a pulse of 1. A duty correction circuit characterized in that the control potential is used as a control potential during a pulse of a pulse generation circuit, and a clock is output with a duty equal to the output of the pulse generation circuit.