GB2127243A - Variable frequency oscillator - Google Patents

Abstract

A variable frequency oscillator comprises a first phase-locked loop (204; 206 or 207; 209) including a first voltage controlled oscillator (209), a second phase-locked loop (214, 215, 218) including a second voltage controlled oscillator (218) having the same constants as the first voltage controlled oscillator, and an oscillator (202) for generating a stable pulse train. The arrangement is such that, in operation, the first phase-locked loop is synchronised with a sequence of input data (at 219), the second phase-locked loop is synchronised with the pulse train from the oscillator (202) and the first voltage controlled oscillator (209) is stabilized with the control voltage (added at 208) which is applied to the second voltage controlled oscillator (218). The arrangement is used to derive window pulses for reading data reproduced from a floppy disk. <IMAGE>

Description

SPECIFICATION Variable frequency oscillator This invention relates to variable frequency oscillators.

Although the present invention is primarily directed to any novel integer or step, or combination of integers or steps, herein disclosed and/or as shown in the accompanying drawings, nevertheless, according to one particular aspect of the present invention to which, however, the invention is in no way restricted, there is provided a variable frequency oscillator comprising: a first phase-locked loop including a first voltage controlled oscillator; a second phase-locked loop including a second voltage controlled oscillator having the same constants asthefirstvoltage controlled oscillator; and an oscillator means for generating a stable pulse train, the arrangement being such that, in operation, the first phase-locked loop is synchronised with a sequence of input data, the second phase-locked loop is synchronised with the pulse train from the oscillator means, and the first voltage controlled oscillatorinthefirst phase-locked loop is stabilised by a control voltage applied to the second voltage controlled oscillatorinthesecond phase-locked loop.

Thevariable frequency oscillator may include a ring oscillatorfor controlling the frequency of oscillation of each voltage controlled oscillator by controlling the currentflowing into the ring oscillator.

The variable frequency oscillator may include a digital circuitforcounting pulses generated at regular intervals and delaying the pulses by a predetermined period of time to delay the sequence of input data before application to the first phase-locked loop.

The variablefrequency oscillator preferablycom- prises shifting means for shifting the phase of each output pulse from the first voltage controlled oscillator in the first phase-locked loop by 90% a flip-flop circuit arranged to be set bythe input data and reset by the output from the shifting means and a circuit arranged to be triggered onthetrailing edge ofthe outputfromtheflip-flopcircuitfordelivering a pulse having a predetermined pulse width.

The invention is illustrated, merely byway of example, in the accompanying drawings, in which: Figure 1 is a block diagram of one embodiment of a variable frequency oscillator according to the present invention; Figure 2(a) is a block diagram of a counter circuit of the variable frequency oscillator of Figure 1; Figure 2(b) is a circuit diagram of part of the variable frequency oscillator of Figure 1; Figure 3(a) and 3(b) illustrate recording formats of a floppy disk; Figure 4 is a blockdiagram of a conventional variable frequency oscillator; Figure 5 is a timing chartfor illustrating and comprising the operations of the conventional vari abiefrequency oscillator of Figure 4 and the variable frequency oscillator of Figure 1; and Figure 6 is a detailed circuit diagram of the conventional variable frequency oscillator of Figure 4.

Before describing a conventional variablefrequency oscillator (VFO) for floppy disks, formats for data writing for floppy disks and thefunctionsfor such a VFO will be described. Presently, IBM format and similarformats are nearly exclusively used as formats forfloppy disks and so these formats are described below.

Referring to Figure 3(a) and 3(b),there are shown a data pulse train read from a floppy disk 20 cm (8 inch) in diameter by means of a floppy disk drive (FDD).

Figure 3(a) shows a single density (FM) recording on the disk. In this case, one clock pulse is admitted every 4 ps of 1 bit cell of the fetched data pulse train. AVFO produces data window waveforms as shown from the data pulse train, and then the window waveforms are AN Ded with the data pulse train to produce separate data pulses. Figures 3(b) shows a double density (MFM) recording, in which onlywhen neighbouring bits are O's is a clock pulse admitted. In this case, a VFO produces data window waveforms from the fetched data pulse train, and then the window waveforms are AN Ded with the data pulse train for reproduction of data. When a floppy disk 12.7 cm (5 inch) in diameter, called a mini-floppy disk, is used the period of bit cells is twice that of a 20 cm (8 inch) floppy disk.

When the pulses of a data pulse train read from the floppy disk drive are located precisely in standard positions within bit cells as shown in Figures 3(a) and 3(b), data window waveforms can be produced by, for example, a one-shot multivibrator with relative ease.

In reality, however, there arises a possibility that each pulse is shifted from its standard position by about f 350 nswith a 20 cm (8 inch) standard floppy disk and + 700 ns with a mini4loppy disk at worst. This phenomenon is known as peak shift and is caused by interference between neighbouring waveforms when data is read.AVFO acts to producecorrectdata window waveforms from a fetched data pulse train accompanied by such peak shift and to derive only data pulses.

An example of a conventional VFO is described in detail in "Interface", July, 1979. Figure 4 shows this conventional VFO in block diagram form, in which data read from a floppy disk drive is applied to a terminal 401 and admitted to phase comparator404 through a one-shot multivibrator403. Avoltagecontrolled oscillator (VCO) 408 produces window waveforms which are supplied to the phase compara tor 404 through a gate circuit 410 for phase comparison with the output from the multivibrator403.The output from the comparator 404 is fed to a first low-pass filter 406 or a second low-pass filter 407 via a switching circuit 405 to remove the high frequency components, and then the signal is fed to the VCO 408, so that the frequency of oscillation ofthe VCO 408, that is, the frequency and phase of the window signal, is controlled by the phase difference between those signals. In particular, the phase comparator 404, the filter 406 or 407 and the VCO 408 form a phase-locked The drawings originally filed were informal and the print here reproduced is taken from a later filed formal copy. loop, and the circuit does not respond to rapid changes in data signals due to peak shift, the data signals being fetched for application to the terminal 411.Rather, it responds to slow changes and produce a signal which is synchronised with the input signal and the phase of which is always in step with that of the input signal. The system includes both the first low-pass filter 406 responding quickly to its input signal or having a high cut-offfrequency and the second low-passfilter407 responding slowing to its input signal or having a low cut-offfrequency. The two filters are alternatively used by the operation ofthe switching circuit 405 for the reason described hereinafter.

Anyfloppy disk has evenly spaced pulses, called syncfields, written in the head portions of sectors for synchronisation. Therefore, no peakshifttakes place in these fields. Thus, the first filter 406 responding quickly is used forthe fields and a synchronisation with sync bits is effected rapidly. Thereafter, when fields of recorded data are to be treated, the filter 406 is changedovertothefilter407,which responds slowly to its input signal, so thatthe system will not respond to changes in the interval of pulses attributed to peak shift. The signal forthe changeover operation can be supplied from a processor or a floppy disk controller of the system using the floppy disk drive and is applied to aterminal 402.Next, the operation ofthe one-shot multivibrator403, a gate circuit 410 and an output waveform shaping circuit 409 having an output terminal 412 are described by refering to the time chart of Figure 5.

The multivibrator 403 is triggered into action on each rising portion of data pulses (waveform (a) of Figure 5) read from the floppy disk drive and delivers pulses having a pulse width that is one-fourth the duration of one bit cell (waveform (b) of Figure 5).

These pulses are applied to the phase comparator 404 at all times, and during syne fields they are compared in phase with window waveforms (waveform (c)). The multivibrator403 serves to adjustthe timings of the associated signals such that each data pulse read by the floppy disk drive is broughtto the centre of each window. During datafields,the pulse interval between fetched waveforms sometimes becomes twice or half ofthe periods of windows and so direct comparison between the outputfrom the multivibrator 403 and the window waveforms is impossible.The gate circuit410 actsto select the signal applied to the comparator 404 based on the syncfield signal fed to the terminal 402 and consists of a switch and a flip-flop which is set on the rising portion of each data pulse as shown in waveform (d) and reset on the transition points of each window waveform (waveform (c)), that is, the leading edge and the trailing edge of each pulse. The switch allows the output signal from theflip4lop to be applied to the comparator 404 during data field periods. In this way, during these periods the waveform (b) is compared in phase with each falling portion of the waveform (d) to prevent occurrence of comparison error due to missing pulses.The output waveform shaping circuit 409 brings each fetched pulse to the centre of each window, moves the pulses and shapes them, so thatthe circuit delivers waveforms as shown by waveform (3). The shaping circuit is made up of a delay circuit such as a one-shot multivibrator.

Figure 6 is a circuit diagram of the conventional VFO shown in Figure 4. The blocks surrounded by phantom lines are denoted bythe same reference numerals as those of Figure 4 exceptfor a low-pass filter 601 which does not possess entirely individual circuits to have both rapid and slow responses, but rather a portion is used forthe rapid and slow responses in common in this filter.

The conventional VFO has some disadvantages.

First, it is difficult to fabricate the oscillator in the form of a semiconductor integrated circuit as can be seen from Figure 6. The circuitry shown in Figure6 requires 19 resistors and 6 capacitors as discrete components.

It is possible even with the prior arttechniqueto fabricate these components on one chip by attaching the discrete components to the outside surface of the chip and fabricating the other components in semiconductor integrated circuit form. However, features inherent in semiconductor integrated circuitry cannot be fully derived from such a construction. Specifically, the space to mount components cannot be made small. A large number junction points to not assure a good reliability. The number of steps for mounting components and the cost of fabricating the circuitry cannot be reduced. A considerable limitation is imposed on the design of such a chip for a semicon ductor integrated circuit.

In particular, when connections are madeto exter nallyattached components from the inside of a semiconductor integrated circuit chip, a considerably larger chip area is needed than the case where no connections are required, because padsforconnection and transistors in the outer buffer circuits are several tens of times as large as those of a device dispensing with external connection. Furthermore, the cost of packaging the integrated circuit is increased.

Another disadvantage ofthe conventional VFO is that adjustments are necessary after assembly. This is caused bythefactthat stable and precise VFOs are not available.

Referring now to Figure 1 there is shown one embodiment of a variable frequency oscillator (VFO) according to the present invention. The VFO includes a counter circuit 201, a crystal oscillator 202, a phase comparator 204, a switching circuit205, low-pass filters 206,207, an adder 208, a phase-shiftcircuit 210, a differentiating circuit 211, a frequency divider circuit 212, a second phase comparator circuit 214 and a second adder 216. The counter circuit 201 is set bythe leading edge of each data pulse,which is read from a floppy disk drive (not shown) and applied to a terminal 219, and countsthe pulses generated by the crystal oscillator 202 until a certain count is reached, whereupon the counter 201 is reset and delivers a pulse. The switching circuit 205 selects one of the filters 206,207 depending on whether a sone field data signal or a data field signal is applied to a terminal 220. The filters have different passbands, and when the sync field signal isto be passed,thefilter 206 having a broader passband is selected. The adder 208 forms the sum of the output from either the firstfilter 206 or the second filter 207 and the output from a third low-pass filter 205 and applies itto the control terminal of a voltage controlled oscillator (VCO) 209 to control the frequency of oscillation ofthe VCO 209. The differentiating circuit 211 produces a narrow pulse when the trailing edge of the signal from a gate circuit 203 is reached.

The adder 216 has the same characteristics as the adder 208 and adds a reference voltage Vr generated bya reference voltage source 217 to the output from thefilter 21 to control asecondvoltage-controlled oscillator (VCO) 218, which is designed so as to have the same characteristics as the VCO 209. Thus the VFO is comprised of a first phase-locked loop, which containsthe phase comparator 204,thefilter 206 or the filter 207, and the VCO 209, and a second phase-locked loop, which contains the second phase comparator 214, the filter 215 and the VCO 218.

Q In operation ofthe VFO constructed as described above, the second phase-locked loop is locked in step with the outputsignal frequency divider circuit 212, which dividesthe output frequency ofthe crystal oscil lator 202 down into a lower frequency and delivers a signal ofthe free-running frequency needed by the VCO 209. Of course, in a state where the second phase-locked loop is locked, the frequency of one input signal to the comparator 214 is equal to that of the other signal and the phase difference between the two signals is kept constant. In otherwordsthe VCO 218 also oscillates at the free-running frequency.Even if the constants of the VCO 218 vary due to changes in the powersupplyvoltage orambienttemperature ageing, scatter in the constants ofthe components or other factors, the outputfrom the filter 215 is controlled so that the VCO 218 always oscillates at the free-running frequency by virtue of the action of the negative feedback loop.

When the reference voltage Vr,for example half the power supply voltage, is applied to one inputterminal of the adder 216 and the output from the filter 215 is applied to one inputterminal of the adder 208 as shown in Figure 1 the VCO 209 should oscillate at the free-running frequency at the time the outputfrom the filter 206 orthe filter 207 equalsthe reference voltage Vr. As long as the adders and the VCOs are symmetri cally accurate, respectively, a VCO entirely free from drift and initial deviation can be attained even if such VCOs are employed that could otherwise not be put into practical use due to their instability. This VCO oscillates atthefree-running frequency when the control voltage Vr is applied. The configuration described so far can stabilisethe operation of the VCO 209 in thefirst phase-locked loop.

Referring nextto Figure 2(a), the counter circuit 201 is shown in detail. The counter circuit 201 receives a fetched data pulse train (waveform (a) of Figure 5) and delivers pulses whose pulse width is one-fourth the length of 1 bit cell (waveform (b)), that is, flip-fiops 302, 303 and a gate 304 produce a short pulseto reseta frequency divider circuit 301 and set a flip4lop 305 on the leading edge of each fetched data pulse which is applied to a terminal 306. Aterminal 308 is connected to the crystal oscillator 202 whose output frequency is divided into a lower frequency bythe divider circuit 301. When the divider circuit 301 receives pulses of the lower frequency, it delivers a carrier to set a fli p-flop 207.

The configuration described thus far offers a oneshot multivibrator stably producing pulses having an accurate pulse width. Also, as can be understood by comparison with the prior art VFO, the novel configuration does not require resistor R1 and capacitor C1. The output from the counter circuit 201 is applied to the phase comparator 204, and it is compared in phase with the output waveform (c) of Figure 5 from the VCO 209 and with the waveform (d) during sync field and data field periods, respectively, by the action of the gate circuit 203. The resultant phase difference signal is supplied to the filter 206 responding quickly during syncfield periods and to the filter 207 responding slowly during data field periods bythe action ofthe switching circuit 205 to filter out wanted high frequency components.The outputfrom either filter is applied to the adder 208 to control the frequency of oscillation of the VCO 209. The other inputto the adder 208 comes from the second phase-locked loop and causestheVCO 209 to oscillate atthefree-runningfrequencywhenthe outputfrom the filter 206 orthefilter 207 is the reference voltage Vr as described previously. The output voltage from the filter 206 or the filter 207 assumes a value of Vr under steady state by making the free-running frequency equal to the windowfrequency.The absolute value of the current flowing into, or out of, the low-pass filter can beinvariablykeptconstantbysettingthevoltage Veto the average value ofthe output voltage derived when the output from the com parato r 204 assu mes a logic high state and the outputvoltage derived when the outputfrom the comparator 204 assumes a logic tow state. Further, since the output from the filter can be brought quite close to the voltage Vr under steady state, use of a charge pumping circuit connected to the output ofthe comparator 204 dispenses with active filters used in conventional devices as low-pass filters.

This makes itvery easyto fabricate the VFO in the form of an integrated circuit. The output from the VCO 209 is fed back from the comparator 204 via the gate circuit 203 to form a loop. Thus stable and precise windows can be formed.

In the conventional VFO, a one-shot multivibrator is used as the output waveform shaping circuit 409 to delay each waveform (d) in Figure 5 so that it is moved to the centre of each window (see waveform (c)). The embodiment of the present invention shown in Figure 1 shapeswaveforms in a different way. In particular, the differentiating circuit 211 produces short pulses (waveform (g) of Figure 5) on the trailing edge of the waveform (d) and can easily be fabricated by including theflip-flops 302,303 and the gate 304 of Figure 2(a).

The fetched data pulse train takes the waveform (g) of Figure 5, and it is not passed through a delay circuit, thus dispensing with resistors R16, R17 and capacitors C5, C6 contrary to the shaping circuit 409 as shown in Figure 6(a). In the embodiment of the invention, as each fetched data pulse (waveform (g)) is broughtto the centre of each window, the phase-shift circuit 210 shifts the phase of the windows an angle of 90 or 2700 (waveform (f) of Figure 5). This phase shift circuit can be readily constructed by forming a 1/2 frequency divider circuit by a master-slave flip4lop, because the phases ofthe output waveforms of the master and slave flip-flops are 900 out of phase.In the convention al VFO and as shown in Figure 6 a 1/2 frequency divider circuit 602 is incorporated into the VCO 408 to setthe duty cycle ofthe output waveforms to 50% . Th 3 waveforms (c) and (f) of Figure 5 can be readily obtained by feeding the outputfrom the master flip-flop back to the gate circuit 203 and supplying the inverted output ofthe slave flip4lop to the terminal 221.

All the components of the VFO of Figure 1 except for the low-pass filters 206,207,215, adders 208,216, reference voltage source 217, VCOs 209,218 and the crystal oscillator can be made as digital circuits.

Further, any part externally attached to that semicon ductor integrated circuit is not required. In addition VCOs do not need high accuracy or stability as described above.

The circuit stages beginning from the phase comparator 204 and ending with the VCO 209 as well as the circuit stages beginning from the phase comparator 214 and ending with the VCO 218 can be made simpler and can be fabricated in the form of an integrated circuit. Referring nextto Figure 2(b), the phase comparators 204,214, switching circuit 205, low-pass filters 206,207,215, adders 208,216, VCOs 209,218 and the phase-shift circuit 210 are shown in detail. The blocks surrounded by phantom lines are denoted by the same reference numerals as the components of Figure 1 for correspondence to them exceptthata low-pass filter 309 corresponds to both the filters 206, 207. The filter 309 includes a portion equivalent to the portion common to both filters 206,207.Also, because the phase-shift circuit 210 can be attained only by the slaveflip4lop ofthe circuit 305 in the VCO 209 as described already, theflip4lop 305 is divided into two bya phantom line. Since the phase com parator 21 4 and the adder 216 have exactly the same internal configurations as the comparator 204 and the adder 208, respectively, they are not shown in detail. Also, as the VCO 218 is the same as the combination of the VCO 209 and the phase-shift circuit 210, its circuitry is also not shown.

Terminals 301,302,303,304 are connected to the counter circuit 201, gate circuit 203, frequency divider circuit 212 and one input of the gate circuit 203, respectively. The combination of AND gates G1, G2to which transistors T1, T2 are connected and the combination of AND gates G3, G4towhich transistors T3, T4 are connected are alternatively enabled, depending on whether sone field signal or data field signal is applied to a terminal 220.This causes the combination ofthe transistors T1, T2 and the combination ofthe transistors T3, T4to conduct selectively whereby the phase difference signal is alternately transmitted to a quick response low-pass filter consisting of resistors R201, R204 and a capacitor C202 and a slow response low-pass filter consisting of resistors R202, R203, R204 and capacitors C201, C202.The drain currents of transistors T16,T17 are summed in the adder circuits 216,208, and then the resultant current is converted into a voltage by a transistorT5to control the VCO 209. lftransistors T5, T6,T7, T8, ... Tg, T17, T18, Tag, T20, ... T21 have the same constants, then their drain current will be equal to that of the transistorT5 in the saturation region.In other words, the drain current ofthesetransistors can be controlled by the gate voltage of the transistors T16,T17. Tra nsistors T, ol Tlar T11, T14 ... T12, T15 constitute inverters and their odd-numbered stages are connected togetherto form ring oscillators whose frequency of oscillation is controlled as the current fed to them is controlled by the gate voltage of the transistorsT16, T17. For this purpose, transistors limiting current are connectedto the sources of those transistors. The output of the ring oscillators is fed to the flip-flop 305 via a buffer306, so that the frequency is halved and the duty cycle is modified.No additional phase shift circuit is required by utilising terminal 304 of the masterflip-flop of the circuit 305. Since the VCO 209 is stabilised in the manner described previously, it is assured that even ring oscillators whose instability could otherwise not be accepted can be employed. The ring oscillators can be made simply by connecting an odd number of inverter stages to one another, and the ring oscillators do not have parts, such as capacitors, which are required to be externally attached to the semiconductor integrated circuit, and therefore they are quite easy to fabricate in the form of a semiconductor circuit. A reference voltage source 217 has resistors R206, R207 for dividing the powersupplyvoltage down to a reference voltage.If the relative accuracy between the resistances of both resistors is good, the derived voltage will be accurately a desired fraction of the power voltage, thereby they easy to incorporate into a semiconductor integrated circuit. Of course, a voltage generated using, for example, zener diodes can equally well be used. The current 1o of a current source 307 is converted into a voltage by a transistorT22 to control the gate voltages of transistors T26, T28 for limiting the channel currentsofthetransistorsT2e,T28.

If the transistors T22, T26, T28 have the same constants, the currents will be limited to lo. AtransistorT23 converts the current lotto a voltage to limit the channel current of a transistor T24. If transistors T25, T23, T24 have the same constants, then the currents will be also limited to c Transistors T25, T27 form a switch called a charge pumping circuit which has the same function as the combination ofthetransistorsT1,T3andthe combination ofthe transistors T2, T4 in the switching circuit 205. The phase difference signal from the comparator 214 causes a capacitor C203 to be charged or discharged to control the voltage applied to the second adder 216. As a result, the output phase ofthe VCO 218 is advanced or retarded.

The low-pass filter 215 consists ofthe currentlimiting transistorT24OrT28, the resistor R205 and the capacitor C203. Because the currents of the transistors T24, T28 are limited to 1O,the quantity of charge conveyed from the transistorT25 orT27 to the resistor R205 and the capacitor C203 is not affected by changes in the potential across the terminals of the capacitor C203, that is, the input voltage of the adder 216. That is, the potential across the capacitor C203 can be varied substantially due to changes in constants of the VCO 218, but changes, for example, in the response constant ofthe second phase-locked loop caused thereby is held to a minimum.

It will be noted by comparing Figure 1 with Figure 2(b) thatthe points from which signals are derived for application to the adders 208,216, respectively, are different from each other. The resistor R205 is inserted to stabilise the operation of the second phase-locked loop and so this resistor can be neglected when the circuit of Figure 2(b) is discussed in principle. As such, the two points may be deemed to be the same.

It is to be understood that nearly all components of Figure 2(b) can be fabricated in the form of a complementary MOS integrated circuit. Of course, bipolar or other semiconductor devices may be used with equal utility. The remaining seven resistors and three capacitors are also incorporated into an integrated circuit in the following fashion. First, the resistors R206, R207 can be incorporated into the integrated circuit only iftheir resistances have a sufficient relative accuracy. The accuracy required for the capacitor C203 and the resistor R205 is relatively low and so these are also capable of being incorporated into the integrated circuit. Likewise, the accuracy necessaryforthe resistors and capacitors in the filter 309 is not so high and hence they can be incorporated into the integrated circuit.However, the constant of the filter must be varied depending on the kind, that is the dimensions and so on, of the floppy disk connected and so it may be desired that they are attached to the integrated circuit externally. The oscillation frequency of each of the VCOs 209,218 can be increased by the reciprocal of the frequency division factor of a frequency divider circuit connected to the terminal 213 of Figure 1 and the time constant ofthe filter 215 can be reduced by connecting all ora portion ofthe frequency divider circuit 212 in series with the terminal 213 and connecting the crystal oscillator 202 directly orthe remaining portion of the divider circuit 212 with the second phase comparator 214.This permits the miniaturisation ofthe capacitor C203, the resistor R205 and other elements, whereby the VFO circuit of Figure 1 can be fabricated in the form of an integrated circuit with greater ease.

The VFO of Figure 1 requires an expensive and stable oscillator circuit, such as the crystal oscillator 202. The conventional VFO of Figure 4 does not need such an oscillator circuit when data is read by the floppy disk drive, but needs it when data is written. In the present invention, the crystal oscillator used for the writing operation can also be used for the reading operation and, consequently, neither complication of the configuration nor increase in manufacturing costs is introduced, thus resulting in no problem. One might suppose that the VFO of Figure 1 is more complex than the conventional VFO of Figure 4 and that the manufacturing cost is increased by the addition of a second phase-locked loop. In fact, however, the opposite is the case.Since externally attached parts are reduced substantially, the area occupied by bonding pads for access to the integrated circuit as well as the area required for buffer transistors connected to the input and output can be reduced to a great extent. These occupy a major portion of a semiconductor integrated circuit, and the area occupied by them is usually considerably largerthan the whole area of the second phase-locked loop. Therefore, it is possible to reduce the cost. The substantial reduction in the number of externally attached parts further permits decrease in the cost of parts, assembly cost and the packaging space and increase in reliability. Furthermore, VCOs dispense with adjustments during assembly operation because the free-running frequency is adjusted automatically.

As described so far, in accordance with the present invention, the addition of a second phase-locked loop permits stabilisation of components including VCOs and so accuratelyfabricated components are not required, so that the components can be fabricated in the form of a semiconductor integrated circuit with greater ease. Also, the circuit can be fabricated in the form of a digital circuit by making the best use of the reference frequency signal generated by the crystal oscillator and replacing a conventionally used oneshot multivibratorwith a counter circuit. The result is thatthe circuit is made more accurate and the number of components is reduced.

Avariable frequency oscillator circuit according to the present invention can be formed into a semicon ductor integrated circuit with greater extent than the conventional VFO, thus permitting simplification of design of instruments and apparatus, increase in reliability of apparatus, decrease in the number of steps for assembly, miniaturisation of apparatus and reduction in the manufacturing cost.

It isto be noted thatthe present invention can find application in VFOs for hard disks and other phase locked loops in the form ofsemiconductorintegrated circuits.

Claims (7)

1. Avariable frequency oscillator comprising: a first phase-locked loop including a first voltage controlled oscillator; a second phase-locked loop including a second voltage controlled oscillator having the same constants as the first voltage controlled oscillator; and an oscillator meansforgenerating a stable pulse train, the arrangement being such that, in operation, the first phase-locked loop is synchronised with a sequence of input data, the second phaselocked loop is synchronised with the pulse train from the oscillator means, and the first voltage controlled oscillator in the first phase-locked loop is stabilised by a control voltage applied to the second voltage controlled oscillatorinthesecond phase-locked loop.

2. Avariablefrequency oscillator as claimed in claim 1 including a ring oscillatorfor controlling the frequency of oscillation of each voltage controlled oscillator by controlling the current flowing into the ring oscillator.

3. Avariablefrequency oscillator as claimed in claim 1 or 2 including a digital circuit for counting pulses generated at regular intervals and delaying the pulses by a predetermined period oftime to delay the sequence ofthe input data before application to the first phase-locked loop.

4. Avariable frequency oscillator as claimed in any preceding claim comprising shifting meansforshift- ing the phase of each output pulse from the first voltage controlled oscillator in the first phase-locked loop by 90 , a flip-flop circuit arranged to be set by the input data and reset by the outputfrom the shifting means, and a circuit arranged to be triggered on the trailing edge ofthe output from the flip4lop circuit for delivering a pulse having a predetermined pulse width.

5. Avariable frequency oscillator substantially as herein described with reference to Figures 1,2(a) and 2(b) ofthe accompanying drawings.

6. Avariablefrequency oscillatorfora floppy disk, theoscillatorcomprising: a first phase-locked loop including a first voltage controlled oscillator; a secon phase-locked loop including a second voltage controlled oscillator having the same constants asthefirst voltage controlled oscillator; and an oscillator means for generating a stable pulse train, the first phase locked loop being synchronised with a sequence of data read from the floppy disk, the second phaselocked loop being synchronised with the output pulses from the oscillator means, thefirstvoltage controlled oscillator in the first phase-locked loop being stabilised bythe control voltage applied to the second voltage controlled oscillator in the second phase-locked loop.

7. Any novel integer or step, or combination of integers or steps, hereinbefore described, irrespective ofwhetherthepresentclaim iswithinthe scope of, or relates to the same or a different invention from that of, the preceding claims.