JP3547983B2 - Pulse width control circuit and disk recording control circuit - Google Patents

Description

【００２３】
一方、ＶＣＯ４では、上述したようにローパスフィルタ８からの制御電圧Ｖｔにより各遅延セルの遅延量ｄｔが決定され、初段の遅延セル４０に入力された信号ｄｔ０は、図４に示すように各遅延セル４０で順次ｄｔづつ遅延されていく。そして、最終段の遅延セル４１では信号が反転され、この反転信号が折り返し遅延ｄαの後に初段に帰還される。つまり、折り返し遅延ｄαがｄｔに比べて十分小さいとすれば、ＶＣＯ４の周期Ｔの半周期Ｔ／２は、遅延量ｄｔを遅延セル４０の段数Ｄ分だけ加算した長さとなる。従って、遅延量ｄｔは式（２）で表される。
【００２４】
【数２】

【００２５】
ここで、周期Ｔは１／ｆ１であって、上述したようにＰＬＬ回路３がロックすると式（１）が成立するので、ロック状態では、遅延量ｄｔは式（３）で表される。
【００２６】
【数３】

【００２７】
つまり、ＶＣＯの遅延セル段数Ｄと分周比Ｍ，Ｎを決定すれば、遅延セル４０の遅延量ｄｔは、基準信号ＲＦＣＫの周波数ｆ０のみに依存する一定値となる。
ところで、図２に示す回路では、上述したようにディレイライン２を構成する遅延セルはＶＣＯ４の遅延セルと全く同一の構成であり、しかもディレイライン２中の遅延セルに供給される制御電圧もＶＣＯ４の遅延セル４０に供給される制御電圧Ｖｔと全く同一である。このため、ディレイライン２中の遅延セルの遅延量は、ＶＣＯ４の遅延セル４０の遅延量ｄｔと全く同一となり、ＰＬＬのロック時には基準信号周波数ｆ０に依存した一定値となる。
【００２８】
ディレイライン２は、入力信号ＳＩＮを遅延セル４０で順次遅延して、セレクタ２０により所望の段の遅延出力を選択して、遅延信号ＳＯＵＴとして出力する構成であり、この各遅延セル段の遅延量ｄｔがＰＬＬロック時には一定値となるので、ディレイライン２においてセレクタ２０から出力する遅延信号の遅延量も所望の一定値となる。つまり、このディレイライン２では、製造時の調整は不要となり、且つＰＬＬ回路３で保証される精度で遅延量を設定でき、このためｐｓｅｃオーダーでの高精度の設定が可能となる。しかも、ＰＬＬでは電源変動や温度変動に対しても保証されるので、ディレイライン２の遅延量もこれら変動の影響を受けなくなる。
【００２９】
また、基準信号ＲＦＣＫの周波数ｆ０や分周比Ｍ，Ｎを変更するだけで、遅延量ｄｔを用意に変更できるので、ディレイライン２の分解能の設定が容易となる。
たとえば、ＶＣＯ４の段数Ｄが「１６段」である場合、分周比Ｍ，Ｎを各々「２」とし、ｆ０を「１７．２８ＭＨｚ」とすれば、式（３）より遅延量ｄｔは「１．８１ｎｓｅｃ」となる。そして、分周比Ｍ，Ｎを各々「４」に変更し、ｆ０を「３４．５６ＭＨｚ」に変更すれば、式（３）より遅延量ｄｔは「０．９０ｎｓｅｃ」とｐｓｅｃオーダーの分解能となる。
【００３０】
更に、図５のＶＣＯ特性に示すように、ＰＬＬがロックする周波数範囲は広く、この範囲内で遅延セルの遅延量ｄｔを変更できるので、ディレイライン２の遅延量可変範囲を広帯域とすることができる。
以上説明した実施形態は、遅延セル内の遅延素子をインバータで構成する例を示したが、インバータの代わりにコンパレータを用いる構成でも良い。また、遅延セル内の一方の電流制御用トランジスタ１０５，１０６には一定バイアスを印加し、他方の電流制御用トランジスタ１０７，１０８のみにローパスフィルタ８からの制御電圧Ｖｔを供給するようにしたが、双方の電流制御用トランジスタに制御電圧Ｖｔを供給するようにしてもよい。
【００３１】
【発明の効果】
本発明によれば、高速のクロックを用いることなく所望のパルス波形を得ることが可能となり、特に、ＰＬＬ回路を用いた場合には遅延量を高精度で設定できるようになる。また、ディスク記録装置に適用すれば、メディア種別や回転速度に対応した適切な記録を実現できるようになる。
【図面の簡単な説明】
【図１】本発明によるパルス幅制御回路の実施形態を示すブロック図である。
【図２】遅延回路の他の実施形態を示すブロック図である。
【図３】実施形態における遅延セルの具体構成を示す回路図である。
【図４】実施形態におけるＶＣＯの動作を説明するためのタイミングチャートである。
【図５】実施形態におけるＶＣＯ特性及び遅延特性を示す特性図である。
【図６】図１に示す実施形態の動作を説明するためのタイミングチャートである。
【図７】本発明によるディスク記録制御回路の実施形態を示すブロック図である。
【図８】実施形態におけるテーブルの記憶内容を示す説明図である。
【符号の説明】
１、１０、３０ 遅延回路
２ ディレイライン
３ ＰＬＬ回路
４ ＶＣＯ
５ プログラマブルデバイダ
６ リファレンスデバイダ
７ 位相比較器
８ ローパスフィルタ
１２ ＡＮＤゲート
２０、１１、３１ セレクタ
３２ ＯＲゲート
４０ 遅延セル
５０ ディスク
５１ ＥＦＭエンコーダ
５２ パルス幅制御回路
５４ ディスク記録制御回路
５５ レーザー装置
１０１、１０２ インバータ
１０５、１０６、１０７、１０８ 電流制御用トランジスタ
１１０ 第１制御端子
１１１ 第２制御端子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a pulse width control circuit configured by using a delay circuit in which delay elements are connected in a plurality of stages, and a disk recording control circuit capable of adjusting the recording timing of a recording mark using the pulse width control circuit in a disk recording device About.
[0002]
[Prior art]
Some optical disk devices and magneto-optical disk devices can not only read data but also write data.In such a device, a recording mark corresponding to a data modulation signal is recorded on a disk by a laser device. And writing data to the recording medium.
[0003]
For example, in a CD-R, first, data to be written is modulated into an EFM signal by an EFM encoder, and the EFM signal is sent to a laser device to record a recording mark corresponding to the EFM signal on a disk.
However, since the recording state changes depending on the type of media on which data is recorded and the rotational speed of the disc, it is not possible to record a desired recording mark by simply sending an EFM signal to the laser device. Therefore, attempts have been made to record a desired recording mark by delaying the rising and falling timings of the EFM signal. In order to delay the EFM signal, a plurality of logic circuits such as D flip-flops that operate in synchronization with a clock are generally connected and used.
[0004]
[Problems to be solved by the invention]
The EFM signal is a signal synchronized with a reference signal called an EFM clock, and has a pulse width of 3 to 11 periods of the clock. Therefore, when the delay circuit is configured by the D flip-flop operating in synchronization with the clock as described above, a clock higher than the EFM clock must be used as the clock applied to the D flip-flop. If the resolution of the circuit is 16 steps, a clock 16 times faster than the EFM clock is required.
[0005]
However, this EFM clock is originally a clock with a considerably high frequency, and is “17.28 MHz” at 4 × speed and “34.56 MHz” at 8 × speed. Therefore, the clock applied to the D flip-flop becomes extremely high at "276.48 MHz" at 4 * speed and "552.96 MHz" at 8 * speed. For this reason, it is actually impossible to supply such a high-speed clock, and it is extremely difficult to produce a logic circuit that operates stably in synchronization with such a high-speed clock.
[0006]
Furthermore, since the logic circuit is susceptible to external factors such as power supply fluctuations and temperature changes, it is difficult to control with high accuracy if the pulse width to be controlled is very short.
[0007]
[Means for Solving the Problems]
According to the present invention, first and second delay circuits for connecting a plurality of delay elements to delay an input signal, and selecting one of output signals of each delay element stage for each of the first and second delay circuits. First and second selectors for outputting a delay signal as a delay signal, and first and second logic circuits for performing a logical operation on an input signal and the delay signal for each delay circuit. A pulse width control circuit is characterized in that an output signal is used as an input signal of a second delay circuit, and one of the first and second logic circuits is an AND circuit and the other is an OR circuit.
[0008]
Also, in the present invention, the delay circuit is configured by connecting delay elements in a plurality of stages in a ring shape, and a VCO controlled by a control voltage to which a delay amount of each stage is input, and an output signal of the VCO or its output signal. A phase comparator that receives the frequency-divided signal and the reference signal and compares the phases of the two signals, a low-pass filter that generates the control voltage according to the phase difference detected by the phase comparator, and a delay element of the VCO And a delay line that delays and outputs an input signal and controls the delay amount of each stage by the control voltage.
[0009]
Further, in the present invention, a disk recording control circuit is constituted by the pulse width control circuit, a modulation signal to be recorded is supplied as an input signal, and a select signal corresponding to the type and / or rotation speed of the medium is supplied to the first and the first signals. An output signal that is input to the second selector and is output to a recording device that records a recording mark corresponding to the modulation signal on a disk, so that the recording timing of the recording mark can be adjusted.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a pulse width control circuit according to the present invention. The pulse width control circuit uses two delay circuits 10 and 30 so that the delay amounts of the rise and fall of an input signal can be set independently. I have. Each of the delay circuits 10 and 30 is configured by connecting a plurality of delay elements 40 formed of inverters in series, and selectors 11 and 31 for selecting any one of the output signals of each stage according to select signals SEL1 and SEL2. Are connected to the delay circuits 10 and 30, respectively. Further, an AND gate 12 for inputting the delay signal selected by the selector 11 and the input signal to the delay circuit 10 and an OR gate 32 for inputting the delay signal selected by the selector 31 and the input signal to the delay circuit 30 are provided. The output signal of the AND gate 12 is supplied as an input signal of the delay circuit 30.
[0011]
Here, each of the delay circuits 10 and 30 is configured by connecting the delay elements 40 in 16 stages, and the delay amount dt of one delay element is set to 1/16 of the period T of the reference clock EFMCK. ing.
Therefore, as shown in FIG. 6B, assuming that a 6T EFM signal corresponding to six periods of the EFMCK (FIG. 6A) is input to the delay circuit 10, in the delay circuit 10, each delay element sequentially converts the input EFM signal by T / 16. I will delay it. Then, the selector 11 selects the delay signal EFMD1 (FIG. 6c) of the number of stages specified by SEL1 and outputs the same to the AND gate 12. If the number of stages n specified by SEL1 is “10”, the rising delay amount Tdf is set to Tdf = 10 · T / 16. Since the input signal EFM is applied to the other input terminal of the AND gate 12 as it is, the output signal of the AND gate 12 is as shown in FIG. Signal. In the delay circuit 30, similarly to the delay circuit 10, the output signal of the AND gate 12 is sequentially delayed by T / 16 by each delay element, and the delay signal EFMD2 (FIG. 6e) of the number n of stages designated by SEL2 is selected by the selector 31. And is output to the OR gate 32. If the number n of stages specified by SEL2 is “8”, the falling delay amount Tdb is set to Tdb = 8 · T / 16. In the OR gate 32, the logical sum of the output signal of the AND gate and the delay signal EFMD2 is obtained, and as shown in FIG. 6f, the output WDAT has a rising edge Tdf (10) when compared with the input EFM signal. .T / 16), the fall is delayed by Tdb (8.T / 16), and a signal having a pulse width reduced by 2T / 16 is output.
[0012]
As described above, the rising and falling delay amounts Tdf and Tdb can be independently set by the select signals SEL1 and SEL2. It is to be noted that an EFM signal is input to the delay circuit 30, an output of the OR gate 32 is input to the delay circuit 10, and an output of the AND gate 12 is used as a final output signal WDAT. be able to. Further, a comparator may be used instead of the inverter as the delay element 40.
[0013]
Next, an example in which the pulse width control circuit described above is applied to a disk recording control circuit for a CD-R will be described with reference to FIG.
FIG. 7 is a block diagram showing the configuration of the entire disc recording apparatus for CD-R. Data to be written to the disc 50 is first modulated into an EFM signal by an EFM encoder 51, and the pulse width control circuit shown in FIG. 52 together with EFMCK. The disk recording control circuit 54 is composed of the pulse width control circuit 52 and the register 53. An output signal of the pulse width control circuit 52 is supplied to a laser device 55 such as a laser pickup, and a recording mark corresponding to the EFM signal is recorded on the disk. Is done. Further, information indicating the type of media and the rotation speed of the disk to be used is input to the microcomputer 56 that controls the entire disk recording device, and a table 57 connected to the microcomputer 56 stores the media as shown in FIG. A rise delay amount Tdf and a fall delay amount Tdb are stored in advance corresponding to the type and the rotation speed, respectively. It should be noted that the stored delay amount is stored as a numerical value indicating how many times the unit delay amount T / 16 is, and thus the numerical values themselves are SEL1 and SEL2.
[0014]
When the media type and the rotation speed are designated, the microcomputer reads the corresponding rising and falling delay amounts from the table, and sets these values in the register 53. Then, the numerical values set in the register 53 are input to the pulse width control circuit 52 as SEL1 and SEL2. The pulse width control circuit 52 delays the rising of the input EFM signal by the delay amount specified by SEL1, delays the falling by the delay amount specified by SEL2, and sends the signal to the laser device 55 as described above. I do. Therefore, in the laser device 55, the recording timing of the EFM signal is adjusted according to the type and rotation speed of the medium, and an appropriate recording mark is recorded.
[0015]
By the way, in the delay elements 40 constituting the delay circuits 10 and 30 shown in FIG. 1, since the characteristics of the transistors constituting the delay elements are not uniform due to manufacturing variations, the delay amount varies. Therefore, when it is desired to set the delay amount with high accuracy, the delay circuit 1 shown in FIG.
The delay circuit 1 shown in FIG. 2 includes a delay line 2 for delaying an input signal, and a PLL circuit 3 for controlling a delay amount of the delay line 2. The PLL circuit 3 includes a VCO 4 whose output signal frequency changes according to an input control voltage Vt, a programmable divider 5 that divides the output signal of the VCO 4 by 1 / N, and an input reference signal RFCK that divides the input signal by 1 / M. A reference divider 6 that circulates, a phase comparator 7 that compares the phases of the output signals of the two dividers 5 and 6, and a low-pass filter 8 that supplies a control voltage Vt corresponding to the phase difference detected by the phase comparator 7 to the VCO 3. , And both dividers 5 and 6 are dividers whose division ratios can be changed. The output stage of the phase comparator 7 is provided with a charge pump.
[0016]
As shown in FIG. 2, the VCO 4 in the PLL circuit 3 has a ring-shaped configuration in which a plurality of delay cells 40 are connected in series, and the output of the last-stage delay cell 41 is negatively fed back to the first stage. The output of the last stage is sent to the programmable divider 5 via the buffer 45. Each of the delay cells has first and second control terminals. The first control terminal is supplied with a constant bias Vb from the bias circuit 46, and the second control terminal is supplied with the control voltage Vt from the low-pass filter 8. Is supplied.
[0017]
On the other hand, the delay line 2 is configured by connecting a plurality of delay cells 40 having the same configuration as the delay cells forming the VCO 4 in series, and unlike the VCO 4, the input signal SIN is applied from the outside to the first delay cell. ing. Then, one of the outputs from the delay cells in each stage is selected by the selector 20, and is taken out as the delay signal SOUT. The selector 20 is a selector corresponding to the selectors 11 and 31 in FIG. The circuit shown in FIG. 2 is configured in the vicinity of the same chip, so that the delay characteristics of the delay cell are almost the same between the VCO 4 and the delay line.
[0018]
Here, a specific configuration of the delay cell 40 will be described with reference to FIG.
The delay cell 40 is basically configured by connecting two stages of inverters 101 and 102 in which a P-channel MOS transistor and an N-channel MOS transistor are cascade-connected. Buffers 103 and 104 are connected. Current control P-channel MOS transistors 105 and 106 are connected between the power supply potentials of inverters 101 and 102, and current control N-channel MOS transistor 107 is connected between the power supply potentials of inverters 101 and 102. , 108 are connected. The gate of the current control P-channel MOS transistor 105 is connected to the first control terminal 110, and the gate of the current control N-channel MOS transistor 107 is connected to the second control terminal 111. Incidentally, reference numeral 109 denotes a parasitic capacitance.
[0019]
In the present embodiment, the constant bias Vb from the bias circuit 46 is supplied to the first control terminal 110, and the control voltage Vt from the low-pass filter 8 is supplied to the second control terminal 111. Therefore, when the control voltage Vt increases, the current flowing through the inverters 101 and 102 increases and the delay amount dt of the input signal IN decreases. When the control voltage Vt decreases, the current flowing through the inverters 101 and 102 decreases and the input signal IN increases. Dt increases. Thus, the delay amount dt of the delay cell 40 changes according to the magnitude of the control voltage Vt.
[0020]
By the way, the last stage of the VCO 4 includes only the first half of the delay cell 40, that is, the inverter 101, the buffer 103, and the control transistors 105 and 107 in order to apply negative feedback. The output of the inverter 101 is the first stage of the VCO 4 It is input to the delay cell 40.
Hereinafter, the operation of the embodiment shown in FIG. 2 will be described.
[0021]
First, the output signal frequency f1 of the VCO 4 is divided by the programmable divider 5 into 1 / N to become f1 / N, and the reference signal frequency f0 is divided by the reference divider 6 to become f0 / M. The phase of these frequency-divided signals is compared by a phase comparator 7, and a control voltage Vt corresponding to the phase difference is supplied from the low-pass filter 8 to the VCO 4. As a result, the PLL circuit 3 operates so as to eliminate the phase difference between the output signals of the two dividers, and when the PLL is locked, the equation (1) holds.
[0022]
(Equation 1)

[0023]
On the other hand, in the VCO 4, the delay amount dt of each delay cell is determined by the control voltage Vt from the low-pass filter 8 as described above, and the signal dt0 input to the first-stage delay cell 40 becomes the delay dt as shown in FIG. The cells 40 are sequentially delayed by dt. Then, the signal is inverted in the delay cell 41 at the last stage, and the inverted signal is fed back to the first stage after the return delay dα. That is, assuming that the return delay dα is sufficiently smaller than dt, the half cycle T / 2 of the cycle T of the VCO 4 is a length obtained by adding the delay amount dt by the number D of stages of the delay cell 40. Therefore, the delay amount dt is represented by the equation (2).
[0024]
(Equation 2)

[0025]
Here, the period T is 1 / f1, and when the PLL circuit 3 locks as described above, the equation (1) is established. Therefore, in the locked state, the delay amount dt is expressed by the equation (3).
[0026]
[Equation 3]

[0027]
That is, if the number of delay cell stages D of the VCO and the division ratios M and N are determined, the delay amount dt of the delay cell 40 becomes a constant value that depends only on the frequency f0 of the reference signal RFCK.
By the way, in the circuit shown in FIG. 2, as described above, the delay cells constituting the delay line 2 have exactly the same configuration as the delay cells of the VCO 4, and the control voltage supplied to the delay cells in the delay line 2 is also VCO 4 Is exactly the same as the control voltage Vt supplied to the delay cell 40 of FIG. For this reason, the delay amount of the delay cell in the delay line 2 becomes exactly the same as the delay amount dt of the delay cell 40 of the VCO 4, and becomes a constant value depending on the reference signal frequency f0 when the PLL is locked.
[0028]
The delay line 2 has a configuration in which the input signal SIN is sequentially delayed by the delay cell 40, a delay output of a desired stage is selected by the selector 20, and the delay output is output as the delay signal SOUT. Since dt has a constant value when the PLL is locked, the delay amount of the delay signal output from the selector 20 in the delay line 2 also has a desired constant value. In other words, the delay line 2 does not require adjustment at the time of manufacturing, and can set the delay amount with the accuracy guaranteed by the PLL circuit 3, so that it is possible to set a high accuracy in the order of psec. Moreover, since the PLL is guaranteed against power supply fluctuations and temperature fluctuations, the delay amount of the delay line 2 is not affected by these fluctuations.
[0029]
Further, since the delay amount dt can be easily changed only by changing the frequency f0 of the reference signal RFCK and the frequency division ratios M and N, the resolution of the delay line 2 can be easily set.
For example, when the number of stages D of the VCO 4 is “16”, if the frequency division ratios M and N are each “2” and f0 is “17.28 MHz”, the delay amount dt is “1” from Expression (3). .81 nsec. " Then, if the frequency division ratios M and N are changed to “4” and f0 is changed to “34.56 MHz”, the delay amount dt becomes “0.90 nsec” and the resolution in the order of psec from the equation (3). .
[0030]
Further, as shown in the VCO characteristic of FIG. 5, the frequency range in which the PLL locks is wide, and the delay amount dt of the delay cell can be changed within this range. it can.
In the embodiment described above, an example is shown in which the delay element in the delay cell is configured by an inverter, but a configuration using a comparator instead of the inverter may be used. Further, a constant bias is applied to one of the current control transistors 105 and 106 in the delay cell, and the control voltage Vt from the low-pass filter 8 is supplied only to the other current control transistors 107 and 108. The control voltage Vt may be supplied to both current control transistors.
[0031]
【The invention's effect】
According to the present invention, a desired pulse waveform can be obtained without using a high-speed clock. In particular, when a PLL circuit is used, a delay amount can be set with high accuracy. Further, if the present invention is applied to a disk recording device, it becomes possible to realize appropriate recording corresponding to the type of media and the rotation speed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a pulse width control circuit according to the present invention.
FIG. 2 is a block diagram showing another embodiment of the delay circuit.
FIG. 3 is a circuit diagram showing a specific configuration of a delay cell in the embodiment.
FIG. 4 is a timing chart for explaining the operation of the VCO in the embodiment.
FIG. 5 is a characteristic diagram showing a VCO characteristic and a delay characteristic in the embodiment.
FIG. 6 is a timing chart for explaining the operation of the embodiment shown in FIG. 1;
FIG. 7 is a block diagram showing an embodiment of a disk recording control circuit according to the present invention.
FIG. 8 is an explanatory diagram showing storage contents of a table in the embodiment.
[Explanation of symbols]
1, 10, 30 delay circuit 2 delay line 3 PLL circuit 4 VCO
Reference Signs List 5 Programmable divider 6 Reference divider 7 Phase comparator 8 Low-pass filter 12 AND gate 20, 11, 31 Selector 32 OR gate 40 Delay cell 50 Disk 51 EFM encoder 52 Pulse width control circuit 54 Disk recording control circuit 55 Laser devices 101, 102 Inverter 105, 106, 107, 108 Current control transistor 110 First control terminal 111 Second control terminal

Claims (5)

First and second delay circuits for connecting a plurality of delay elements to delay an input signal, and selecting one of the output signals of each delay element stage for each of the first and second delay circuits as a delay signal There are first and second selectors for outputting, and first and second logic circuits for performing a logical operation on an input signal and the delay signal for each delay circuit, and outputs an output signal of the first logic circuit to a first 2. A pulse width control circuit comprising: an input signal to a second delay circuit; one of the first and second logic circuits being an AND circuit; and the other being an OR circuit. 2. The pulse width control circuit according to claim 1, wherein said delay element comprises an inverter or a comparator. The delay circuit is configured by connecting a plurality of delay elements in a ring shape in a plurality of stages, a VCO controlled by a control voltage to which a delay amount of each stage is input, an output signal of the VCO or a divided signal thereof and a reference signal. , A phase comparator for comparing the phases of both signals, a low-pass filter for generating the control voltage according to the phase difference detected by the phase comparator, and a delay element having the same configuration as the delay element of the VCO 2. The pulse width control according to claim 1, further comprising: a delay line for delaying and outputting an input signal and controlling the delay amount of each stage by the control voltage. circuit. 4. A pulse width control circuit according to claim 1, wherein a modulation signal to be recorded is supplied as an input signal, and a select signal according to a type and / or rotation speed of a medium is supplied to the first and second pulses. 2. A disk recording control circuit, wherein an output signal is sent to a recording device that inputs a recording mark corresponding to the modulation signal to a disk and is input to the selector of (2), thereby enabling the recording timing of the recording mark to be adjusted. A delay line whose delay amount is controlled by a control voltage is connected in a plurality of stages, and a delay line for inputting and delaying a modulation signal to be recorded and a delay line having the same configuration as the delay device are connected in a plurality of stages. A VCO whose delay amount is controlled by the control voltage, a PLL circuit having a loop filter for generating the control voltage, and an output signal of each delay element stage of the delay line. And a logic circuit that performs a logical operation on the delay signal from the selector and the input modulation signal, and outputs an output signal based on the operation result of the logic circuit to a recording mark corresponding to the modulation signal. A disc recording control circuit for sending a recording mark to a recording device for recording on a disk so that the recording timing of a recording mark can be adjusted.

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