JP2001255515A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower manufacturing cost by reducing the number of components and simplifying a structure in a liquid crystal display device. SOLUTION: The liquid crystal display device has a liquid crystal display panel PNL, an intermediate frame MFR, on the upper side of which the liquid crystal display panel PNL is mounted and on the lower side of which a backlight part BL is mounted and a drive circuit substrate electrically connected with the liquid crystal display panel PNL through a flat cable FC and engaged with the intermediate frame MFR, so as to be overlapped by the end part of the liquid crystal display panel PNL along two sides adjacent to each other of the liquid crystal display panel PNL. A connector connected with an external device and a power source circuit are mounted on the drive circuit substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, the present invention relates to an active matrix type liquid crystal display device using a thin film transistor or the like.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active method has better contrast than the so-called simple matrix method that employs the time-division driving method. Then it is becoming an indispensable technology. A typical switching element is a thin film transistor (TFT).

In a liquid crystal display (liquid crystal display panel), a thin film transistor, a transparent pixel electrode, a protective film for the thin film transistor, and a lower alignment film for setting the direction of liquid crystal molecules are sequentially provided on a lower transparent glass substrate based on the liquid crystal layer. And the upper substrate, on which a black matrix, a color filter, a protective film for a color filter, a common transparent pixel electrode, and an upper alignment film are sequentially provided on an upper transparent glass substrate, so that the alignment films face each other. At the same time, the two substrates are adhered to each other with a sealant arranged around the edge of the substrate, and the liquid crystal is sealed between the two substrates. A backlight is provided on the lower substrate side.

Incidentally, an active matrix type liquid crystal display device using thin film transistors is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-309921 or "1.
2.5-inch active matrix color liquid crystal display, "Nikkei Electronics, pp. 193-110, December 1986
March 15, published by Nikkei McGraw-Hill, Inc.

[0005]

In a conventional liquid crystal display device, a storage case for a backlight and a reflector made of a metal plate such as aluminum for reflecting light of the backlight toward the liquid crystal display section are separately provided. And the number of parts is large, the structure is complicated, and the manufacturing cost is high.

One object of the present invention is to provide a liquid crystal display device which can reduce the number of parts, another object is to simplify the structure, and another object is to reduce the manufacturing cost.

[0007]

In order to solve the above problems, the present invention provides a liquid crystal display panel and a frame member on which the liquid crystal display panel is mounted above and a backlight portion is mounted below the liquid crystal display panel. And a circuit board electrically connected to the liquid crystal display panel through a flat cable and fitted to the frame member along two adjacent sides of the liquid crystal display panel so as to overlap an end of the liquid crystal display panel. A liquid crystal display device having a circuit board and a connector connected to an external device and a power supply circuit mounted on the circuit board.

[0008]

According to the liquid crystal display device of the present invention, the number of parts can be reduced, the structure can be simplified, and the manufacturing cost can be reduced by the above configuration.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS The invention, further objects of the invention and further features of the invention will become apparent from the following description with reference to the drawings, in which: FIG. << Active Matrix Liquid Crystal Display >> An embodiment in which the present invention is applied to an active matrix type color liquid crystal display will be described below. In the drawings described below, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted. << Outline of Matrix Unit >> FIG. 1 is a plan view showing one pixel of an active matrix type color liquid crystal display device to which the present invention is applied and the periphery thereof, and FIG. FIG. 3 is a sectional view taken along line 3-3 in FIG. FIG. 4 is a plan view when a plurality of pixels shown in FIG. 1 are arranged.

As shown in FIG. 1, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL.
And two adjacent video signal lines (drain signal lines or vertical signal lines) DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1, and a storage capacitor Cadd. The scanning signal lines GL extend in the column direction, and a plurality of the scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction.

As shown in FIG. 2, a thin film transistor TFT is provided on the lower transparent glass substrate SUB1 side with respect to the liquid crystal LC.
Further, a transparent pixel electrode ITO1 is formed, and a color filter FIL and a light-shielding black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 mm. In addition, the transparent glass substrates SUB1, S
A silicon oxide film SIO formed by dipping or the like is provided on both surfaces of UB2. For this reason, even if there are sharp scratches on the surfaces of the transparent glass substrates SUB1 and SUB2, the sharp scratches can be covered with the silicon oxide film SIO.
L, the film quality of the light shielding film BM and the like can be kept uniform.

A light shielding film BM and a color filter FI are provided on the inner surface (the liquid crystal LC side) of the upper transparent glass substrate SUB2.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and an upper alignment film ORI2 are sequentially laminated. << Outline of matrix periphery >> FIG. 16 shows upper and lower glass substrates S
FIG. 17 is a plan view of the periphery of the matrix (AR) of the display panel PNL including UB1 and SUB2, FIG. 17 is a plan view further exaggerating the periphery, and FIG. 18 is a seal corresponding to the upper left corner of the panel in FIGS. It is a figure showing the enlarged plane near part SL. 19 is a cross section taken along the line 19a-19a in FIG. 18 with the cross section of FIG. 2 at the center, and an external connection terminal DT to which the video signal drive circuit is to be connected is shown on the right.
It is a figure showing a section near M. Similarly, FIG. 20 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

[0013] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared A glass substrate of a standardized size is processed even in a variety, and the size is reduced to a size suitable for each type. In each case, the glass is cut after passing through one process. FIGS. 16 to 18 show examples of the latter, and FIGS. 16 and 17 both show the upper and lower substrates SUB.
FIG. 18 shows a state before cutting the substrates SUB1 and SUB2, and FIG. 18 shows a state before cutting the substrates. LN indicates an edge of both substrates before cutting, and CT1 and CT2 indicate positions where the substrates SUB1 and SUB2 are to be cut, respectively. In any case, in the completed state, the external connection terminal group T
g, Td (subscripts omitted) (upper and lower sides and left side in the figure)
In the portions, the size of the upper substrate SUB2 is limited to the inside of the lower substrate SUB1 so as to expose them. The terminal groups Tg and Td are respectively provided with a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, which are described later, and their leading wiring portions of a tape carrier package TCP (FIGS. 20 and 21) on which an integrated circuit chip CHI is mounted. The unit is named plurally. The lead wiring from the matrix section of each group to the external connection terminal section is inclined as approaching both ends. This is because the terminals DTM and GTM of the display panel PNL are matched with the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP.

Between the transparent glass substrates SUB1 and SUB2, along the edge thereof, except for the liquid crystal filling opening INJ, the liquid crystal LC
Is formed to seal the sealing pattern SL. The sealing material is made of, for example, an epoxy resin. At least one common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to the lead-out wiring INT formed on the lower transparent glass substrate SUB1 side by a silver paste material AGP at four corners of the panel in this embodiment. ing. The lead wiring INT is formed in the same manufacturing process as the later-described gate terminal GTM and drain terminal DTM.

The alignment films ORI1, ORI2, the transparent pixel electrode ITO1, and the common transparent pixel electrode ITO2 are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are each a lower transparent glass substrate SUB
1. Formed on the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is sealed in a region partitioned by the seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 for setting the direction of the liquid crystal molecules. The lower alignment film ORI1 is a protective film P on the lower transparent glass substrate SUB1 side.
It is formed above the SV1.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2.
Side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are sealed. Assembled by cutting. << Thin film transistor TFT >> Thin film transistor TFT
Operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases.

The thin film transistor TFT of each pixel is divided into two (a plurality) in the pixel, and is constituted by thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same). Each of the divided thin film transistors TFT1 and TFT2 is a gate electrode GT, a gate insulating film GI, and an i-type semiconductor made of i-type (intrinsic, intrinsic, not doped with a conductivity type determining impurity) amorphous silicon (Si). It has a layer AS, a pair of source electrodes SD1, and a drain electrode SD2. It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are interchanged during the operation. However, in the following description, one is fixed and the other is fixed as a drain for convenience. << Gate electrode GT >> The gate electrode GT is shown in FIG.
As shown in a plan view depicting only the conductive film g2 and the i-type semiconductor layer AS, a vertical direction (FIG.
5 (upward in FIG. 5) (branched into a T-shape). Gate electrode GT
Protrudes beyond the respective active areas of the thin film transistors TFT1 and TFT2. Thin film transistor T
The respective gate electrodes GT of the FT1 and the TFT2 are integrally formed (as a common gate electrode) and formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of a single-layer second conductive film g2. The second conductive film g2 is formed, for example, using an aluminum (Al) film formed by sputtering and having a thickness of about 1000 to 5500 °. An anodic oxide film AOF of Al is provided on the gate electrode GT.

As shown in FIGS. 1, 2 and 5, the gate electrode GT is formed larger than the gate electrode GT so as to completely cover the i-type semiconductor layer AS (as viewed from below).
Therefore, when a backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of opaque Al becomes a shadow, and the i-type semiconductor layer AS is not irradiated with the backlight. In addition, the conductive phenomenon due to light irradiation, that is, the deterioration of the off characteristic of the thin film transistor TFT is less likely to occur. Note that the original size of the gate electrode GT is the minimum necessary to extend between the source electrode SD1 and the drain electrode SD2 (including the margin for positioning between the gate electrode GT, the source electrode SD1, and the drain electrode SD2). ) Has a width and the depth length that determines the channel width W is determined by the ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, the factor W / L that determines the transconductance gm. It depends on what you do. The gate electrode G in this liquid crystal display device
The size of T is, of course, made larger than the original size described above. << Scanning Signal Line GL >> The scanning signal line GL is formed of the second conductive film g2. The second conductive film g2 of the scanning signal line GL
Are formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and are integrally formed. An anodic oxide film AOF of Al is also provided on the scanning signal line GL. << Insulating film GI >> The insulating film GI is a thin film transistor TFT
1. Used as a gate insulating film of each TFT2. The insulating film GI includes the gate electrode GT and the scanning signal line GL.
Is formed in the upper layer. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is used.
Film thickness of ２2700 ° (in this liquid crystal display device, 2000
(膜厚 film thickness). FIG. 18 shows the gate insulating film GI.
As shown in FIG. 7, the matrix portion AR is formed so as to surround the entirety, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM. << i-type semiconductor layer AS >> As shown in FIG. 5, the i-type semiconductor layer AS has a plurality of divided thin film transistors TFT1,
Each of the TFTs 2 is used as a channel forming region. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of 200 to 2200 （(about 2,000 で は in this liquid crystal display device).

The i-type semiconductor layer AS is formed by the same plasma CVD method by changing the composition of the supply gas and forming an insulating film GI used as a gate insulating film made of Si ₃ N _4.
The device is formed without being exposed to the outside from the plasma CVD device. An N ⁺ type semiconductor layer d doped with 2.5% of phosphorus (P) for ohmic contact
0 (FIG. 2) is similarly formed continuously with a film thickness of 200 to 500 ° (about 300 ° in this liquid crystal display device). Then, the lower transparent glass substrate SUB1 is CV
The N ⁺ -type semiconductor layer d0 and the i-type semiconductor layer AS are taken out of the device D and are patterned into independent islands by a photographic processing technique as shown in FIGS. 1, 2 and 5.

As shown in FIGS. 1 and 5, the i-type semiconductor layer AS is also provided between both intersections (crossover portions) between the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the video signal line DL at the intersection. << Transparent Pixel Electrode ITO1 >> The transparent pixel electrode ITO1 forms one of the pixel electrodes of the liquid crystal display unit.

The transparent pixel electrode ITO1 is connected to the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T1.
It is connected to both source electrodes SD1 of FT2. Therefore, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut off by a laser beam or the like, and if not, the other thin film transistor operates normally. You can leave it. It is rare that defects occur simultaneously in the two thin film transistors TFT1 and TFT2, and the probability of a point defect or a line defect can be extremely reduced by such a redundant system. Transparent pixel electrode ITO
Reference numeral 1 denotes a first conductive film d1.
The conductive film d1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering.
A film thickness of 100 to 2000 ° (14 in this liquid crystal display device).
(Thickness of about 00 °). << Source electrode SD1, Drain electrode SD2 >> The source electrode SD1 and the drain electrode SD2 of each of the thin-film transistors TFT1 and TFT2 divided into a plurality are shown in FIG.
As shown in FIG. 2 and FIG. 6 (a plan view depicting only the first to third conductive films d1 to d3 in FIG. 1), they are separately provided on the i-type semiconductor layer AS.

Each of the source electrode SD1 and the drain electrode SD2 is formed by sequentially stacking a second conductive film d2 and a third conductive film d3 from the lower side in contact with the N ⁺ type semiconductor layer d0. Second conductive film d2 of source electrode SD1
The third conductive film d3 is formed in the same manufacturing process as the second conductive film d2 and the third conductive film d3 of the drain electrode SD2.

The second conductive film d2 is formed using a chromium (Cr) film formed by sputtering and having a thickness of 500 to 1000 Å (about 600 膜厚 in this liquid crystal display device).
Since the stress increases when the Cr film is formed to have a large thickness, the Cr film is formed in a range not exceeding about 2000 °.
The Cr film has good contact with the N ⁺ type semiconductor layer d0. C
The r film forms a so-called barrier layer that prevents Al of a third conductive film d3 described later from diffusing into the N ⁺ type semiconductor layer d0. As the second conductive film d2, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used in addition to the Cr film.

The third conductive film d3 has a thickness of 3000 to 5000 ° by sputtering of Al (in this liquid crystal display device,
(A film thickness of about 4000 °). The Al film has a smaller stress than the Cr film and can be formed with a large thickness, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. As the third conductive film d3, an Al film containing silicon or copper (Cu) as an additive may be used in addition to the pure Al film.

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, using the same mask or using the second conductive film d2 and the third conductive film d3 as a mask, an N ⁺ type semiconductor layer is formed. d0 is removed. That is, i
In the N ⁺ type semiconductor layer d0 remaining on the type semiconductor layer AS, portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, since the N ⁺ type semiconductor layer d0 is etched so as to remove the entire thickness thereof,
The surface of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

The source electrode SD1 is a transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 has an i-type semiconductor layer AS step (the thickness of the second conductive film g2, the thickness of the anodic oxide film AOF, the thickness of the i-type semiconductor layer AS, and the N ⁺ type semiconductor layer d.
(A step corresponding to a film thickness obtained by adding a film thickness of 0). Specifically, the source electrode SD1 is formed of a second conductive film d2 formed along a step of the i-type semiconductor layer AS.
And a third conductive film d formed on the second conductive film d2.
3 is comprised. Since the third conductive film d3 of the source electrode SD1 cannot form a thick Cr film of the second conductive film d2 due to an increase in stress and cannot cross the step shape of the i-type semiconductor layer AS, the third conductive film d3 crosses over the i-type semiconductor layer AS. Is configured for. That is, the step coverage is improved by forming the third conductive film d3 to be thick. Since the third conductive film d3 can be formed to be thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL). << Protective Film PSV1 >> A protective film PSV1 is provided on the thin film transistor TFT and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of about 1 μm.

As shown in FIG. 18, the protective film PSV1 is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM.
Further, the common electrode COM of the upper substrate SUB2 is connected to the lower substrate SU.
The portion connected to the external connection terminal connection lead-out line INT of B1 with the silver paste AGP is also removed. Protective film PSV
Regarding the thickness relationship between 1 and the gate insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner in the transconductance gm of the transistor. Therefore, as shown in FIG. 18, the protection film PSV1 having a high protection effect is formed larger than the gate insulating film GI so as to protect the peripheral portion as much as possible. << Light-Shielding Film BM >> On the upper transparent glass substrate SUB2 side, external light (light from above in FIG. 2) is not incident on the i-type semiconductor layer AS used as a channel formation region.
A light-shielding film BM is provided, and the light-shielding film BM has a pattern as shown by hatching in FIG. Note that FIG.
FIG. 3 is a plan view illustrating only a first conductive film d1, a color filter FIL, and a light shielding film BM made of an ITO film in FIG. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property. In this liquid crystal display device, the chromium film is formed to a thickness of about 1300 ° by sputtering.

Therefore, the thin film transistors TFT1, TF
The i-type semiconductor layer AS of T2 is sandwiched between the upper and lower light shielding films BM and the large gate electrode GT,
That portion is not exposed to external natural light or backlight light. The light-shielding film BM is formed around the pixel as shown by the hatched portion in FIG. 7, that is, the light-shielding film BM is formed in a lattice shape (black matrix), and an effective display area of one pixel is partitioned by the lattice. . Therefore, the outline of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light-shielding film BM has two functions of light-shielding for the i-type semiconductor layer AS and black matrix.

Also, a portion (lower right portion in FIG. 1) of the transparent pixel electrode ITO1 facing the edge portion on the root side in the rubbing direction.
Is shielded from light by the light-shielding film BM, so that even if a domain is generated in the above-mentioned portion, the domain is not visible, so that the display characteristics do not deteriorate.

The backlight can be attached to the upper transparent glass substrate SUB2, and the lower transparent glass substrate SUB1 can be used as the observation side (exposed side).

The light-shielding film BM is also formed in a peripheral portion in a frame-shaped pattern as shown in FIG. 17, and the pattern is formed continuously with the pattern of the matrix portion shown in FIG. Have been. The light-shielding film BM in the peripheral portion is extended outside the seal portion SL as shown in FIG. 17 to FIG. 20 to prevent leakage light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion. . On the other hand, this light-shielding film BM is about 0.3 to 1..
The substrate SUB2 is formed so as to be kept inside by about 0 mm so as to avoid the cutting region of the substrate SUB2. << Color Filter FIL >> The color filter FIL is formed by coloring a dye on a dye base made of a resin material such as an acrylic resin. The color filters FIL are formed in stripes at positions facing the pixels (FIG. 8), and are dyed separately (FIG. 8 depicts only the first conductive film d1, the light shielding film BM, and the color filters FIL in FIG. 4). Each of the B, R, and G color filters FIL is cross-hatched at 45 ° and 135 °, respectively.) The color filter FIL is formed to be large so as to cover the entirety of the transparent pixel electrode ITO1 as shown in FIGS. 7 and 9, and the light-shielding film BM is formed so that the transparent pixel electrode I1 overlaps the edge portion of the color filter FIL and the transparent pixel electrode ITO1.
It is formed inside the periphery of TO1.

The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process. << Protective film PSV2 >> The protective film PSV2 is a color filter F
This is provided in order to prevent a dye obtained by dyeing the IL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin. << Common transparent pixel electrode ITO2 >> Common transparent pixel electrode ITO
Reference numeral 2 denotes a transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is determined by the pixel electrode ITO1 and the common transparent pixel electrode IT1.
It changes in response to a potential difference (electric field) with O2. The common transparent pixel electrode ITO2 is configured to apply a common voltage Vcom. In this embodiment, the common voltage Vcom is set to an intermediate potential between the low-level drive voltage Vdmin and the high-level drive voltage Vdmax applied to the video signal line DL. If it is desired to reduce the power supply voltage by about half, an AC voltage may be applied. The common transparent pixel electrode ITO2
Please refer to FIG. 17 and FIG. 18 for the planar shape of. << Gate Terminal >> FIG. 9 shows the scanning signal lines G of the display matrix.
It is a figure which shows the connection structure from L to the external connection terminal GTM, (A) is a plane and (B) has shown the cross section in the BB cutting line of (A). This figure corresponds to the vicinity of the lower part of FIG. 18, and the diagonal wiring portion is represented by a straight line for convenience.

AO is a mask pattern for photo processing, in other words, a photoresist pattern of selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but its locus remains because the oxide film AOF is selectively formed on the gate wiring GL as shown in the sectional view. In the plan view, the left side is a region which is covered with the resist and is not anodized, and the right side is a region which is exposed from the resist and is anodized with reference to the boundary line AO of the photoresist. Anodized A
L layer g2 conductive portion of the lower formed its oxide the Al ₂ O ₃ film AOF on the surface volume decreases. Of course, anodic oxidation is performed by setting an appropriate time, voltage and the like so that the conductive portion remains. The mask pattern AO does not intersect the scanning line GL with a single straight line, but intersects by bending in a crank shape.

In the figure, the AL layer g2 is hatched for easy understanding, but the region not anodized is patterned in a comb shape. This is because, when the width of the Al layer is large, whiskers are generated on the surface. Therefore, the width of each one is narrowed, and a plurality of these are bundled in parallel to prevent the generation of whiskers and disconnect the wires. The aim is to minimize the probability and conductivity sacrifice. Therefore, in this example, the portion corresponding to the root of the comb is also shifted along the mask AO.

The gate terminal GTM has a Cr layer g1 which has good adhesion to the silicon oxide SIO layer and has higher contact resistance than Al or the like.
Further, the transparent conductive layer d1 has the same level (same layer, simultaneous formation) as the pixel electrode ITO1 and protects the surface thereof.
Note that the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof are formed in such regions that the conductive layers g2 and g1 are not etched together due to a pinhole or the like when the conductive layers d3 and d2 are etched. It remains as a result of being covered with photoresist. In addition, the ITO layer d1 extending rightward beyond the gate insulating film GI is a more complete countermeasure.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line, the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located at the left end is formed.
Are exposed from them so that they can make electrical contact with external circuits. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, such a pair is arranged in a plural number up and down as shown in FIG.
(FIGS. 17 and 18), and the left end of the gate terminal is
In the manufacturing process, the wiring is extended beyond the cutting area CT1 of the substrate and short-circuited by the wiring SHg. In the manufacturing process, such a short-circuit line SHg is supplied with power during anodization and the alignment film OR.
It is useful for preventing electrostatic breakdown at the time of rubbing of I1. << Drain Terminal DTM >> FIG. 10 is a diagram showing a connection from the video signal line DL to its external connection terminal DTM.
(A) shows the plane, and (B) shows a cross section taken along the line BB of (A). 18 corresponds to the vicinity of the upper right of FIG. 18, and the direction of the drawing is changed for convenience, but the right end corresponds to the upper end (or lower end) of the substrate SUB1.

TSTd is an inspection terminal to which an external circuit is not connected, but is wider than a wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal D
The TM is also wider than the wiring part so that it can be connected to an external circuit. A plurality of test terminals TSTd and external connection drain terminals DTM are alternately arranged in a staggered manner in the vertical direction, and the test terminals TSTd are terminated without reaching the end of the substrate SUB1 as shown in FIG.
Constitutes a terminal group Td (subscript omitted) as shown in FIG. 18 and is further extended beyond the cutting line CT1 of the substrate SUB1.
During the manufacturing process, all of them are short-circuited to each other by the wiring SHd to prevent electrostatic breakdown. A drain connection terminal is connected to the opposite side of the matrix of the video signal line DL where the inspection terminal TSTd exists, and the drain connection terminal DTM is conversely connected.
An inspection terminal is connected to the opposite side of the matrix of the video signal line DL in which is present.

The drain connection terminal DTM is made of the Cr layer g1 and the ITO layer d1 for the same reason as the gate terminal GTM described above.
And the portion where the gate insulating film GI is removed is connected to the video signal line DL. The semiconductor layer AS formed on the edge of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. On the terminal DTM, the protection film PSV1 is removed as well as the connection for connection with an external circuit. AO is the anodic oxidation mask described above, and the boundary line is formed so as to largely surround the entire matrix. In the figure, the left side from the boundary line is covered with the mask. This pattern is not directly relevant since it does not exist.

The lead-out wiring from the matrix portion to the drain terminal portion DTM is as shown in FIG.
The structure is such that the layers d2 and d3 of the same level as the video signal line DL are partially stacked on the seal pattern SL just above the layers d1 and g1 of the same level as the drain terminal portion DTM. Is minimized, and the Al layer d3 that is easily touched is protected as much as possible by the protective film PSV1 and the seal pattern SL. << Structure of Storage Capacitor Cadd >> Transparent Pixel Electrode ITO1
Are formed so as to overlap an adjacent scanning signal line GL at an end opposite to the end connected to the thin film transistor TFT. As is clear from FIGS. 1 and 3, this superposition is performed by connecting the transparent pixel electrode ITO1 to one electrode P.
L2, and a storage capacitance element (capacitance element) Cadd using the adjacent scanning signal line GL as the other electrode PL1.
The dielectric film of the storage capacitor Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As is apparent from FIG. 5, the storage capacitance element Cadd is formed in a portion of the scanning signal line GL where the width of the second conductive film g2 is increased. Note that the portion of the second conductive film g2 that intersects with the video signal line DL is made thin in order to reduce the probability of a short circuit with the video signal line DL.

Even if the transparent pixel electrode ITO1 breaks at the step of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive film d2 are formed so as to extend over the step.
The defect is compensated for by the island region constituted by the conductive film d3. << Equivalent Circuit of Entire Display Device >> FIG. 11 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. Although the figure is a circuit diagram, it is drawn corresponding to an actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.

In the figure, X indicates a video signal line DL, and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively. .., End are added according to the order of the scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP uses a TFT liquid crystal display device to output information for a CRT (cathode ray tube) from a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source or a host (upper processing unit). This is a circuit that includes a circuit that exchanges information for use. << Equivalent Circuit of Storage Capacitor Cadd and Its Operation >> FIG. 12 shows an equivalent circuit of the pixel shown in FIG. In FIG. 12, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT.
The dielectric film of the parasitic capacitance Cgs is the insulating film GI and the anodic oxide film AOF. Cpix is a transparent pixel electrode ITO1 (PI
X) and a liquid crystal capacitance formed between the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitor Cpix is a liquid crystal LC, a protective film PSV1, and an alignment film ORI1, OR
I2. Vlc is a midpoint potential.

The storage capacitance element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, ΔVlc represents a change in the midpoint potential due to ΔVg. The change ΔVlc causes a DC component applied to the liquid crystal LC, but the value can be reduced as the storage capacitance Cadd is increased. Further, the holding capacitance element C
The add function has a function of prolonging the discharge time, and stores video information after the thin film transistor TFT is turned off for a long time. The reduction of the DC component applied to the liquid crystal LC improves the life of the liquid crystal LC, and can reduce so-called image sticking in which a previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. The midpoint potential Vlc has an adverse effect of being easily affected by the gate (scan) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cadd.

The storage capacitance of the storage capacitance element Cadd is
From the writing characteristics, it is 4 to 8 times (4 · C
pix <Cadd <8 · Cpix), 8 to 3 for the parasitic capacitance Cgs
Set to a value of about twice (8 · Cgs <Cadd <32 · Cgs)
You. << Connection method of storage capacitor element Cadd electrode line >> Storage capacitor electrode
Scanning signal line GL (Y₀)
Represents a common transparent pixel electrode ITO2 as shown in FIG.
(Vcom) is set to the same potential. In the example of FIG.
The scanning signal lines are the terminal GT0, the lead line INT, the terminal DT0 and
And the external electrode is short-circuited to the common electrode COM. Some
Is the first-stage storage capacitor electrode line Y ₀Is the final scanning signal line Y
end, connect to DC potential point (AC ground point) other than Vcom
Or one extra scan pulse from the vertical scan circuit V
SU₀May be connected to receive the same. << Connection Structure with External Circuit >> FIG. 21 shows a scanning signal driving circuit V
And an integrated circuit chip constituting the video signal drive circuits He and Ho
CHI is a flexible wiring board (commonly known as TAB, Tape)
 Automated Bonding)
It is a figure which shows the cross-section of a cage TCP, FIG.
Is the terminal DT of the video signal circuit of the liquid crystal display panel in this example.
FIG. 4 is a cross-sectional view of a main part showing a state connected to M.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI. ) Is the integrated circuit C
The HI bonding pads PAD are connected by a so-called face-down bonding method. Terminal TTB, T
The outer ends (commonly called outer leads) of the TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively.
CRT / TFT conversion circuit / power supply circuit S by soldering
A liquid crystal display panel P is formed on the UP by using an anisotropic conductive film ACF.
NL. The package TCP has a protective film PS whose leading end exposes the connection terminal DTM on the panel PNL side.
The external connection terminal DTM (GTM) is covered with at least one of the protective film PSV1 and the package TCP, so that it is resistant to electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that solder does not stick to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by an epoxy resin EPX or the like, and the space between the package TCP and the upper substrate SUB2 is further filled with a silicone resin SIL to multiplex protection. << Manufacturing Method >> Next, the substrate SU of the above-described liquid crystal display device
The manufacturing method on the B1 side will be described with reference to FIGS. In the same figure, the characters at the center are abbreviations of the process names, and the left side shows the flow of processing viewed from the cross-sectional shape near the gate terminal shown in FIG. Except for the process D, the processes A to I are classified according to the respective photographic processes, and any cross-sectional view of each process shows a stage where the processing after the photographic process is completed and the photoresist is removed. In the present description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 13 After a silicon oxide film SIO is provided on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. Film thickness of 1100Å on lower transparent glass substrate SUB1
The first conductive film g1 made of chromium is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a ceric ammonium nitrate solution as an etchant. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line SHg connecting the gate terminal GTM, the bus line SHd shorting the drain terminal DTM, and the anodized pad connected to the anodized bus line SHg (not shown) To form

Step B, FIG. 13 Al-Pd, Al-Si, Al-S having a thickness of 2800 °
Second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Is provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, and glacial acetic acid.

Step C, FIG. 13 After photo processing (after formation of the above-described anodizing mask AO), 3
% Tartaric acid adjusted to PH 6.25 ± 0.05 with ammonia
The prepared solution was diluted 1: 9 with ethylene glycol solution.
Substrate SUB1 is immersed in an anodizing solution composed of
0.5 mA / cm current density²Adjust to be
(Constant current formation). Next, the specified Al₂O₃Thickness is obtained
Anodization is performed until the formation voltage 125V required for
U. Thereafter, it is desirable to hold this state for several tens of minutes.
(Constant voltage formation). This is a uniform Al ₂O₃To get the membrane
It is important. As a result, the conductive film g2 becomes anodic acid.
And the scanning signal line GL, the gate electrode GT and the electrode P
An anodic oxide film AOF having a thickness of 1800 ° is formed on L1.
Step D, FIG. 14 Ammonia gas, silane gas, nitrogen gas
Gas to introduce a 2000-nm thick Si nitride film.
Introduce silane gas and hydrogen gas into plasma CVD equipment
Then, an i-type amorphous Si film having a thickness of 2000 ° was provided.
In addition, hydrogen gas and phosphine gas are supplied to the plasma CVD device.
Introduce N of 300Å⁺Type amorphous Si film
You.

Step E, FIG. 14 After photographic processing, SF ₆ and CC are used as dry etching gases.
Use l ₄ N ⁺ -type amorphous Si film, by selectively etching the i-type amorphous Si film, i-type semiconductor layer A
The island of S is formed.

Step F, FIG. 14 After the photographic processing, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Step G, FIG. 15 A first conductive film d1 made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photo processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the uppermost layer of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form

Step H, FIG. 15 A second conductive film d2 made of Cr having a thickness of 600 ° is provided by sputtering, and a second conductive film d2 having a thickness of 4000 ° is further formed.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as in the step B, and the second conductive film d2 is etched with the same liquid as in the step A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. I do. Next, CCl ₄ and SF ₆ are introduced into a dry etching apparatus, and N ⁺ type amorphous S
By etching the i film, the N ⁺ type semiconductor layer d0 between the source and the drain is selectively removed.

Step I, FIG. 15 An ammonia gas, a silane gas and a nitrogen gas are introduced into a plasma CVD apparatus to form a 1 μm-thick Si nitride film. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo etching technique using SF ₆ as a dry etching gas. << Overall Configuration of Liquid Crystal Display Module >> FIG. 23 is an exploded perspective view of the liquid crystal display module MDL, and the specific configuration of each component is shown in FIGS.

SHD is a shield case (= metal frame) made of a metal plate, LCW is a liquid crystal display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, MFR is an intermediate frame, BL is a backlight, and BLS is a backlight support. The body and LCA are a lower case, and the respective members are stacked in a vertical arrangement as shown in the figure to assemble a module MDL.

The module MDL includes a lower case LCA,
It has three types of holding members, an intermediate frame MFR and a shield case SHD. Each of these three members has a substantially box shape, is stacked in a stacking order in the order described above, and has a configuration in which a shield case SHD holds the other two members on which each component is mounted. Display panel PNL and light diffusion plate SP
B can be once placed on the intermediate frame MFR, and the backlight support BLS supporting the four backlights (cold cathode fluorescent tubes) BL can be once placed on the lower case LCA. Therefore, the necessary components are mounted on the two members of the lower case LCA and the intermediate frame MFR, respectively, and the two members can be stacked and manufactured without being turned upside down. There is an advantage that a good and highly reliable device can be provided. This is one of the major features of this module.

Hereinafter, each member will be described in detail. << Shield Case SHD >> FIG.
FIG. 25 is a diagram showing an upper surface, a front side surface, a rear side surface, a right side surface, and a left side surface of the HD, and FIG. 25 is a perspective view when the shield case SHD is viewed obliquely from above.

Shield case (metal frame) SHD
Is manufactured by punching or bending a single metal plate by a press working technique. LCW is the display panel P
An opening that exposes the NL to the field of view is shown, and is hereinafter referred to as a display window.

CL is a claw for fixing the intermediate frame MFR (19 in total), FK is a hook for fixing the lower case LCA (9 in total), and are provided integrally with the shield case SHD. The fixing claws CL in the state shown in the figure are bent inward at the time of assembling, so that the intermediate frames MFR are bent.
Is inserted into a square fixing claw hole CLH (see each side view in FIG. 27) provided in the. Thereby, the shield case S
The HD holds an intermediate frame MFR that holds and stores the display panel PNL and the like, and both are firmly fixed. The fixing hooks FK are fitted to fixing protrusions FKP (see each side view in FIG. 34) provided on the lower case LCA. Thereby, the shield case SHD holds the lower case LCA that holds and stores the backlight BL, the backlight support body BLS, and the like, and both are firmly fixed. The intermediate frame MFR and the lower case LCA are fitted at the peripheral edge, the shield case SHD is covered and fitted to the intermediate frame MFR, and the three members are united. A thin and long rectangular rubber spacer (rubber cushion, not shown) is provided around four edges that do not affect the display on the upper surface and the lower surface of the display panel PNL. The rubber spacer on the upper surface is interposed between the display panel PNL and the shield case SHD, and the rubber spacer on the lower surface is interposed between the display panel PNL, the intermediate frame MFR, and the light diffusion plate SPB. By using the elasticity of these rubber spacers to push the shield case SHD toward the inside of the device, the fixing hook FK is engaged with the fixing projection FKP, and both fixing members function as stoppers. Is bent and inserted into the claw hole CLH, the intermediate frame MFR and the lower case LCA are fixed by the shield case SHD, and the whole module is firmly held as one unit, and other fixing members are unnecessary. Therefore, assembling is easy and manufacturing costs can be reduced. Further, the mechanical strength is large, the vibration and shock resistance can be improved, and the reliability of the device can be improved. In addition, since the fixing nail CL and the fixing hook FK are easily removed (only the bending of the fixing nail CL is extended and the fixing hook FK is removed), disassembly and assembly of the three members are easy, so that repair is easy. The replacement of the backlight BL is also easy (the fixing hook FK of the lower case LCA, which has a high removal rate due to the backlight replacement or the like, is easier to remove than the fixing claw CL). In this module, the lower case LCA and the intermediate frame MFR are not only attached by the fixing member but also provided with four through holes LHL (FIGS.
It is further screwed with a screw hole MVH (see FIG. 28) and a screw of the intermediate frame MFR.

COH is a common through hole. Common through hole C
OH is the display panel P in addition to the shield case SHD.
NL drive circuit board PCB1, intermediate frame MFR drive circuit board PCB2, intermediate frame MFR, lower case LCA, two through-holes provided in common (at the same plane position). By inserting the common through holes COH into the pins that are set up in order from the lower case LCA and mounting the components, the relative positions of the members and the components are accurately set. When the module MDL is mounted on an application product such as a personal computer, the common through hole COH can be used as a reference for positioning.

FG is six frame grounds formed integrally with the metal shield case SHD, and extends into a "U" -shaped opening opened in the shield case SHD, in other words, into a square opening. It is constituted by an elongated projection. The elongated projections are bent in the direction toward the inside of the device, and are connected by soldering to a frame ground pad FGP (FIG. 26) to which the ground line of the drive circuit board PCB1 of the display panel PNL is connected. I have. << Display panel PNL and drive circuit board PCB1 >> FIG.
FIG. 17 is a top view showing a state where a drive circuit is mounted on the display panel PNL shown in FIG. 16 and the like.

CHI is a driving IC chip for driving the display panel PNL (the lower three are driving ICs on the vertical scanning circuit side)
Chips, 6 each on the left and right sides, drive I on the video signal drive circuit side
C chip). TCP is a tape carrier package in which the driving IC chip CHI is mounted by the tape automated bonding method (TAB) as described with reference to FIGS. 21 and 22, and PCB1 is a PCB (printing) in which TCP, a capacitor CDS, etc. are mounted, respectively. Ted
Circuit board), which is divided into three parts. FGP is a frame ground pad. FC is a flat cable that electrically connects the lower drive circuit board PCB1 to the left drive circuit board PCB1 and the lower drive circuit board PCB1 to the right drive circuit board PCB1. As shown in the figure, as the flat cable FC, as shown in FIG.
(Plated) is used by sandwiching and supporting a striped polyethylene layer and a polyvinyl alcohol layer. << Drive Circuit Board PCB1 >> The drive circuit board PCB1 is divided into three parts as shown in FIG.
, And are electrically and mechanically connected by two flat cables FC. Since the drive circuit board PCB1 is divided, the stress (stress) generated in the long axis direction of the drive circuit board PCB1 due to the difference in the coefficient of thermal expansion between the display panel PNL and the drive circuit board PCB1 is absorbed at the flat cable FC. In addition, peeling of the output leads (TTM in FIGS. 21 and 22) of the tape carrier package TCP tape having a weak connection strength and the external connection terminals DTM (GTM) of the display panel can be prevented, and the reliability of the module against heat can be improved. In such a substrate dividing method, a large number of substrates PCB1 can be obtained from one substrate material because each has a simple rectangular shape as compared with a single “U” -shaped substrate. There is an effect that the utilization rate of the printed circuit board material is increased and the cost of parts and materials can be reduced (in the case of this embodiment, reduced to about 50%). If a flexible FPC (flexible printed circuit) is used for the drive circuit board PCB1 instead of the PCB, the FPC bends, so that the effect of preventing lead peeling can be further enhanced. It is also possible to use an integrated "U" -shaped PCB that is not divided,
In this case, the number of steps is reduced, the number of parts is reduced, the production process management is simplified, and the reliability is improved by eliminating the connection cable between PCBs.

Each drive circuit board PCB1 divided into three parts
As shown in FIG. 26, two frame ground pads FGP connected to each ground line are provided for each substrate, that is, six in total. When the drive circuit board PCB1 is divided into a plurality of parts, if at least one of the drive circuit boards is connected to the frame ground in terms of DC,
Although there is no electrical problem, if there are few locations in the high frequency range, the EMI (Electro-Magnetic)
The generation potential of unnecessary radiated radio waves causing interference (interference) increases. In particular, in a module MDL using a thin film transistor, since a high-speed clock is used, it is difficult to take measures against EMI. In order to prevent this, ground wiring (AC ground potential) is connected to a common frame (i.e., a shield) at a sufficiently low impedance at at least one position in each of the plurality of divided drive circuit boards PCB1, and in this embodiment, at two positions. (Case SHD). As a result, the ground line in the high-frequency region is strengthened. In comparison with the case where only one shield case is connected to the shield case SHD as a whole, the electric field intensity of radiation is improved by 5 dB or more in the six cases in the present embodiment. Was done.

The frame ground FG of the shield case SHD is formed of a metal elongated projection, and can be easily connected to the frame ground pad FGP of the display panel PNL by bending, and no special wire (lead wire) for connection is required. It is. Further, since the shield case SHD and the driving circuit board PCB1 can be mechanically connected via the frame ground FG, the mechanical strength of the driving circuit board PCB1 can be improved. << Intermediate Frame MFR >> FIG.
Top view, front side view, rear side view, right side view, left side view,
FIG. 28 is a bottom view of the intermediate frame MFR, and FIG. 29 is a perspective view of the intermediate frame MFR as viewed from above.

The intermediate frame MFR is a drive circuit board PCB
Liquid crystal display unit LCD, light diffusion plate SP integrated with 1
This is a holding member for the B and L-shaped drive circuit boards PCB2.

BLW is a backlight light taking-in window for taking in the light of the backlight BL into the liquid crystal display portion LCD, and the light diffusing plate SPB is placed and held here. SPB
S is a holder for the light diffusion plate SPB. RDW is a heat dissipation hole, and CW is a notch for a connector to be connected to the outside. The MVH has four screw holes, and the lower case LCA and the intermediate frame MFR are fixed by screws (not shown) via the screw holes MVH and the through holes LHL (see FIGS. 34 to 36) of the lower case LCA. You. CLH is a fixing claw hole into which the fixing claw CL of the shield case SHD is inserted (see each side view in FIG. 27 and FIG. 29). 2HL is a fixing hole of the drive circuit board PCB2 (see FIG. 30), into which a stopper such as a nylon rivet is inserted. The L-shaped drive circuit board PCB2 is arranged in the L-shaped region on the right and lower edges of the top view of the intermediate frame MFR in FIG. The intermediate frame MFR is formed of the same white synthetic resin as the backlight support BLS and the lower case LCA.
Also, since the intermediate frame MFR is made of synthetic resin, the driving circuit board PCB1 and the driving circuit board PCB
2 is advantageous in terms of insulation. << Light Diffusion Plate SPB >> The light diffusion plate SPB (see FIG. 23)
Backlight light intake window BLW of intermediate frame MFR
The holding portions SPBS provided on the four peripheral edges of FIG.
See FIG. (Lower than the upper surface of the intermediate frame MFR). When the light diffusion plate SPB is placed on the holding part SPBS, the upper surface of the light diffusion plate SPB and the upper surface of the intermediate frame MFR are flush with each other. On the light diffusion plate SPB, a liquid crystal display unit LCD integrated with the drive circuit board PCB1 is mounted. Between the liquid crystal display part LCD and the light diffusion plate SPB, four rubber spacers are arranged around four edges on the lower surface of the liquid crystal display part LCD (not shown; see the description of << Shield case SHD >>). LCD interposed LCD
The space between the light diffusion plate SPB and the light diffusion plate SPB is sealed by these rubber spacers. That is, the light diffusion plate SPB is mounted on the intermediate frame MFR (frame), the upper surface of the light diffusion plate SPB is covered by the liquid crystal display LCD, and the gap between the liquid crystal display LCD and the light diffusion plate SPB is provided. Is completely sealed by a rubber spacer (the light diffusion plate SPB and the liquid crystal display unit LCD are integrated and fixed independently of the backlight unit using the intermediate frame MFR). Therefore, foreign matter may enter between the liquid crystal display part LCD and the light diffusion plate SPB,
It is possible to suppress the problem that the foreign matter attached to the display area other than the display area due to static electricity or the like moves to the display area and the display quality deteriorates. Since the light diffusion plate SPB is thicker than the light diffusion sheet, the presence of foreign matter on the lower surface side of the light diffusion plate SPB is inconspicuous. Further, the foreign matter present on the lower surface side of the light diffusion plate SPB is far from the liquid crystal display unit LCD, so it is difficult to focus, and the image is diffused, so that there is almost no problem. Further, since the light diffusion plate SPB and the liquid crystal display unit LCD are sequentially held in the intermediate frame MFR, the assembling property is also good. << Drive Circuit Board PCB2 >> FIG. 30 shows a drive circuit board PC.
It is a bottom view of B2. As shown in FIG. 30, the drive circuit board PCB2 of the liquid crystal display portion LCD held and housed in the intermediate frame MFR has an L-shape, and has mounted thereon electronic components such as ICs, capacitors, and resistors. The drive circuit board PCB2 includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and information for a CRT (cathode ray tube) from a host (upper processing unit). A circuit including a circuit for converting information into information for a TFT liquid crystal display device is mounted. CJ is a connector connection portion to which a connector (not shown) connected to the outside is connected. The drive circuit board PCB2 and the drive circuit board PCB1 correspond to FIG.
As shown in FIG. 1, they are electrically connected by a flat cable FC (details will be described later). Also, the drive circuit board PCB2
And the inverter circuit board IPCB are the drive circuit board PC
A connector hole CHL provided in the intermediate frame MFR by a backlight connector and a backlight cable (not shown) connected to the backlight connection portion BC2 of B2 and the backlight connection portion BCI of the inverter circuit board IPCB (see FIGS. 27 to 29). Are electrically connected via << Electrical Connection between Drive Circuit Board PCB1 and Drive Circuit Board PCB2 >> FIG. 31 shows the connection between the drive circuit board PCB1 of the liquid crystal display unit LCD (the upper surface is visible) and the drive circuit board PCB2 of the intermediate frame MFR (the lower surface is visible). It is a top view which shows a connection state.

Liquid crystal display section LCD and drive circuit board PCB2
Are electrically connected by a foldable flat cable FC. An operation check can be performed in this state. The drive circuit board PCB2 is formed by bending the flat cable FC by 180 ° so that the liquid crystal display section LCD is formed.
The drive circuit board PCB1 integrated with the liquid crystal display portion LCD is mounted on the lower surface of the intermediate frame MFR, fitted in a predetermined recess of the intermediate frame MFR, fixed with a fastener such as a nylon rivet, or the like. Placed and retained. << Backlight Support BLS >> FIG. 32 is a top view, a rear side view, a right side view, and a left side view of the backlight support BLS, and FIG. 33 is a perspective view of the backlight support BLS seen from the top side. is there.

The backlight support BLS includes four backlights (cold cathode fluorescent lamps) BL (see FIGS. 37 and 23).
I support. SPC is a hole (space), and the backlight support BLS forms a frame.

The backlight support BLS uses the four backlights BL as white silicone rubber SG (FIGS. 37 and 3).
9). Reference numeral SS denotes a backlight support portion, which supports both ends of each backlight BL via silicon rubber SG. The silicone rubber SG also serves to prevent foreign matter from entering the lighting area of the backlight BL. RH is a lead hole through which lead wires LD (see FIG. 37) connected to both ends of the backlight BL pass.

SHL are four through holes provided in the backlight support BLS, which coincide with the screw holes LVH of the lower case LCA, and are fixed to the lower case LCA by screws (not shown).

The SRM is shown in FIG.
The backlights BL formed on both left and right inner side surfaces (the outer two backlights B among the four backlights BL)
L), the light from the backlight BL is efficiently reflected toward the liquid crystal display unit LCD in the same manner as the upper surface of the backlight light reflection mountain RM (see FIGS. 34 and 36) of the lower case LCA. (See the description of << Lower Case >>). Note that the backlight support BLS is connected to the intermediate frame MF.
R, made by molding with the same white synthetic resin as the lower case LCA. << Lower Case LCA >> FIG. 34 is a top view (reflection side), rear side view, right side view, left side view, and FIG.
5 is a bottom view of the lower case LCA, FIG. 36 is a perspective view of the lower case LCA as viewed from above, and FIG. 38 is a cross-sectional view of the lower case LCA (cross-section taken along line 38-38 in FIG. 34). Figure).

The lower case LCA includes a backlight BL,
The backlight support member BLS is a holding member (backlight storage case) for the inverter circuit board IPCB for turning on the backlight BL, and also serves as a backlight light reflection plate for the backlight BL. It is made by integrally molding with a single mold using a white synthetic resin that is a color that reflects efficiently. On the upper surface of the lower case LCA, three backlight light reflection ridges RM formed integrally with the lower case LCA are formed, and constitute a backlight light reflection surface of the backlight BL. The three backlight light reflection peaks RM are composed of a combination of a plurality of planes for efficiently reflecting the light of the backlight BL toward the liquid crystal display LCD. That is, as shown in the cross-sectional view of FIG. 38, the cross-sectional shape of the backlight light reflection mountain RM is formed by an approximate straight line of a curve obtained by calculation so as to reflect the light of the backlight BL most efficiently. I have. The height of the backlight light reflection mountain RM is:
It is higher than the upper surface of the backlight BL to increase the reflectance (see FIG. 39). As described above, since the storage case of the backlight BL and the backlight light reflection plate of the backlight BL are formed as an integral member, the number of parts can be reduced, the structure can be simplified, and the manufacturing cost can be reduced. Therefore, the vibration shock resistance and the heat shock resistance of the device can be improved, and the reliability can be improved. Also, the lower case LCA is
Because it is made of synthetic resin, the inverter circuit board IP
This is advantageous for CB insulation.

Note that LVH has four screw holes, and the screw holes LVH and the through holes SH of the backlight support member BLS.
The backlight support BLS is fixed to the lower case LCA by screws (not shown) via L (see FIGS. 32 and 33). LHL is four through holes, and this through hole LH
L and screw hole MVH of intermediate frame MFR (see Fig. 28)
, The intermediate frame MFR and the lower case LCA are fixed by screws (not shown). IHL is an inverter circuit board IPC into which fasteners such as nylon rivets are inserted.
B is a fixing hole, CW is a notch for a connector to be connected to the outside, and FKP is a fixing hook F of a shield case SHD.
K is a fixing projection to be fitted (see each side view of FIG. 34, FIG. 36). << Backlight BL >> FIG. 37 is a top view, a rear side view, a right side view, a left side view, and a view showing a state where the backlight support BLS, the backlight BL, and the inverter circuit board IPCB are mounted on the lower case LCA. 39 is 39- of FIG.
It is sectional drawing in 39 cutting lines.

The backlight BL is a direct-type backlight that is disposed directly below the liquid crystal display LCD. The backlight BL includes four cold cathode fluorescent tubes, is supported by the backlight support BLS, and is attached to the lower case LCA using screws (not shown) in the lower case LCA. By fixing through the SHL and the screw holes LVH of the lower case LCA, it is held by the lower case LCA which is a backlight storage case.

The ECL is the sealing side of the cold-cathode tube (the side on which the phosphor is applied to the inner surface of the tube, the vacuum is drawn by drawing a gas, or the gas is sealed). As shown in FIG. 37, the sealing ECLs of the four backlights BL arranged side by side are arranged alternately left and right (in FIG. 37, alternately up and down) (staggered arrangement). As a result, the left and right inclination of the color temperature of the display screen caused by the application of the fluorescent material on the fluorescent tube (the color temperature is higher on the sealing side) can be made inconspicuous, and the display quality can be improved. << Inverter circuit board IPCB >> Inverter circuit IPC
B is a lighting circuit board for the four backlights BL, which is mounted on the lower case LCA as shown in FIG. 37 and has fixing holes IHL in the lower case LCA (see FIGS. 34 to 36).
And is fixed by a fastener such as a nylon rivet (not shown). On the inverter circuit IPCB, two transformers TF1, TF2 and electronic components such as capacitors, coils, and resistors are mounted. The inverter circuit board IPCB serving as a heat source is located on the upper side of the device (in FIG. 37,
(Shown on the left side of the top view), so that heat dissipation is good. The inverter circuit board IPCB is disposed on the upper side of the apparatus, and the L-shaped drive circuit board PCB2 is disposed on the lower side and the left side of the apparatus (L-shaped areas on the right and lower edges of the top view of the intermediate frame MFR in FIG. 27). The inverter circuit board IPCB and the drive circuit board PCB2 serving as heat sources are arranged so as not to overlap with each other from the viewpoint of heat dissipation and reducing the thickness of the entire module. << Backlight BL, backlight support BLS, inverter circuit board IPCB >> Backlight support BLS
After fitting four backlights BL each having a lead wire LD (see FIG. 37) at each end, (before storing and fixing the backlight support BLS and the inverter circuit board IPCB to the lower case LCA) 2) Each backlight B
The L lead wire LD is soldered to the inverter circuit board IPCB. Thus, one unit is configured by the backlight BL, the backlight support member BLS, and the inverter circuit board IPCB (see FIGS. 23 and 37). In this state, a lighting test of the backlight BL can be performed. In the past, the backlight and the inverter circuit board were each fixed to the backlight storage case, and then the lead wires of the backlight were soldered to the inverter circuit board, so the space for soldering was very narrow, Although the workability was poor, in this module, before the backlight BL and the inverter circuit board IPCB were fixed to the lower case LCA, reading of the backlight BL with the backlight BL supported by the backlight support body BLS was performed. Since the line LD can be soldered to the inverter circuit board IPCB, workability is good. Further, when a defective component occurs, it is easy to replace the component. When the light-on test is completed, as shown in FIG. 37, the inverter circuit board IPCB is fixed to the lower case LCA using a fastener such as a nylon rivet.
HL, and the backlight support BLS is screwed with four through holes SHL and screw holes LVH by screws (not shown).
(Refer to FIG. 36 and FIG. 34).

Conventionally, six cold cathode tubes and two inverter circuit boards are used, and three cold cathode tubes are turned on per inverter circuit board (each having two transformers). The two inverter circuit boards are located on the upper and lower sides of the backlight in the backlight storage case (Fig. 3).
7, the size of the entire backlight portion is increased because the lower case LCA is disposed on the left and right sides of the top view, and two inverter circuit boards, which are heat sources, are disposed on the upper and lower sides. There was a problem in heat dissipation. However, in this device, since only one inverter circuit board IPCB is used, the size of the entire backlight unit can be reduced, and heat radiation is good. Further, in the present device, since the inverter circuit board IPCB is disposed on the upper side of the device (in FIG. 37, shown on the left side of the top view), heat radiation is good.

[0082]

As described above, according to the present invention,
The number of parts can be reduced, the structure can be simplified, and the manufacturing cost can be reduced. Therefore, the vibration shock resistance and the heat shock resistance of the liquid crystal display module can be improved, and the reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in an active matrix type color liquid crystal display device to which the present invention is applied.

FIG. 2 is a cross-sectional view showing one pixel and a periphery thereof taken along a cutting line 2-2 in FIG. 1;

FIG. 3 is a sectional view of the additional capacitance Cadd taken along section line 3-3 in FIG. 1;

FIG. 4 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 1 are arranged.

FIG. 5 is a plan view illustrating only layers g2 and AS of the pixel illustrated in FIG. 1;

FIG. 6 is a plan view illustrating only layers d1, d2, and d3 of the pixel shown in FIG.

FIG. 7 is a plan view illustrating only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel illustrated in FIG.

FIG. 8 is a plan view of a main part, in which only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel array shown in FIG. 6 are drawn.

FIG. 9 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 10 is a plan view and a sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 11 is an equivalent circuit diagram showing a liquid crystal display section of an active matrix type color liquid crystal display device.

FIG. 12 is an equivalent circuit diagram of the pixel shown in FIG.

FIG. 13 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes A to C on the substrate SUB1 side.

FIG. 14 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes D to F on the substrate SUB1 side.

FIG. 15 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes GI on the substrate SUB1 side.

FIG. 16 is a plan view for describing a configuration of a matrix peripheral portion of a display panel.

FIG. 17 is a panel plan view for explaining in more detail the peripheral portion of FIG. 16 in a slightly exaggerated manner.

FIG. 18 is an enlarged plan view of a corner portion of the display panel including an electrical connection portion between the upper and lower substrates.

FIG. 19 is a cross-sectional view showing the vicinity of a panel corner and the vicinity of a video signal terminal on both sides with the pixel portion of the matrix at the center.

FIG. 20 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 21 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.

FIG. 22 is a fragmentary cross-sectional view showing a state where the tape carrier package TCP is connected to a video signal circuit terminal DTM of the liquid crystal display panel PNL.

FIG. 23 is an exploded perspective view of the liquid crystal display module.

FIG. 24 is a top view, a front side view, a rear side view, a right side view, and a left side view of the shield case of the liquid crystal display module.

FIG. 25 is a perspective view of the shield case as seen from the top side.

FIG. 26 is a top view showing a state where peripheral driving circuits are mounted on a liquid crystal display panel.

FIG. 27 is a top view, a front side view, a rear side view, a right side view, and a left side view of the intermediate frame.

FIG. 28 is a bottom view of the intermediate frame.

FIG. 29 is a perspective view of the intermediate frame as viewed from above.

FIG. 30 is a bottom view of the drive circuit board mounted on the intermediate frame.

FIG. 31 shows a drive circuit board of the liquid crystal display unit (the upper surface is visible).
FIG. 4 is a top view showing a connection state between the driving circuit board of the intermediate frame (a lower surface is visible).

FIG. 32 is a top view, a rear side view, a right side view, and a left side view of the backlight support.

FIG. 33 is a perspective view of the backlight support as viewed from above.

FIG. 34 is a top view (reflection side), a rear side view, and the like of the lower case.
It is a right side view and a left side view.

FIG. 35 is a bottom view of the lower case.

FIG. 36 is a perspective view of the lower case viewed from the upper surface side.

FIG. 37 is a top view, a rear side view, a right side view, and a left side view showing a state where a backlight support, a backlight, and an inverter circuit board are mounted on a lower case.

38 is a cross-sectional view of the lower case (a cross-sectional view taken along line 38-38 in FIG. 34).

FIG. 39 is a sectional view taken along section line 39-39 in FIG. 37;

[Explanation of symbols]

SUB: transparent glass substrate, GL: scanning signal line, DL: video signal line GI: insulating film, GT: gate electrode, AS: i-type semiconductor layer SD: source or drain electrode, PSV: protective film, BM: light shielding film LC: liquid crystal, TFT: thin film transistor, ITO: transparent pixel electrode g, d: conductive film, Cadd: storage capacitor element, AOF: anodized film AO: anodized mask, GTM: gate terminal, DTM ...
Drain terminal SHD: Shield case, PNL: Liquid crystal display panel, S
PB: light diffusion plate, MFR: intermediate frame, BL: backlight, BLS: backlight support, LCA: lower case, RM: backlight light reflection mountain.

Continuing from the front page (72) Inventor Junichi Owada 3300 Hayano, Mobara-shi, Chiba Pref., Hitachi, Ltd. Mobara Plant, Hitachi, Ltd. (72) Inventor Akira Kobayashi 3300, Hayano, Mobara-shi, Chiba Pref., Hitachi, Ltd. Author Yu Fujita 3300 Hayano, Mobara-shi, Chiba Pref. In Hitachi, Ltd.Mobara Factory (72) Inventor Hiroshi Nakamoto 3300 Hayano, Mobara-shi, Chiba Pref. In Mobara factory, Hitachi (72) Inventor Takashi Ono, Hayano, Mobara-shi, Chiba Pref. 3681 Hitachi Device Engineering Co., Ltd. (72) Inventor Tsutomu Isono 3681 Hayano Mobara City, Chiba Prefecture Hitachi Device Engineering Co., Ltd.

Claims (7)

[Claims] A liquid crystal display panel, a frame member on which the liquid crystal display panel is mounted on the upper side, and a backlight portion mounted on the lower side thereof; and a flat cable electrically connected to the liquid crystal display panel; A circuit board fitted to the frame member so as to overlap an end of the liquid crystal display panel along two adjacent sides of the liquid crystal display panel; and a connector connected to an external device on the circuit board. A liquid crystal display device having a power supply circuit mounted thereon. 2. A liquid crystal display panel, a metal frame disposed above the liquid crystal display panel and having a display window and a fixing claw formed thereon, and the liquid crystal display panel mounted above the liquid crystal display panel and a backside disposed below the liquid crystal display panel. A resin frame member having a hole in which a light portion is mounted and into which the fixing claw is inserted; and a liquid crystal which is electrically connected to the liquid crystal display panel through a flat cable and extends along two adjacent sides of the liquid crystal display panel. A circuit board fitted to the frame member so as to overlap an end of the display panel, wherein a connector and a power supply circuit connected to an external device are mounted on the circuit board. Liquid crystal display. 3. The flat cable connected to the circuit board is bent by 180 °.
Or the liquid crystal display device according to 2. 4. A liquid crystal display panel having a driving circuit board provided on a peripheral portion thereof, a frame member having the liquid crystal display panel mounted thereon and a backlight portion mounted below the liquid crystal display panel; A circuit board connected to the substrate and fitted to the frame member so as to overlap an end of the liquid crystal display panel along two adjacent sides of the liquid crystal display panel; A liquid crystal display device comprising a connector and a power supply circuit connected to the liquid crystal display. 5. The frame member is a resin frame member having a fixing hole, and a metal frame having a display window bends a fixing claw formed on the metal frame and inserts the same into the fixing hole. 5. The liquid crystal display device according to claim 4, wherein the liquid crystal display device is fixed above the liquid crystal display panel. 6. The drive circuit board according to claim 4, wherein said drive circuit board is a flexible printed circuit.
Or the liquid crystal display device according to 5. 7. The liquid crystal display panel according to claim 1, wherein portions of the circuit board along two adjacent sides of the liquid crystal display panel are L-shaped. Liquid crystal display device.