JP2001244464A - Method of manufacturing metal oxide transistor - Google Patents
Method of manufacturing metal oxide transistorInfo
- Publication number
- JP2001244464A JP2001244464A JP2000057440A JP2000057440A JP2001244464A JP 2001244464 A JP2001244464 A JP 2001244464A JP 2000057440 A JP2000057440 A JP 2000057440A JP 2000057440 A JP2000057440 A JP 2000057440A JP 2001244464 A JP2001244464 A JP 2001244464A
- Authority
- JP
- Japan
- Prior art keywords
- metal oxide
- insulating film
- gate insulating
- channel layer
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 32
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000010408 film Substances 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 23
- 239000010409 thin film Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000000725 suspension Substances 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 21
- 239000002131 composite material Substances 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000003618 dip coating Methods 0.000 description 4
- 238000002441 X-ray diffraction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910004283 SiO 4 Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- ZBCBWPMODOFKDW-UHFFFAOYSA-N diethanolamine Chemical compound OCCNCCO ZBCBWPMODOFKDW-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000007062 hydrolysis Effects 0.000 description 1
- 238000006460 hydrolysis reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は金属酸化物半導体
を用いて金属−絶縁膜−半導体構造の電界効果形トラン
ジスタを製造する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor having a metal-insulating film-semiconductor structure using a metal oxide semiconductor.
【０００２】[0002]
【従来の技術】従来のトランジスタは単結晶シリコンに
不純物を拡散させ気相成長させたり、あるいは化合物半
導体を気相成長させてｐ−ｎ接合を形成して製造するも
のが主流である。これらの場合は排ガスの処理に大きな
設備と、処理費用を要した。一方、ゾル−ゲル（Ｓｏｌ
−Ｇｅｌ）法に代表される溶液法により金属酸化物半導
体を作製すれば排ガス処理の問題がなく、比較的簡単な
設備で安価に作ることが可能である。しかし酸化物半導
体は、一般に移動度が低いため、Ｓｉ、Ｇｅ、化合物半
導体と比較して扱いにくい欠点があった。またゾル−ゲ
ル法によって作製された薄膜はポーラスであることが多
く、ガスセンサのように膜表面での吸着反応を利用する
ことは試みられているが、厚さ方向の電導現象はほとん
ど利用されていない。2. Description of the Related Art Conventionally, a transistor is mainly manufactured by diffusing impurities into single crystal silicon and performing vapor phase growth or by growing a compound semiconductor by vapor phase to form a pn junction. In these cases, large facilities and processing costs were required for treating the exhaust gas. On the other hand, sol-gel (Sol
-If the metal oxide semiconductor is manufactured by a solution method typified by the (Gel) method, there is no problem of the exhaust gas treatment, and the metal oxide semiconductor can be manufactured at a low cost with relatively simple equipment. However, oxide semiconductors generally have low mobility, and thus have a drawback that they are difficult to handle as compared with Si, Ge, and compound semiconductors. In addition, thin films prepared by the sol-gel method are often porous, and attempts have been made to utilize the adsorption reaction on the film surface as in the case of gas sensors, but most of the conduction phenomena in the thickness direction have been used. Absent.
【０００３】例えば図５に示すように基板１１上に、Ｎ
ｉＯなどのｎ形金属酸化物層１２を形成し、その上にＴ
ｉＯなどのｐ形金属酸化物層１３を溶液法により形成
し、更にその上にＮｉＯなどのｎ形金属酸化物層１４を
溶液法により形成して接合形トランジスタを構成するこ
とが考えられる。しかし各金属酸化物層の形成ごとに、
６００〜８００℃程度の高温加熱を必要とするため、ｐ
形金属酸化物層１３を形成する際に、その下のｎ形金属
酸化物層１２とｐ形金属酸化物層１３との境界に両層の
複合酸化物膜１５が生成され、またｎ形金属酸化物層１
４を形成する際にそのｎ形金属酸化物層１４とｐ形金属
酸化物層１３との境界に両層の複合酸化物膜１６が生成
され、しかも先に形成された複合酸化物膜１５が成長し
て、その膜厚が厚くなる。この複合酸化物膜、特に１５
が完全な絶縁物となり、電子や正孔が移動することがで
きず、トランジスタとして作用させることが困難であ
る。[0003] For example, as shown in FIG.
An n-type metal oxide layer 12 such as iO is formed, and T
It is considered that a p-type metal oxide layer 13 such as iO is formed by a solution method, and an n-type metal oxide layer 14 such as NiO is further formed thereon by a solution method to form a junction transistor. However, with each metal oxide layer formation,
Since high-temperature heating of about 600 to 800 ° C. is required, p
When the n-type metal oxide layer 13 is formed, a composite oxide film 15 of both layers is generated at a boundary between the n-type metal oxide layer 12 and the p-type metal oxide layer 13 thereunder. Oxide layer 1
At the time of forming 4, a composite oxide film 16 of both layers is formed at the boundary between the n-type metal oxide layer 14 and the p-type metal oxide layer 13, and the previously formed composite oxide film 15 It grows and its film thickness increases. This composite oxide film, especially 15
Becomes a perfect insulator, electrons and holes cannot move, and it is difficult to function as a transistor.
【０００４】あるいは図６に示すように、シリコン基板
１１上にＮｉＯのようなｎ形金属酸化層よりなるチャネ
ル層１７を溶液法により形成し、そのチャネル層１７上
の一部にＳｉＯ2 などのゲート絶縁膜１８を溶液法によ
り形成し、ゲート絶縁膜１８上にゲート電極１９を、ゲ
ート絶縁膜１８の両側においてチャネル層１７上にソー
ス電極２１、ドレイン電極２２を形成して、Ｍ−Ｉ−Ｓ
構造の電界効果形トランジスタを構成することも考えら
れる。この場合は、ゲート絶縁膜１８の形成後に、高温
に加熱することがないため、チャネル層１７とゲート絶
縁膜１８の境界に生じる複合酸化物膜はそれ程厚いもの
にはならない。しかし、チャネル層１７上に、ゲート絶
縁膜１８を溶液法で作る場合、絶縁性の良好なものを作
ることが困難であった。Alternatively, as shown in FIG. 6, a channel layer 17 made of an n-type metal oxide layer such as NiO is formed on a silicon substrate 11 by a solution method, and a portion of the channel layer 17 such as SiO 2 is formed on the channel layer 17. A gate insulating film 18 is formed by a solution method, a gate electrode 19 is formed on the gate insulating film 18, and a source electrode 21 and a drain electrode 22 are formed on the channel layer 17 on both sides of the gate insulating film 18. S
It is also conceivable to construct a field-effect transistor having a structure. In this case, since the gate insulating film 18 is not heated to a high temperature after the formation, the composite oxide film formed at the boundary between the channel layer 17 and the gate insulating film 18 is not so thick. However, when the gate insulating film 18 is formed on the channel layer 17 by a solution method, it is difficult to form a gate insulating film 18 having good insulating properties.
【０００５】[0005]
【発明が解決しようとする課題】以上述べたように、溶
液法により金属酸化物半導体を作製すれば製造設備が比
較的簡単な半導体素子を作ることができるが、従来にお
いてはトランジスタを作ることが困難であった。As described above, if a metal oxide semiconductor is manufactured by a solution method, a semiconductor device whose manufacturing equipment is relatively simple can be manufactured, but conventionally, a transistor cannot be manufactured. It was difficult.
【０００６】[0006]
【課題を解決するための手段】この発明によれば基板上
にゲート絶縁膜を形成し、そのゲート絶縁膜上にｎ形又
はｐ形金属酸化物半導体薄膜を溶液法で作ってチャネル
層を形成し、そのチャネル層上にソース電極及びドレイ
ン電極を形成する。上記溶液法によるチャネル層の形成
は、比較的低い温度で金属酸化物を析出させた後、その
温度より高い温度で析出した金属酸化物を酸化させて金
属酸化物半導体薄膜を得ることが好ましい。According to the present invention, a gate insulating film is formed on a substrate, and an n-type or p-type metal oxide semiconductor thin film is formed on the gate insulating film by a solution method to form a channel layer. Then, a source electrode and a drain electrode are formed on the channel layer. In the formation of the channel layer by the above solution method, it is preferable to deposit a metal oxide at a relatively low temperature and then oxidize the deposited metal oxide at a temperature higher than that temperature to obtain a metal oxide semiconductor thin film.
【０００７】[0007]
【発明の実施の形態】図１にこの発明の実施例を示す。
先ず例えば（１００）単結晶シリコン（ｎ形、１．４×
１０-2Ωｃｍ）の基板３１を用意し、その基板３１上に
ゲート絶縁膜３２を形成する。このゲート絶縁膜３２は
基板３１を熱酸化してＳｉＯ2 膜を形成して作ることが
できる。あるいはスパッタリングによりＳｉＯ2 膜を形
成してもよい。ゲート絶縁膜３２の厚さは例えば１３０
ｎｍとする。FIG. 1 shows an embodiment of the present invention.
First, for example, (100) single crystal silicon (n-type, 1.4 ×
A substrate 31 of 10 −2 Ωcm) is prepared, and a gate insulating film 32 is formed on the substrate 31. The gate insulating film 32 can be formed by thermally oxidizing the substrate 31 to form an SiO 2 film. Alternatively, an SiO 2 film may be formed by sputtering. The thickness of the gate insulating film 32 is, for example, 130
nm.
【０００８】このゲート絶縁膜３２上にｎ形又はｐ形の
金属酸化物半導体薄膜を溶液法により形成してチャネル
層３３とする（図１Ｂ）。例えば有機金属液体としてＺ
ｎ（ＯＡｃ）2 ・４Ｈ2 Ｏを用い、これをイソプロパノ
ール（アルコールの一種）に懸濁させ、Ｚｎに対し等モ
ルのジエタノールアミンを加水分解抑止剤として添加し
て溶解し、更に２倍モルの水を添加して０．４ｍｏｌ／
ｌの溶液を調整する。この溶液をディップコーティング
法、又はスプレイ法、スピンコーティング法によりゲー
ト絶縁膜３２上にコーティングする。ディップコーティ
ングの場合、溶液中から６ｃｍ／分の引き上げ速度で基
板３１を引き上げると１回のコーティングで２０ｎｍの
ＺｎＯ膜が形成されるが、例えばＺｎＯの膜厚、つまり
チャネル層３３の膜厚が４０ｎｍになるようにコーティ
ングを行い、その後、６００℃〜９００℃の温度で空気
中又は酸素雰囲気中で加熱処理を行い、ＺｎＯの膜、つ
まりチャネル層３３を形成する。An n-type or p-type metal oxide semiconductor thin film is formed on the gate insulating film 32 by a solution method to form a channel layer 33 (FIG. 1B). For example, Z as an organic metal liquid
Using n (OAc) 2 .4H 2 O, this was suspended in isopropanol (a type of alcohol), and dissolved by adding an equimolar amount of diethanolamine to Zn as a hydrolysis inhibitor, and further dissolved in 2 times water. 0.4 mol /
Prepare 1 solution. This solution is coated on the gate insulating film 32 by a dip coating method, a spray method, or a spin coating method. In the case of dip coating, when the substrate 31 is pulled up from the solution at a pulling rate of 6 cm / min, a ZnO film of 20 nm is formed by one coating. For example, the thickness of the ZnO film, that is, the thickness of the channel layer 33 is 40 nm. Then, heat treatment is performed in air or an oxygen atmosphere at a temperature of 600 ° C. to 900 ° C. to form a ZnO film, that is, a channel layer 33.
【０００９】次に図１Ｃに示すように、チャネル層３３
上に金属膜により、ソース電極３４とドレイン電極３５
を形成して電界効果形トランジスタ（ＦＥＴ）を得る。
必要に応じて基板３１のゲート絶縁膜３２と反対側にゲ
ート電極３６を形成する。基板３１自体をゲート電極と
してもよい。電極３４，３５，３６は例えばＡｕの蒸着
により、或いはＩＴＯ（インジウム、スズ酸化膜）など
の透明電極材の溶液法により形成する。[0009] Next, as shown in FIG.
A source electrode 34 and a drain electrode 35 are formed on the
Is formed to obtain a field effect transistor (FET).
A gate electrode 36 is formed on the side of the substrate 31 opposite to the gate insulating film 32 as necessary. The substrate 31 itself may be used as a gate electrode. The electrodes 34, 35, and 36 are formed by, for example, vapor deposition of Au or a solution method of a transparent electrode material such as ITO (indium, tin oxide film).
【００１０】ゲート絶縁膜３２の厚さは、ゲート絶縁膜
３２とチャネル層３３との境界に複合酸化膜が生成され
る点から、１００ｎｍ程度以上が好ましいが、チャネル
制御が確実に行われる点から５００ｎｍ以下がよい。チ
ャネルはチャネル層３３のゲート絶縁膜３２と接して形
成され、ソース電極３４とドレイン電極３５の間にこの
チャネルを通って電流が流れるには、電流はチャネル層
３３の厚さ方向に流れて、電極からチャネルへまたチャ
ネルから電極へ電流が流れることになる。この点からチ
ャネル層３３の厚さを１００ｎｍ程度以上にすると、電
子空乏層ができて電流が流れ難くなる。また１０ｎｍ程
度以下にするとチャネルとしての動作が良好に行わなく
なるおそれがある。これらの点からチャネル層３３の厚
さは１０〜１００ｎｍ程度がよい。The thickness of the gate insulating film 32 is preferably about 100 nm or more from the viewpoint that a composite oxide film is formed at the boundary between the gate insulating film 32 and the channel layer 33, but from the viewpoint that channel control is reliably performed. The thickness is preferably 500 nm or less. The channel is formed in contact with the gate insulating film 32 of the channel layer 33, and in order for a current to flow through the channel between the source electrode 34 and the drain electrode 35, the current flows in the thickness direction of the channel layer 33, Current will flow from the electrode to the channel and from the channel to the electrode. From this point, if the thickness of the channel layer 33 is set to about 100 nm or more, an electron depletion layer is formed and it becomes difficult for current to flow. On the other hand, if the thickness is less than about 10 nm, the operation as a channel may not be performed well. From these points, the thickness of the channel layer 33 is preferably about 10 to 100 nm.
【００１１】チャネル層３３の形成時における加熱処理
の温度を６００℃以下にすると、ゲート絶縁膜３２とチ
ャネル層３３との境界にＺｎＯとＳｉＯ2 の複合酸化物
膜Ｚｎ2 ＳｉＯ4 が十分生成されないため、ゲート絶縁
膜３２とチャネル層３３との密着性が悪くまたゲート絶
縁膜３２を通るゲート電流が増加し、つまり絶縁性が悪
く、良好なトランジスタ特性は得難くなる。従って、加
熱処理温度は６００℃以上とする。一方加熱処理温度を
９００℃以上にすると、複合酸化物膜Ｚｎ2 ＳｉＯ4 の
厚さが厚くなり、ＺｎＯ（チャネル層３３）の厚さが薄
くなり過ぎ、ソース電極３４とドレイン電極３５間に電
流が流れ難くなり、トランジスタ特性が得られなくな
る。この点より酸化処理温度は９００℃以下とする。If the temperature of the heat treatment at the time of forming the channel layer 33 is set to 600 ° C. or less, the composite oxide film of ZnO and SiO 2 Zn 2 SiO 4 is not sufficiently generated at the boundary between the gate insulating film 32 and the channel layer 33. Therefore, the adhesion between the gate insulating film 32 and the channel layer 33 is poor, and the gate current passing through the gate insulating film 32 is increased, that is, the insulating property is poor, and it is difficult to obtain good transistor characteristics. Therefore, the heat treatment temperature is set to 600 ° C. or higher. On the other hand, when the heat treatment temperature is set to 900 ° C. or higher, the thickness of the composite oxide film Zn 2 SiO 4 becomes too large, the thickness of the ZnO (channel layer 33) becomes too thin, and the current between the source electrode 34 and the drain electrode 35 becomes large. Flows hardly, and transistor characteristics cannot be obtained. From this point, the oxidation temperature is set to 900 ° C. or less.
【００１２】前記Ｚｎ（ＯＡｃ）2 ・４Ｈ2 Ｏを用いて
作った、０．４ｍｏｌ／ｌのディップ溶液に、２回ディ
ップコーティングし、６００℃、７００℃、８００℃及
び９００℃でそれぞれ加熱処理を各６０分行ってＦＥＴ
を作製した。ここで６００℃で加熱処理とは、１回ディ
ップコーティングを行い乾燥後６００℃で３０分間加熱
処理を行い、再び１回ディップコーティングを行い乾燥
後６００℃で３０分間加熱処理を行うことである。７０
０℃、８００℃及び９００℃での各加熱処理も同様にし
て各３０分間の加熱処理を２回行った。このようにして
作製したＦＥＴのＸ線回折パターンを図２に示す。加熱
処理の温度が低い６００℃ではＺｎ2 ＳｉＯ4 に基づく
ピークが確認できないが、ＺｎＯに基づくピークは確認
される。加熱処理温度が高くなるに従ってＺｎ2 ＳｉＯ
4 に基づくピークが確認できるようになり、逆にＺｎＯ
に基づくピークが小さくなり、９００℃ではＺｎ2 Ｓｉ
Ｏ 4 に基づくピークが可成り大きく現われ、逆にＺｎＯ
に基づくピークが可成り小さくなり、（１００）ＺｎＯ
に基づくピークはほぼなくなっている。The Zn (OAc)Two・ 4HTwoWith O
Dip the prepared 0.4mol / l dip solution twice.
600 ° C, 700 ° C, 800 ° C
And heat treatment at 900 ° C for 60 minutes each for FET
Was prepared. Here, the heat treatment at 600 ° C.
After coating and drying, heat at 600 ° C for 30 minutes
Processing, dip coating once again and drying
Thereafter, heat treatment is performed at 600 ° C. for 30 minutes. 70
The same applies to each heat treatment at 0 ° C, 800 ° C and 900 ° C.
The heat treatment was performed twice for 30 minutes each. Like this
FIG. 2 shows an X-ray diffraction pattern of the manufactured FET. heating
At a low processing temperature of 600 ° C., ZnTwoSiOFourbased on
No peak can be confirmed, but a peak based on ZnO is confirmed
Is done. As the heat treatment temperature increases, ZnTwoSiO
FourBased on ZnO, and conversely, ZnO
At 900 ° C., the peak based onTwoSi
O FourPeaks based on ZnO appear considerably large, and conversely ZnO
Is significantly reduced, and the (100) ZnO
Is almost eliminated.
【００１３】これら実験結果より、加熱処理を、ＺｎＯ
を析出させるが、Ｚｎ2 ＳｉＯ4 の生成を生じない低い
温度、つまり６００℃による加熱を行ってＺｎＯを析出
させ、結晶化させた後、９００℃で加熱処理して、結晶
化したＺｎＯをＳｉＯ2 （ゲート絶縁膜）と反応させて
Ｚｎ2 ＳｉＯ4 を薄く生成した。両加熱処理の合計時間
を６０分とした。この場合のサンプルのＸ線回折パター
ンは、Ｚｎ2 ＳｉＯ4に基づくピークの温度が、９００
℃のみで加熱処理した場合のそれよりも小さくなった。
更に透過形電子顕微鏡により断面を観察した所、ＺｎＯ
とＺｎ2 ＳｉＯ 4 との明白な界面が観察でき、Ｓｉ
Ｏ2 ，Ｚｎ2 ＳｉＯ4 及びＺｎＯの各膜厚はそれぞれ１
１５．４０及び４５ｎｍであった。Ｚｎ2 ＳｉＯ4 とＳ
ｉＯ2 との界面は非常に密着性が良いものとなっている
ことも確認された。From these experimental results, the heat treatment was performed using ZnO
Is precipitated, but ZnTwoSiOFourLow does not produce
Precipitation of ZnO by heating at a temperature of 600 ° C
After crystallization, heat treatment at 900 ° C.
Converted ZnO into SiOTwo(Gate insulating film)
ZnTwoSiOFourWas produced thinly. Total time of both heat treatments
For 60 minutes. X-ray diffraction pattern of the sample in this case
Is ZnTwoSiOFourThe peak temperature based on
It became smaller than that when heat treatment was performed only at ° C.
Further, when the cross section was observed with a transmission electron microscope, it was found that ZnO
And ZnTwoSiO FourAnd a clear interface with
OTwo, ZnTwoSiOFourAnd each film thickness of ZnO is 1
15.40 and 45 nm. ZnTwoSiOFourAnd S
iOTwoInterface has very good adhesion
It was also confirmed.
【００１４】以上のことから加熱処理は酸化物半導体結
晶が析出するが、その酸化物半導体結晶とゲート絶縁膜
と反応しない温度で加熱し、酸化物半導体を析出結晶化
させた後、これよりも高い温度で加熱して析出結晶化し
た半導体とゲート絶縁膜とを反応させる手法が好ましい
ことが理解される。２回ディップコーティングで各６０
０℃１０分の加熱処理と、９００℃１５分の加熱処理と
の合計３５分の加熱処理を行って作製したＺｎＯ−ＦＥ
Ｔのドレイン電流とゲート電流のゲート電圧に対する特
性を測定した。その結果を図３に実線と破線でそれぞれ
示す。この図から、ゲート電極への漏れ（ゲート電流）
は少なく、トランジスタ特性が得られていることが理解
される。From the above, the oxide semiconductor crystal is deposited by the heat treatment, but the oxide semiconductor crystal is heated at a temperature at which the oxide semiconductor crystal does not react with the gate insulating film to precipitate and crystallize the oxide semiconductor. It is understood that a method of reacting the semiconductor deposited and crystallized by heating at a high temperature with the gate insulating film is preferable. Dip coating twice for 60 each
ZnO-FE manufactured by performing a total of 35 minutes of heat treatment of 0 ° C. for 10 minutes and 900 ° C. for 15 minutes
The characteristics of the drain current and the gate current of T with respect to the gate voltage were measured. The result is shown by a solid line and a broken line in FIG. From this figure, leakage to the gate electrode (gate current)
, It is understood that transistor characteristics are obtained.
【００１５】上述において基板３１としては石英ガラ
ス、Ａｌ2 Ｏ3 など他の材料でもよい。またゲート絶縁
膜３２としてはＳｉＮ4 、ＳｉＯＮなどを用いてもよ
い。更にチャネル層３３としては、ＺｎＯに限らず、Ｔ
ｉＯ2 、ＢａＯ、ＴｉＢａＯなどを用いてもよく、また
ｎ形金属酸化物半導体のみならず、ＮｉＯ、ＣｕＯ2 、
Ｃｏ2 Ｏ3 などのｐ形金属酸化物半導体を用いてもよ
い。なお図１Ｄに示すように基板３１を切削又は化学的
エッチングにより、ゲート絶縁膜３２と反対側を削り、
基板３１の厚さを例えば０．０５ｍｍ以下、つまり可視
光が透過する程度以下にし、場合によっては全て除去
し、ゲート絶縁膜３２にＩＴＯなどの透明電極（ゲート
電極）を付けて液晶駆動トランジスタとして使用できる
ようにすることもできる。つまり透明なＦＥＴとするこ
ともできる。また図４に示すように、図１Ｃに対し、ソ
ース電極３４，ドレイン電極３５の形成面上に、これら
の周縁部と一部重なるように酸化シリコンや強誘電体チ
タン酸バリウムなどの絶縁膜３７を形成してチャネル層
表面を流れる洩れ電流を減らすように少なくともチャネ
ル層膜上に絶縁膜を溶液法で形成することが好ましい。In the above description, the substrate 31 may be made of another material such as quartz glass or Al 2 O 3 . Further, as the gate insulating film 32, SiN 4 , SiON, or the like may be used. Further, the channel layer 33 is not limited to ZnO,
iO 2 , BaO, TiBaO, etc. may be used. Not only n-type metal oxide semiconductors, but also NiO, CuO 2 ,
A p-type metal oxide semiconductor such as Co 2 O 3 may be used. In addition, as shown in FIG. 1D, the opposite side to the gate insulating film 32 is cut by cutting or chemically etching the substrate 31,
The thickness of the substrate 31 is set to, for example, 0.05 mm or less, that is, to the extent that visible light is transmitted therethrough, and in some cases, all of the thickness is removed. It can also be used. That is, a transparent FET can be used. Further, as shown in FIG. 4, the insulating film 37 such as silicon oxide or ferroelectric barium titanate is formed on the surface where the source electrode 34 and the drain electrode 35 are formed so as to partially overlap with the peripheral portions thereof. It is preferable to form an insulating film on at least the channel layer film by a solution method so as to reduce leakage current flowing on the channel layer surface.
【００１６】[0016]
【発明の効果】以上述べたようにこの発明によれば、チ
ャネル層を溶液法により形成することにより、金属酸化
物半導体をチャネル層としたＦＥＴを作製することがで
き、排ガス処理など大きな設備を必要とせず、比較的簡
単な設備で製造することができる。As described above, according to the present invention, an FET using a metal oxide semiconductor as a channel layer can be manufactured by forming a channel layer by a solution method. It can be manufactured with relatively simple equipment without the need.
【図面の簡単な説明】[Brief description of the drawings]
【図１】この発明の実施例の製造工程を説明するための
断面図。FIG. 1 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.
【図２】各種加熱処理温度で作製したＺｎＯ−ＦＥＴの
Ｘ線回折パターンを示す図。FIG. 2 shows X-ray diffraction patterns of ZnO-FETs manufactured at various heat treatment temperatures.
【図３】この発明方法で作ったＺｎＯ−ＦＥＴのトラン
ジスタ特性を示す図。FIG. 3 is a diagram showing transistor characteristics of a ZnO-FET manufactured by the method of the present invention.
【図４】この発明方法で作られたトランジスタの例を示
す断面図。FIG. 4 is a cross-sectional view showing an example of a transistor manufactured by the method of the present invention.
【図５】従来技術で考えられる接合形金属酸化物半導体
トランジスタを示す断面図。FIG. 5 is a cross-sectional view showing a junction type metal oxide semiconductor transistor considered in the prior art.
【図６】従来技術で考えられる金属酸化物半導体ＦＥＴ
を示す断面図。FIG. 6 shows a metal oxide semiconductor FET considered in the prior art.
FIG.
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F110 DD01 DD03 DD05 DD13 FF03 FF04 GG01 GG04 GG25 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F110 DD01 DD03 DD05 DD13 FF03 FF04 GG01 GG04 GG25
Claims (2)
膜を溶液法で作ってチャネル層を形成し、 そのチャネル層上にソース電極及びドレイン電極を形成
することを特徴とする金属酸化物トランジスタの製造方
法。1. A gate insulating film is formed on a substrate, an n-type or p-type metal oxide semiconductor thin film is formed on the gate insulating film by a solution method to form a channel layer, and a source electrode is formed on the channel layer. And forming a drain electrode.
記金属酸化物層を形成し、その後、上記温度より高い温
度で上記金属酸化物を酸化させて上記金属酸化物半導体
薄膜を得ることを特徴とする請求項１記載の金属酸化物
トランジスタの製造方法。2. The formation of a channel layer by the solution method includes forming the metal oxide layer at a relatively low temperature within a range where the metal oxide can be deposited, and then forming the metal oxide layer at a temperature higher than the temperature. 2. The method for manufacturing a metal oxide transistor according to claim 1, wherein the metal oxide semiconductor thin film is obtained by oxidizing the thin film.
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|---|---|---|---|
| JP2000057440A JP2001244464A (en) | 2000-03-02 | 2000-03-02 | Method of manufacturing metal oxide transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000057440A JP2001244464A (en) | 2000-03-02 | 2000-03-02 | Method of manufacturing metal oxide transistor |
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| Publication Number | Publication Date |
|---|---|
| JP2001244464A true JP2001244464A (en) | 2001-09-07 |
Family
ID=18578229
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|---|---|---|---|
| JP2000057440A Pending JP2001244464A (en) | 2000-03-02 | 2000-03-02 | Method of manufacturing metal oxide transistor |
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| Country | Link |
|---|---|
| JP (1) | JP2001244464A (en) |
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| JP2022044610A (en) * | 2009-10-05 | 2022-03-17 | 株式会社半導体エネルギー研究所 | Display device |
| JP7199501B2 (en) | 2009-10-05 | 2023-01-05 | 株式会社半導体エネルギー研究所 | Display device |
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| JP2013197539A (en) * | 2012-03-22 | 2013-09-30 | National Institute Of Advanced Industrial & Technology | Method of manufacturing oxide semiconductor film, and oxide semiconductor film |
| JP2014007398A (en) * | 2012-06-01 | 2014-01-16 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacturing method thereof |
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