TWI451501B - Methods for manufacturing a metal oxide semiconductor transistor - Google Patents

Description

Method for manufacturing metal oxide semiconductor transistor

The present invention relates to a method of fabricating a metal oxide semiconductor transistor.

A metal oxide semiconductor transistor (Metal Oxide Semiconductor Transistor) is a transistor using a metal oxide as a semiconductor layer. Compared with amorphous germanium thin film transistors, metal oxide semiconductor transistors have higher carrier mobility, and thus metal oxide semiconductor transistors have better electrical performance. In addition, the manufacturing method of the metal oxide semiconductor transistor is also simpler than the low temperature polycrystalline silicon film transistor, so the metal oxide semiconductor transistor also has high production efficiency.

In the method of manufacturing a metal oxide semiconductor, the electrical performance of a transistor made of an unannealed metal oxide layer is not stable. Fig. 1 is a graph showing the relationship between the gate voltage and the drain current of the above-mentioned transistor for six consecutive measurements under the condition that the drain voltage is 20V. As shown in Fig. 1, the relationship between the gate voltage and the drain current of each measurement is different, and there is a clear phenomenon of threshold voltage shift. The difference in threshold voltage is as high as 9.36V. In order to improve the above problems, the industry uses an annealing process with temperatures up to 350 ° C to improve the stability of the transistor. However, the annealing process at a high temperature tends to cause a thermal stress effect, resulting in deformation of the metal oxide semiconductor transistor.

Therefore, there is a great need for an improved manufacturing method that can reduce the temperature of the annealing process and stabilize the metal oxide semiconductor transistor. The electrical properties are fixed.

Accordingly, the present invention provides a method of fabricating a metal oxide semiconductor transistor capable of producing an electrically stable metal oxide semiconductor transistor at a temperature lower than 350 °C. .

According to an embodiment of the present invention, a method of manufacturing the above metal oxide semiconductor transistor includes the following steps. A gate is formed on a substrate. A gate insulating layer is formed to cover the gate. A patterned metal oxide semiconductor layer is formed on the gate insulating layer, and the patterned metal oxide semiconductor layer has a channel region. A source and a drain are formed on the patterned metal oxide semiconductor layer, and a gap between the source and the drain exposes the channel region. Forming a mobility enhancement layer on the channel region causes the mobility enhancement layer to oxidize with oxygen in the metal oxide semiconductor layer, and the mobility enhancement layer does not contact the source and the drain. The metal oxide semiconductor layer and the mobility enhancing layer are subjected to an annealing process in an environment having a temperature of from about 200 ° C to about 350 ° C.

According to another embodiment of the present invention, a method of manufacturing a metal oxide semiconductor transistor includes the following steps. A gate is formed on a substrate. A gate insulating layer is formed to cover the gate. A patterned metal oxide semiconductor layer is formed on the gate insulating layer, and the patterned metal oxide semiconductor layer has a channel region. A source and a drain are formed on the patterned metal oxide semiconductor layer, and a gap between the source and the drain is exposed to the channel region. The channel region is surface treated with a mobility enhancing medium to cause an oxidation reaction between the mobility enhancing medium and the metal oxide semiconductor layer. Surface treated metal oxide semiconducting in an environment having a temperature of from about 200 ° C to about 350 ° C The body layer is subjected to an annealing process.

The description of the embodiments of the present invention is intended to be illustrative and not restrictive. The embodiments disclosed herein may be combined or substituted with each other in an advantageous manner, and other embodiments may be added to an embodiment without further description or description.

In the following description, numerous specific details are set forth However, embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are only schematically shown in the drawings in order to simplify the drawings.

Fig. 2 is a flow chart showing a method 100 of manufacturing a metal oxide semiconductor transistor according to an embodiment of the present invention. 3-7 are schematic cross-sectional views of various process stages of the manufacturing method 100.

In step 102, a gate 220 is formed on the substrate 210 as shown in FIG. The substrate 210 may be, for example, a glass substrate or a germanium substrate. In one embodiment, the gate 220 is formed using a DC sputtering process. The material of the gate 220 may be, for example, molybdenum molybdenum, a molybdenum alloy or an aluminum alloy. In another embodiment, heavily doped p-type Si can be used as the material for the gate 220, which is well known in the art.

In step 104, a gate insulating layer 230 is formed to cover the gate 220 as shown in FIG. In one embodiment, the gate insulating layer 230 is formed using a horizontal furnace for chemical vapor deposition or a plasma-assisted chemical vapor deposition (PECVD). The material of the gate insulating layer 230 may be, for example, tantalum nitride (SiN _x ) or tantalum oxide (SiO _x ).

In step 106, a patterned metal oxide semiconductor layer 240 is formed over the gate insulating layer 230, and the patterned metal oxide semiconductor layer 240 has a channel region 242, as shown in FIG. In one embodiment, the method of forming the metal oxide semiconductor layer 240 is a radio frequency magnetron sputtering method or a direct current sputtering method. The material of the metal oxide semiconductor layer 240 may be, for example, amorphous indium gallium zinc oxide (a-IGZO), indium zinc oxide (IZO), amorphous indium zinc tin oxide (a-IZTO), or the like.

In step 108, a source 250a and a drain 250b are formed on the metal oxide semiconductor layer 240 as shown in FIG. There is a gap 252 between the source 250a and the drain 250b that exposes the channel 242. In one embodiment, the method of forming source 250a and drain 250b is a thermal evaporation or DC sputtering process. The material forming the source 250a and the drain 250b may be, for example, molybdenum molybdenum, a molybdenum alloy, or an aluminum alloy.

In one embodiment, after the step 108 is completed, a step of heat treatment may be performed on the metal oxide semiconductor layer 240 before the step 110 is performed. For example, the structure in which the source electrode 250a, the drain electrode 250b, and the metal oxide semiconductor layer 240 are formed may be placed in an environment having a temperature of about 200 ° C to about 350 ° C, and the metal oxide semiconductor layer 240 may be heat-treated to A metal oxide semiconductor layer 240 having a relatively stable nature is obtained, which will be described in more detail below.

In step 110, a mobility enhancement layer 260 is formed over channel region 242, as shown in FIG. 7A. Mobility enhancement layer 260 is used to remove metal oxygen The oxygen atoms in the semiconductor layer 240 are not bonded or weakly bonded to improve the stability of the metal oxide semiconductor layer 240. The mobility enhancement layer 260 contains a chemical substance such as an inorganic substance, an ionic compound or a covalent compound which can be bonded to oxygen. The mobility enhancement layer 260 contacts the metal oxide semiconductor layer 240 to cause the mobility enhancement layer 260 to oxidize with oxygen in the metal oxide semiconductor layer 240, thereby removing unbonded or weak bonds in the metal oxide semiconductor layer 240. Oxygen atom. When the metal oxide semiconductor layer 240 is deposited, there is an unbonded or weakly bonded oxygen atom in the metal oxide semiconductor layer 240. The inventors of the present invention have found that these unbonded or weakly bonded oxygen atoms are the main cause of the instability of the electrical properties of the metal oxide semiconductor layer 240. Therefore, the stability of the metal oxide semiconductor transistor is improved by removing these unbonded or weakly bonded oxygen atoms.

The material of the mobility enhancement layer 260 may be, for example, calcium, lithium, potassium, sodium, magnesium, barium, molybdenum, silver, strontium, titanium, iron, gallium, aluminum, lanthanum, cerium or the above oxides which are not in a saturated oxidation state. The "oxide which is not in a saturated oxidation state" may be, for example, AlO, which may be further oxidized to Al ₂ O ₃ . Other examples of such oxides that are not in a saturated oxidation state are calcium oxide, lithium oxide, sodium oxide, magnesium oxide, cerium oxide, molybdenum oxide, and silver oxide. In one embodiment, the mobility enhancing layer 260 can be formed using a thermal evaporation or radio frequency magnetron sputtering process.

The mobility enhancement layer 260 does not contact the source 250a and the drain 250b. The inventors of the present invention have found that even if a mobility enhancing layer 260 is formed using a non-conductive material such as calcium, if the mobility enhancing layer 260 is in contact with the source 250a and the drain 250b, the finally formed metal oxide semiconductor transistor Leakage can occur, which is not conducive to the on/off function of the transistor. therefore, One feature of the present invention is that the mobility enhancing layer 260 does not contact the source 250a and the drain 250b, but enables the metal oxide semiconductor transistor to have better electrical performance.

After performing step 110, a protective layer 270 may be formed to cover the metal oxide semiconductor layer 240, the source 250a, the drain 250b, and the mobility enhancing layer 260, as shown in FIG. 7B. The protective layer 270 serves to protect the underlying structure from the degradation of these structures by oxygen or moisture in the air.

In step 112, the metal oxide semiconductor layer 240 and the mobility enhancement layer 260 are annealed. The annealing process substantially heats the metal oxide semiconductor layer 240 and the mobility enhancing layer 260 to accelerate the oxidation reaction of the mobility enhancing layer 260 to bring the metal oxide semiconductor layer 240 to a stable state. On the other hand, since the mobility enhancement layer 260 has been formed on the metal oxide semiconductor layer 240 to remove the unbonded or weakly bonded oxygen atoms in the metal oxide semiconductor layer 240, the annealing process can be less than 350. When the temperature is °C, the metal oxide semiconductor transistor can be stabilized. In one embodiment, the structure formed in step 110 is placed in an environment of from about 200 ° C to about 350 ° C, such as from about 200 ° C to about 300 ° C, more specifically from about 200 ° C to about 250 ° C. The manner of performing the annealing process is not particularly limited, and for example, a high temperature furnace, a pulsed laser or an ultraviolet lamp may be used to heat the metal oxide semiconductor layer 240 and the mobility enhancement layer 260.

In another embodiment, after step 108, before performing step 110, a patterned protective layer 360 may be formed to cover the source 250a and the drain 250b, as shown in FIG. 8A. The patterned protective layer 360 has an opening 362 that exposes a portion of the channel region 242. Next, in step 110, a mobility enhancement layer 370 is formed on the exposed channel region 242, as shown in FIG. 8B. The mobility enhancement layer 370 does not contact the source 250a and the drain 250b. The specific embodiments and features of the patterned protective layer 360 and the mobility enhancing layer 370 of the present embodiment can be the same as those of the above-described embodiments.

Fig. 9 is a flow chart showing a method 400 of manufacturing a metal oxide semiconductor transistor according to another embodiment of the present invention. The specific implementations and features of step 402, step 404, step 406, and step 408 in method 400 may be the same as step 102, step 104, step 106, and step 108 in the foregoing method 100, respectively.

In step 410, mobility enhancing medium 510 is provided to channel region 242 to surface treat channel region 242 of metal oxide semiconductor layer 240, as shown in FIG. 10A. The mobility enhancing medium 510 generates an oxidation reaction with oxygen in the metal oxide semiconductor layer 240, and removes oxygen atoms in the metal oxide semiconductor layer 240. After the surface treatment with the mobility enhancing medium 510, a solid film layer structure is not formed on the metal oxide semiconductor layer 240. In one embodiment, the mobility enhancing medium 510 is a liquid or gas that can bond with oxygen. In one example, the mobility enhancing medium 510 is an organic material that can bond with oxygen, such as 2-methylpentane, 2,2-dimethylbutane, tertiary butanol, or benzene. In another example, the mobility enhancing layer media 510 can be a gas such as carbon monoxide or hydrogen.

In step 412, the surface-treated metal oxide semiconductor layer 240 is subjected to an annealing process. The annealing process essentially heats the metal oxide semiconductor layer 240. For specific embodiments of heating, reference may be made to step 112 above.

After step 412, a protective layer 520 may be formed to cover the source 250a, the drain 250b, and the metal oxide semiconductor layer 240, as shown in FIG. 10B. The specific embodiment of the protective layer 520 can be the same as the above embodiment. In an embodiment, the protective layer 520 may be formed after step 410 and before step 412.

11 is a graph showing a relationship between a gate voltage and a drain current of a metal oxide semiconductor transistor according to an embodiment of the present invention. Figure 11 shows the results of six consecutive measurements, with a drain voltage of 20V. As shown in the figure, the results of six consecutive measurements are very close, and the difference in threshold voltage is only 0.9V. It indicates that the stability of the metal oxide semiconductor transistor is significantly improved.

FIG. 12 is a graph showing the relationship between the drain current and the drain voltage of the metal oxide semiconductor transistor at different gate voltages (0 V, 5 V, 10 V, and 15 V) according to an embodiment of the present invention. The forward path and reverse path curves of the drain voltage and the drain current are also shown in Fig. 12. As shown in Fig. 12, at different gate voltages, the forward and reverse paths of the drain current and the drain voltage almost overlap, indicating that the metal oxide semiconductor transistor exhibits a stable state.

In the prior art, it is generally necessary to manufacture an electrically stable metal oxide semiconductor transistor at a temperature higher than 350 °C. However, the annealing process at a high temperature tends to cause a thermal stress effect, resulting in deformation of the metal oxide semiconductor transistor. According to an embodiment of the present invention, an electrically stable metal oxide semiconductor transistor can be fabricated at a temperature lower than 350 °C. Therefore, the problem of deformation of the metal oxide semiconductor transistor in the prior art can be effectively improved. On the other hand, embodiments of the present invention can be carried out at lower process temperatures, which has the advantage of saving energy.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and those skilled in the art, without departing from the spirit of the invention, In the scope of the invention, the scope of the invention is defined by the scope of the appended claims.

100, 400‧‧‧ method

102, 104, 106, 108, 110, 112, 402, 404, 406, 408, 410, 412 ‧ ‧ steps

210‧‧‧Substrate

220‧‧‧ gate

230‧‧‧ gate insulation

240‧‧‧Metal oxide semiconductor layer

242‧‧‧Channel area

250a‧‧‧ source

250b‧‧‧汲polar

252‧‧‧ gap

262‧‧‧ openings

270, 310‧‧‧ mobility enhancement layer

260, 320, 520‧‧ ‧ protective layer

510‧‧‧ mobility enhancement media

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A graph showing the relationship between gate voltage and drain current for six measurements.

Fig. 2 is a flow chart showing a method of manufacturing a metal oxide semiconductor transistor according to an embodiment of the present invention.

3-8B are schematic cross-sectional views showing respective process stages of the manufacturing method according to an embodiment of the present invention.

Figure 9 is a flow chart showing a method of manufacturing a metal oxide semiconductor transistor according to another embodiment of the present invention.

10A and 10B are schematic cross-sectional views showing a manufacturing process of a manufacturing method according to another embodiment of the present invention.

11 is a graph showing a relationship between a gate voltage and a drain current of a metal oxide semiconductor transistor according to an embodiment of the present invention.

FIG. 12 is a graph showing a relationship between a gate current and a drain voltage of a metal oxide semiconductor transistor at different gate voltages according to an embodiment of the present invention.

100‧‧‧ method

102, 104, 106, 108, 110, 112‧‧‧ steps

Claims (12)

A method for fabricating a metal oxide semiconductor transistor, comprising: forming a gate on a substrate; forming a gate insulating layer covering the gate; forming a patterned metal oxide semiconductor layer on the gate insulating layer, The patterned metal oxide semiconductor layer has a channel region; a source and a drain are formed on the patterned metal oxide semiconductor layer, wherein a gap between the source and the drain exposes the channel region; a mobility enhancement layer on the channel region, wherein the mobility enhancement layer does not contact the source and the drain, and the mobility enhancement layer comprises a metal or an oxide that does not reach a saturated oxidation state, wherein the metal system Selected from calcium (Ca), lithium (Li), potassium (K), sodium (Na), magnesium (Mg), cerium (Ce), molybdenum (Mo), silver (Ag), barium (Ba), titanium (Ti a group consisting of iron (Fe), gallium (Ga), and germanium (Ge), the oxide that is not saturated with oxidation is selected from the group consisting of unsaturated calcium oxide, unsaturated lithium oxide, unsaturated potassium oxide, and Saturated sodium oxide, unsaturated magnesium oxide, unsaturated cerium oxide, unsaturated molybdenum oxide, unsaturated silver oxide, unsaturated a group consisting of ruthenium oxide, unsaturated titanium oxide, unsaturated iron oxide, unsaturated gallium oxide, and unsaturated ruthenium oxide; and the metal oxide semiconductor layer in an environment having a temperature of about 200 ° C to about 350 ° C And the mobility enhancement layer performs an annealing process. The manufacturing method according to claim 1, wherein the step of forming the metal oxide semiconductor layer comprises using a radio frequency magnetron sputtering or a direct current sputtering. The manufacturing method according to claim 1, wherein the material of the metal oxide semiconductor layer is amorphous indium gallium zinc oxide (a-IGZO), indium zinc oxide (IZO) or amorphous indium zinc tin oxide (a). -IZTO). The manufacturing method of claim 1, wherein the step of forming the mobility enhancing layer comprises using a thermal evaporation process or a sputtering process. The manufacturing method according to claim 1, wherein the material of the mobility enhancing layer is an inorganic substance, an ionic compound or a covalent compound which can be bonded to oxygen. The manufacturing method of claim 1, after the step of forming the source and the drain, further comprising forming a patterned protective layer covering the source and the drain, wherein the patterned protective layer has an opening exposed One part of the channel area. The manufacturing method according to claim 1, after forming the mobility enhancement layer step, further comprising forming a protective layer covering the source, the drain, the metal oxide semiconductor layer, and the mobility enhancement layer. The manufacturing method according to claim 1, further comprising performing a heat treatment process on the metal oxide semiconductor layer before the formation of the mobility enhancement layer, and the temperature of the heat treatment is from about 200 ° C to about 350 ° C. The method of claim 1, wherein the annealing process has a temperature in the range of from about 200 ° C to about 250 ° C. A method for fabricating a metal oxide semiconductor transistor, comprising the steps of: forming a gate on a substrate; forming a gate insulating layer covering the gate; forming a patterned metal oxide semiconductor layer on the gate insulating layer The patterned metal oxide semiconductor layer has a channel region; a source and a drain are formed on the patterned metal oxide semiconductor layer, wherein a gap between the source and the drain exposes the channel region Relating the channel region with a mobility enhancing medium for surface treatment, wherein the mobility enhancing medium comprises at least one substance selected from the group consisting of 2-methylpentane, 2,2-dimethylbutane, and tertiary butyl a group consisting of alcohol, benzene, carbon monoxide, and hydrogen; and an annealing process of the metal oxide semiconductor layer subjected to the surface treatment in an environment having a temperature of about 200 ° C to about 350 ° C. The manufacturing method according to claim 10, after the surface treating step, further comprises forming a protective layer covering the source, the drain, and the metal oxide semiconductor layer. The manufacturing method of claim 10, wherein the temperature of the annealing process is The range is from about 200 ° C to about 250 ° C.