KR101023491B1 - Transistor structures and methods for making the same - Google Patents

Transistor structures and methods for making the same Download PDF

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KR101023491B1
KR101023491B1 KR1020047018750A KR20047018750A KR101023491B1 KR 101023491 B1 KR101023491 B1 KR 101023491B1 KR 1020047018750 A KR1020047018750 A KR 1020047018750A KR 20047018750 A KR20047018750 A KR 20047018750A KR 101023491 B1 KR101023491 B1 KR 101023491B1
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South Korea
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effect transistor
field effect
zno
delete delete
channel layer
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KR1020047018750A
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Korean (ko)
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KR20040106576A (en
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웨이저존에프.Ⅲ
호프만랜디엘.
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더 스테이트 오브 오레곤 액팅 바이 앤드 쓰루 더 스테이트 보드 오브 하이어 에쥬케이션 온 비해프 오브 오레곤 스테이트 유니버시티
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Priority to US60/382,696 priority
Priority to US10/307,162 priority patent/US7189992B2/en
Priority to US10/307,162 priority
Priority to US10/350,819 priority
Priority to US10/350,819 priority patent/US7339187B2/en
Application filed by 더 스테이트 오브 오레곤 액팅 바이 앤드 쓰루 더 스테이트 보드 오브 하이어 에쥬케이션 온 비해프 오브 오레곤 스테이트 유니버시티 filed Critical 더 스테이트 오브 오레곤 액팅 바이 앤드 쓰루 더 스테이트 보드 오브 하이어 에쥬케이션 온 비해프 오브 오레곤 스테이트 유니버시티
Priority to PCT/US2003/015527 priority patent/WO2004038757A2/en
Publication of KR20040106576A publication Critical patent/KR20040106576A/en
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Abstract

An increased field effect transistor is disclosed wherein at least a portion of the transistor structure is substantially transparent. One variation of the transistor according to the invention comprises a channel layer comprising a substantially insulating, substantially transparent material selected from ZnO, SnO 2, or In 2 O 3. A gate insulating layer comprising a substantially transparent material is disposed adjacent to the channel layer to define the channel layer / gate insulating layer interface. A second variant of the transistor comprises a channel layer comprising a substantially transparent material, selected from ZnO, SnO 2, or In 2 O 3, which is manufactured by annealing and is substantially insulating. Devices comprising such transistors and methods of manufacturing the transistors are also disclosed.
Transparent transistor, field effect transistor, optoelectronic device, display

Description

Transistor structures and methods for making the same

The present invention relates to a transistor structure, and more particularly to a transparent transistor.

The microelectronics industry and research community are working to fabricate electronic devices (eg diodes and transistors) that are transparent to the human visible electromagnetic spectrum. Circuits composed of such elements may be the only alternative to innovation or enhancement of consumer-, automotive-, and military-electronic systems.

For example, active-matrix liquid crystal displays (AMLCDs) are widely used in laptop computers and other information display products. The operation of an AMLCD is related to each picture or display element (pixel) that can be selected or addressed to turn that pixel on or off, and must have a corresponding thin-film transistor (TFT). do. Currently, AMLCD displays can be deposited on a glass substrate, but non-transparent (typically amorphous, polycrystalline, or continuous-grain silicon is used to fabricate TFTs on glass. Transistor material is applied. Thus, the display glass portion in which the electronic element for addressing is located cannot pass light through the display. Therefore, the use of transparent transistors for AMLCD addressing will improve display performance by allowing more light to pass through the display.

To aid in understanding, the following terms used herein are described in more detail below.

An "enhancement-mode transistor" refers to a transistor with little off-current compared to on-current under a gate voltage of 0 V between source and drain. it means. That is, the transistor element is in the "normally off" state. Depletion-mode transistors, on the other hand, are in a "normally on" state where a current above the negligible current flows between the source and drain under a gate voltage of 0V.

"Gate" generally refers to the insulated gate terminal of a three terminal FET when used in a transistor circuit arrangement.

“Substantially insulating” refers to insulators (eg, materials having a resistivity greater than about 10 10 Ω-cm) and semi-insulators (eg, resistivity in the range of about 10 3 Ω-cm to about 10 10 Ω-cm Material having).

"Substantially transparent" generally means a material or structure that does not absorb a substantial amount of light in the visible light region (or in some cases the infrared region) of the electromagnetic spectrum.

"Vertical" means substantially orthogonal to the surface of the substrate.

The above description of terms is provided only to assist the reader, and should not be construed as less than that understood by those of ordinary skill in the art to which the present invention pertains, and also to limit the scope of the claims. It should not be interpreted.

Disclosed herein are incremental, field effect transistors at least part of the transistor structure being substantially transparent. A device comprising the transistor and a method of manufacturing the transistor are also disclosed.

One variation of the transistor includes a channel layer selected from the group of ZnO, SnO 2 , or In 2 O 3 , which is composed of a substantially insulating and transparent material. A gate insulating layer composed of a substantially transparent material is positioned in contact with the channel to define the channel layer / gate insulating layer interface. The transistor also includes a source for injecting electrons from the channel layer to accumulate at the channel layer / gate insulating layer interface and a drain capable of extracting electrons from the channel layer.

The second variant of the transistor comprises a channel layer composed of a substantially transparent material selected from the group of substantially insulating ZnO, substantially insulating SnO 2, or substantially insulating In 2 O 3 . At this time, substantially insulating ZnO, substantially insulating SnO 2, or substantially insulating In 2 O 3 is produced by annealing.

The gate insulating layer is located adjacent to the channel layer and consists of a substantially transparent material. The transistor also includes a source, a drain, and a gate electrode.

The method of manufacturing the transistor includes providing a gate insulating layer, depositing ZnO, SnO 2 , or In 2 O 3 on at least a portion of the gate insulating layer, and the ZnO, SnO 2 , or In 2 O 3 Annealing at about 300 to about 100 ° C. for about 1 minute or about 2 hours in an oxidizing atmosphere.

The transistors may be included as switches connected to at least one display configuration in optoelectronic display devices. Another embodiment device is a substantially transparent DRAM (DRAM) cell consisting of a substantially transparent capacitor connected to the transistor. Another application of the transistor is a substantially transparent inverter to which the transistor is connected to a load device.

In general, the transistor structure includes a substrate, a gate electrode, a gate insulating layer, a channel layer, a source and a drain. The channel layer is adjacent to the gate insulating layer such that the surface of the channel layer contacts the surface of the gate insulating layer. The contact between the channel layer surface and the gate insulating layer surface is indicated here as the channel layer / gate insulating layer interface. In an exemplary structure, the channel layer insulation material is different from the gate insulation layer material, and the channel layer / gate insulation layer interface defines a discontinuous material boundary.

A feature of an embodiment of the transistor structure is that the channel layer / gate insulating layer interface may define a conductive channel for the flow of electrons from the source to the drain. That is, the transistor can be separated into "surface channel" or "interface channel" devices. The applied gate voltage causes electrons to accumulate in the channel layer / gate insulating layer interface region. In addition, the applied voltage promotes electron injection from the source to the channel layer / gate insulating layer interface and electron extraction therefrom by the drain.

Another feature of the transistor structure is that the embodiment selected from the structure or the combination of the channel layer and the gate insulation layer is characterized by at least 90%, more specifically about 95%, light in the visible region (or under some variable infrared region) of the electromagnetic wave. It shows light transmission. Each additional element of the structure (ie, substrate, gate electrode, source / drain terminals) may be selectively opaque or substantially transparent, depending on the user's requirements of the transistor. In one embodiment, the transistor structure as a whole (or individual configurations of the transistor) is at least 50%, more specifically at least about 70%, most specifically in the visible region (or under some variable infrared region) of the electromagnetic wave. Light transmittance of at least about 90%.

Another feature of the FETs disclosed herein is that they can be easily manufactured as thin film transistors (TFTs). For example, a relatively low fabrication temperature (eg, no more than 800 ° C.) is used, and ion implantation needs to be done to match the channel threshold voltage and to define the source and drain contacts under certain variables of the FET structure. none. Such TFTs are typically very useful in connection with optoelectronic devices, as described in more detail below.

The channel layer is typically formed of a substantially insulating, substantially transparent material. In the bulk region of the channel layer, small amounts of electrons are available, as negligible as they are. This is because the channel layer is substantially formed of an insulating material. In addition, the substantially insulating channel layer provides inherent electrical isolation (with patterned gate, source, and drain electrodes defining each device) for multiple devices sharing a continuous channel layer film. do. Such intrinsic device isolation means that the patterning of the channel layer film is unnecessary. This is because the conductivity in the channel layer / gate insulating layer only appears under the patterned gate electrode.

Exemplary materials for the channel layer include ZnO, SnO 2 , or In 2 O 3 . Insulating ZnO, SnO 2 , or In 2 O 3 may be formed by an annealing process, more particularly by rapid heat treatment (RTA). Such insulating ZnO, SnO 2 , or In 2 O 3 typically exhibit a bandgap of about 5 eV or less.

For example, a ZnO layer is deposited (e.g., sputtering, chemical vapor deposition, spin coating, physical vapor deposition, vapor phase epitaxy, molecular beam epitaxy) Taxi, etc.), and then in a substantially oxidizing atmosphere for about 1 minute to about 2 hours at a temperature of about 300 to about 1000 ° C., more specifically at a temperature of about 700 to about 800 ° C., more specifically about 1 minute to For about 1 hour, in some cases, an annealing step may be performed for about 1 to 5 minutes. Although not supported by any theory, it is believed that this treatment allows more oxygen to be added to the ZnO layer, thus reducing the oxygen vacancy concentration or the degree of oxygen deficiency. ought. Oxygen vacancy or oxygen deficiency in ZnO can cause ZnO to be n-type conductivity. High temperature (eg, at least about 700 ° C.) annealing, for example in an inert atmosphere such as argon (Ar), may also produce insulating ZnO. Although not supported by any theory, this high temperature annealing can improve the crystallinity of the ZnO, thereby improving the electron transport properties. Such insulating ZnO may or may not be doped. If doped, the resistivity of the ZnO is also improved by substitutional doping with acceptor dopants such as, for example, N, Cu, Li, Na, K, Rb, P, As and mixtures thereof. Can be.

Similarly, a SnO 2 layer is deposited (eg, by sputtering, chemical vapor deposition, spin coating, physical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, etc.), and then at about 300 to about 1000 ° C. in a substantially oxidizing atmosphere. Annealing at a temperature, more specifically at a temperature of about 700 to about 900 ° C. for about 1 minute to about 2 hours, more specifically about 1 minute to about 1 hour, and in some cases about 1 minute to 5 minutes Can be rough. Although not supported by any theory, it is believed that such treatment may allow more oxygen to be added to the SnO 2 layer, thereby reducing the oxygen vacancy concentration or the degree of oxygen deficiency. Oxygen vacancy or lack of oxygen in the SnO 2 may be SnO 2 is such that the n- type conductivity. Annealing at high temperatures (eg, above about 700 ° C.) in an inert atmosphere such as, for example, argon, can also produce insulating SnO 2 . Although not supported by any theory, this high temperature annealing can improve the crystallinity of the SnO 2 and thus improve the electron transport properties. The SnO by substitutional doping with acceptor dopants such as, for example, Al, In, Ga, Bi, B, La, Sc, Y, Lu, Er, Ho, N, P, As, and mixtures thereof The resistivity of 2 can also be improved.

Also similarly, an In 2 O 3 layer is deposited (eg, by sputtering, chemical vapor deposition, spin coating, physical vapor deposition, vapor phase epitaxy, molecular beam epitaxy, etc.), and then about 300 to substantially 300 in an oxidizing atmosphere. For about 1 minute to about 2 hours, more specifically for about 1 minute to about 1 hour at a temperature of about 1000 ° C., more specifically about 700 to about 900 ° C., in some cases about 1 minute to 5 hours The annealing step can be followed for minutes. Although not supported by any theory, it is believed that such treatment can allow more oxygen to be added to the In 2 O 3 layer, thereby reducing the oxygen vacancy concentration or the degree of oxygen deficiency. From In 2 O 3 oxygen vacancy or lack of oxygen it can be the In 2 O 3 so that the n- type conductivity. Annealing at high temperatures (eg, above about 700 ° C.) in an inert atmosphere, such as, for example, argon, can also produce insulating In 2 O 3 . Although not supported by any theory, such high temperature annealing can improve the crystallinity of the In 2 O 3 , thereby improving the electron transport properties. By resistive doping with acceptor dopants such as, for example, Be, Mg, Ca, Sr, Ba, N, P, As, Zn, Cd, and mixtures thereof, the resistivity of the In 2 O 3 is also improved. Can be.

According to a particular embodiment, the Zno, SnO 2 , or In 2 O 3 layer may be sputter deposited in an atmosphere comprising at least one sputter gas and at least one film modifying gas. The thin film-modifying gas may be any gas that can increase the specific resistance of the thin film by adding it into the thin film at an atom or subatomic level. For example, the thin film-modifying gas can be an oxidizing gas whose molecules, atoms, or ions are added into the thin film and occupy oxygen vacancies or deficiency in the thin film, as described above. Another thin film-modifying gas may be a dopant gas whose molecules, atoms, or ions are added into the thin film to increase the resistivity of the thin film. Exemplary sputter gases may include Ar, Ne and mixtures thereof. Exemplary oxidizing gases can include O 2 , N 2 O and mixtures thereof. Exemplary dopant gases may include N 2 , NH 3 and other gases including the aforementioned dopants. The concentration of the gases in the sputter atmosphere may vary depending on the characteristics required for the thin film. For example, the concentration of the oxidizing gas can range from about 0 to about 50 volume percent. The concentration of dopant gas may range from about 0 to about 50 volume percent. The concentration of sputter gas can range from about 0 to 100 volume percent. Sputtering conditions may also vary depending on the properties required for the thin film. For example, the temperature may range from about room temperature to 600 ° C., and the pressure may range from about 1 mTorr to about 50 mTorr. In certain embodiments, the undoped ZnO target may be sputter deposited in an atmosphere comprising 80 volume percent Ar, 10 volume percent N 2 , and 10 percent O 2 .

The thickness of the channel layer can vary, and in certain embodiments can range from about 10 to about 500 nm. The channel length may also vary, and in certain embodiments may range from about 1,000 to about 100,000 nm.

The gate insulating layer may be formed of any material that exhibits the insulating properties required for the gate insulator, especially the substantially transparent material. The gate insulating material typically exhibits a band gap of about 5 eV or more. Exemplary materials include substantially transparent materials such as aluminum-titanium oxide (Al 2 O 3 / TiO 2 ), Al 2 O 3 , MgO, SiO 2 , silicon nitride, and silicon oxynitirde. One distinct example of a substantially transparent material is an aluminum-titanium oxide film formed by atomic layer deposition. The thickness of the gate insulating layer is variable, and in certain embodiments may range from about 10 to about 300 nm. The gate insulating layer may be introduced into the structure by techniques such as chemical vapor deposition, sputtering, atomic layer deposition, or evaporation.

The source / drain terminals correspond to the terminals of the FET, and between them a challenge occurs under the influence of an electric field. Designers often designate specific source / drain terminals as "source" or "drain" based on the voltage applied to the terminal when the FET is operating in the circuit. The source and drain may be formed of a suitable conductive material, such as an n-type material. The source and drain materials may optionally be opaque materials or substantially transparent materials. Exemplary materials include indium-tin oxide (ITO), transparent n-type conductors such as Zno, SnO 2 , or In 2 O 3 , or Al, Cu, Au, Pt, W, Ni, Or opaque metals such as Ti. In particular, materials useful as the source and drain are materials capable of injecting and extracting electrons into the channel layer insulating material. Examples of such electron injection materials include indium-tin oxide films, LaB 6 , and ZnO: Al.

The source and drain can be introduced into the structure by methods such as chemical vapor deposition, sputtering, evaporation, diffusion or doping of channel layer materials through ion implantation. The source and drain terminals can be manufactured geometrically symmetrically or asymmetrically.

The gate electrode may be formed of a suitable conductive material. The gate electrode material may optionally be an opaque material or a substantially transparent material. Exemplary gate electrode materials include indium-tin oxide (ITO), transparent n-type conductors such as Zno, SnO 2 , or In 2 O 3 , or Al, Cu, Au, Pt, W, Ni, or Ti; The same opaque metals may be included. The thickness of the gate electrode may vary and may range from about 50 to about 1000 nm, depending on the particular embodiment. The gate electrode may be introduced into the structure by chemical vapor deposition, sputtering, evaporation or doping.

As used herein, a "substrate" refers to a physical material that is a basic workpiece that can be converted to the desired microelectronic configuration by various process operations. The substrate may also refer to a wafer. Wafers may be formed of a semiconductor, a non-semiconductor, or a combination of a semiconductor and a non-semiconductor material. The substrate may be formed of any suitable material. The substrate material may optionally be an opaque material or a substantially transparent material. Exemplary substrate materials include glass and silicon. The thickness of the substrate is variable, and in certain embodiments may range from about 100 μm to about 1 cm.

Electrical contact to the gate electrode, source, drain, and substrate may be provided in a number of ways. For example, metal lines, traces, wires, interconnects, conductors, signal paths, and signaling mediums provide the desired electrical connections. Can be used. The associated terms are generally interchangeable and are arranged in order from specific to general. Metal lines, generally aluminum (Al), copper (Cu), or alloys of Al and Cu, are conductors that provide signal paths for coupling or wiring of electrical circuits. Conductors other than metal may also be used.

Exemplary n-channel operation of the transistor includes applying a positive voltage to the gate electrode, grounding the source, and applying a positive voltage to the drain. For example, a voltage of about 5 to about 40 V may be applied to the gate electrode and the drain operation. The threshold voltage may range from about 1 to about 20 volts. Electrons flow from the source along the conductive channel created at the channel / gate insulating layer interface and through the drain out of the transistor. The effective mobility of the electrons at the interface varies depending on the specific structure, but may be, for example, in the range of about 0.05 to about 20 cm 2 V −1 s −1 . The transistor can be turned off by simply removing the positive voltage applied to the gate electrode. This is because the transistor is an enhancement-mode transistor.

The transistor structure disclosed herein can be used as chips, integrated circuits, monolithic devices, semiconductor devices, and microelectronic devices. One example of microelectronics is an optoelectronic device. Exemplary optoelectronic devices are active-matrix liquid-crystal displays (AMLCDs).

One aspect of the device is an optoelectronic display device comprising a configuration comprising electrodes and an electro-optical material positioned between the electrodes. A connection electrode of the transparent transistor can be connected to the display configuration. At this time, the switching configuration and the display configuration at least partially overlap. An optoelectronic display configuration is understood here as a display configuration, for example a liquid crystal display (LCD), whose optical properties change under the influence of an electrical quantity such as current or voltage. The transparent transistor described herein is fast enough to switch the display configuration at a high frequency enough to be used as a switching configuration in a liquid crystal display. The display arrangement acts as a capacitor that is charged and discharged by transparent transistors in electrical terms. The optoelectronic display elements may comprise many display configurations, each having its own transparent transistor, for example arranged in a matrix. The transparent transistors are described, for example, in Information Display 2/02, p. It can be arranged in the LCD device of the "Thin-Film-Transistor Device Design" by Kim described in 26 (2002).

One example of an AMLCD cell circuit is shown in FIG. The AMLCD cell circuit comprises a transistor 60 described herein and an LCD pixel 61 electrically connected thereto. Transistor 60 and LCD pixel 61 together form transistor / pixel cell 62. As arranged, transistor 60 is electrically connected to a row or control line 63 that receives an on / off input thereto. The source electrode of transistor 60 is electrically connected to a column or data line 64 that receives a signal controlling LCD pixel 61.

Other examples of microelectronic devices to which the transistor structure described herein may be applied include devices such as inverters, analog amplifiers, and single-transistor DRAMs.

For example, a transparent incremental transistor whose source is connected to one terminal of a transparent capacitor and the other terminal of the capacitor is grounded constitutes a transparent single-transistor DRAM cell. In such DRAM cells, information is stored as the charge of the capacitor. In this case, the incremental transistor serves as an access transistor for controlling the capacitor charge state. Typically in such DRAM cells, logic "0" corresponds to the case of little capacitor charge and thus a small capacitor voltage. On the other hand, logic "1" is obtained by charging the capacitor and thus raising the capacitor voltage until it is close to the power supply voltage.

All or part of the DRAM cell described herein is transparent. Manufacturing transparent capacitors and connecting them to transparent transistors to form DRAM cells can be performed in a variety of ways. Specifically, the transparent capacitor may be formed by sandwiching a transparent insulating layer using a material such as an indium-tin oxide film, ZnO, or SnO 2 .

One specific example of the DRAM cell circuit is shown in FIG. 12. The DRAM cell circuit includes the transistor 70 described herein, and a storage capacitor 71 electrically connected thereto. Transistor 70 and storage capacitor 71 together form transistor / capacitor cell 72. As arranged, transistor 70 is electrically connected to a storage capacitor 71 via a drain electrode. The gate electrode of transistor 70 is electrically connected to a row or write line 73 that receives an on / off input to transistor 70. The source electrode of transistor 70 is electrically connected to a column or data line 74 that receives a signal that controls what is stored on storage capacitor 71.

Embodiments will be described in more detail with reference to the following drawings.

1 is a cross-sectional view illustrating a transistor structure according to a first embodiment of the present invention.

2 is a cross-sectional view illustrating a transistor structure according to a second embodiment of the present invention.

3 is a cross-sectional view illustrating a transistor structure according to a third embodiment of the present invention.

FIG. 4 is a graph showing the drain-source current I DS versus the drain-source voltage as a function of the gate-source voltage V GS for the transistor structure shown in FIG. 1 (the gate-source voltage is +40 2 V increments from V (top curve) to +2 V).

FIG. 5 is a graph showing I DS characteristics for V GS under three different drain-source voltages for the transistor structure shown in FIG. 1.

FIG. 6 is a graph showing inverter transfer characteristics of the transistor structure shown in FIG. 1 using a transparent thin film resistive load (R = 70 MΩ) and a power supply voltage (V DD = 40 V).

FIG. 7 is a graph illustrating optical transmission characteristics through the source or drain portions of the transistor structure illustrated in FIG. 1.

8 is a cross-sectional view illustrating a transistor structure according to a fourth embodiment of the present invention.

9 is a cross-sectional view illustrating a transistor structure according to a fifth embodiment of the present invention.

10 is a cross-sectional view illustrating a transistor structure according to a sixth embodiment of the present invention.

11 is a schematic diagram showing an example of a cell circuit for an AMLCD including a transistor structure according to the present invention.

12 is a schematic diagram showing an example of a DRAM cell circuit including a transistor structure according to the present invention.

13 is a schematic diagram showing an example of a logic inverter including a transistor structure according to the present invention.

14 is a schematic diagram showing an example of an inverting amplifier circuit including a transistor structure according to the present invention.

Examples of specific transistor structures are shown in FIGS. 1-3 and 8-10. The specific examples described below are for illustrative purposes and should not be construed as limiting the scope of the claims. The same reference numerals in FIGS. 1-3 and 8-10 indicate the same configuration, unless otherwise indicated.

Referring to Figure 1, a TFT structure 1 fabricated on a composite substrate 1 inch by 1 inch thick is shown. The platform comprises a glass substrate 2, a 200 nm thick indium-tin oxide (ITO) gate electrode 3 coated on the substrate 2, and a 200 nm thick aluminum titanium oxide gate insulating layer 4.

ZnO channels and ITO source / drain electrode films are deposited by ion beam sputtering at 10 −4 Torr of Ar / O 2 (80% / 20%). During this deposition, the substrate is not heated. The ZnO channel layer 5 (100 nm thick), the ITO source electrode 6 (300 nm thick) and the ITO drain electrode 7 (300 nm thick) are defined using a shadow mask. The resulting structure defines the channel layer / gate insulating layer interface 8. Rapid 300 ° C. heat treatment (RTA) on Ar before ZnO and ITO deposition serves to remove adsorbed contaminants on exposed surfaces. As a result, the thin film quality (particularly the ITO film) is remarkably improved. After deposition of the ZnO layer, RTA (typically at a temperature of 600 to 800 ° C., in an O 2 or Ar atmosphere) is performed to increase the ZnO channel resistivity and to improve the electrical properties of the channel / gate insulating layer interface 8 do. Following deposition of the ITO source / drain electrodes, a 300 ° C. RTA treatment in an O 2 atmosphere is performed to improve the transparency of the ITO layer. In the transistor structure 1, the source / drain electrodes 6, 7 are disposed on the top surface (vertically) of the channel layer 5, and the gate electrode 3 and the channel layer 5 are each gate insulated. It is arranged on the opposite surface of layer 4. As a result, the structure 1 enables the high temperature treatment of the ZnO channel layer 5 before deposition of the ITO source / drain electrodes 6, 7. Specific electrical and physical features of the TFT structure 1 are described below and shown in FIGS. 4 to 7.

Referring to FIG. 4, n-channel incremental operation is obtained, as evidenced by the fact that a positive gate voltage above the threshold voltage (˜15 V) is needed to obtain significant drain-source current. This I DS -V DS graph shows the basic FET characteristics. What is important here is that the graph is flat at large drain voltages (i.e., "hard" saturation). The applied drain and gate voltage is rather large compared to conventional FETs. At this time, the gate and drain voltages can be reduced to a range expected in conventional FET operation (i.e., ~ 5-10V) by simply reducing the thickness of the gate insulator. In the TFT structure 1, the insulator thickness is ˜200 nm, as optimized for an electroluminescent display device. At this time, if the other insulator is changed back to a thickness of 20 nm, the gate and drain voltages will be reduced by about 10 times.

The I DS of the structure 1 is rather small here (ie, the I DS (max) is about 6 GPa in FIG. 4). Larger I DS would be desirable in most devices. The size of the I DS is determined by two factors. One is the effective mobility of the channel electron, μ eff (about 0.05-0.2 cm 2 V −1 s −1 for the TFT structure (1)). Process / device optimization can improve μ eff by about 2 to 100 times, thereby increasing the I DS .

5 shows I DS -V GS characteristics of the TFT structure 1 under three different drain voltages. This figure shows that when the transistor is used as a switch, there is a 10 5 -10 6 times difference between the "on" and "off" currents.

6 shows the transfer characteristics of the TFT structure 1 when used as an inverter. The ZnO transparent thin film resistor (R = 70 MΩ) is used as the inverter passive load when the power supply voltage V DD = 40 V. From this graph a logic swing of about 15V is apparent between 15 and 30V. This indicates that the transparent TFT described herein can be used as a transparent inverter. In this simplest implementation, a logic inverter consists of two components: a transistor connected to a load element. The load element may be a resistor applied in this example. Alternatively, depletion- or incremental-transistors may also be used with load elements that typically provide good performance. The basic feature of a logic inverter is that it performs a logic not operation. Here, a logic "0 (1)" input produces a logic "1 (0)" output. Since the inverter is the most basic block in achieving a transparent digital electronic device, the successful performance of the transparent logic inverter described herein is important. By reducing resistor thickness, reducing physical dimensions, and increasing the current drive capability (increased aspect ratio and effective mobility), optimizing the transparent thin film transistors provides the power supply required for inverter operation. The voltage can be significantly lowered.

One example of a logic inverter circuit is shown in FIG. The logic inverter circuit includes the transistor 80 described herein. The gate electrode of transistor 80 is electrically connected to an input voltage V in , the source electrode of transistor 80 is electrically connected to ground, and the drain electrode of transistor 80 is connected to load 81 and It is electrically connected to a power source V DD . The load 81 may be a transparent thin film resistor or a transparent thin film transistor. The voltage V out out of the circuit is controlled by V in turning the transistor 80 on or off.

Transparent transistors can also be used in the amplification device. For example, the inverter structure described herein can also operate as a simple analog inverting amplifier. If there is an appropriate DC bias for the input, a small input signal (in addition to the DC bias) can be amplified by the inverter transmission characteristic. In addition to such simple amplification arrangements, these transistors can be applied directly to any amplification arrangement with the limitation that the maximum operating frequency is relatively low due to the low mobility of these devices.

One specific example of the inverting amplification circuit is shown in FIG. 14. The inverting amplification circuit includes the transistor 90 described herein. The gate electrode of the transistor 90 is electrically connected to the voltage input signal V in and the DC bias V bias . The source electrode of transistor 90 is electrically connected to ground, and the drain electrode of transistor 90 is electrically connected to load 91 and power source V DD . The load 91 may be a transparent thin film resistor or a transparent thin film transistor.

7 shows the light transmittance of the TFT structure 1 through the source 6 or drain 7 (the light transmittance through the channel (not shown here) is higher than through the source or drain). In the visible region (450-700 nm) of electromagnetic waves, the average light transmittance is about 90% (about 95% through the channel). Visually, the transparent TFT structure is essentially invisible; Looking closely, some coloring of the glass substrate is evident.

Another transparent TFT structure 10 version is shown in FIG. 2. Here, the source electrode 11 (100 nm thick) and the drain electrode 12 (100 nm thick) connect the ends of the ZnO channel layer 13 (100 nm thick) to In (or other suitable n-type dopant). Formed by selective doping. This is accomplished by ion beam sputter deposition of a thin (about 5 nm) ITO layer using a source / drain shadow mask prior to depositing the ZnO channel film. A subsequent high temperature (˜600-800 ° C.) annealing step is performed to diffuse-dope the ZnO. As a result, n-type doped source / drain regions 11 and 12 are formed. Diffusion-doped RTA also serves as an oxidized RTA for ZnO. ITO contacts may be disposed on the source and drain regions to provide better electrical contact. The substrate 2, the gate electrode 3, the gate insulating layer 4 and the channel / gate insulating layer interface 8 are the same as shown in FIG.

Referring to Fig. 3, in the third modification of the TFT structure 2, the ITO source electrode 21 (300 nm thick) and the ITO drain electrode 22 (300 nm thick) are ZnO channel layers 23 (100). nm thickness) before deposition. The ZnO channel layer 23 is then deposited conformally on the ITO source / drain electrodes 21, 22. After deposition of ZnO, 700 ° C. Ar annealing is performed, followed by 300 ° C. oxygen annealing. The substrate 2, the gate electrode 3, the gate insulating layer 4 and the channel layer / gate insulating layer interface 8 are the same as shown in FIG.

A fourth variant of the TFT structure 30 is shown in FIG. The TFT structure 30 includes a glass substrate 2 on which a source electrode 35 and a drain electrode 36 are disposed thereon. The channel structure 37 is disposed between the source electrode 35 and the drain electrode 36 and includes a bulk portion 38 adjacent to the glass substrate 2. The channel structure 37 also combines with the bulk portion 38 and includes an interface portion 39 disposed between the gate insulating layer 34 and each of the source electrode 35 and the drain electrode 36. The interface part 39 may overlap one part or the entire part of the source electrode 35 and the drain electrode 36. The interface 39 and the gate insulating layer 34 form a channel layer / gate insulating layer 31 which defines a conductive channel for the flow of electrons from the source to the drain. The gate electrode 33 is disposed at the top (vertically) of the gate insulating layer 34. That is, the gate electrode 33 and the channel structure 37 are provided on the opposite surface of the gate insulating layer 34.

The TFT structure 30 may be manufactured by, for example, depositing and patterning a thin film defining the source electrode 35 and the drain electrode 36. For example, a 500 kV ITO source / drain electrode film may be sputter deposited on the glass substrate 2. Source and drain patterning may be performed by shadow masking or photolithography. The source / drain electrode film may be selectively annealed. Channel structure 37 may then be deposited and patterned on source electrode 35, drain electrode 36 and substrate 2. For example, a 500 ns ZnO film may be sputter deposited and then patterned by shadow masking or photolithography. The ZnO film may be selectively annealed. Subsequently, a gate insulating layer 34 may be deposited and patterned on the channel structure 37. For example, a 2000 micron Al 2 O 3 film can be sputter deposited and then patterned by shadow masking or photolithography. Vias may be formed through the gate insulating layer 34 to be electrically connected to the source electrode 35 and the drain electrode 36. The Al 2 O 3 film is optionally annealed. Gate electrode 33 is then deposited and patterned on gate insulating layer 34. For example, a 2000 microsecond ITO film can be sputter deposited and subsequently patterned by shadow masking or photolithography. The ITO film may be selectively annealed.

A fifth variant of the TFT structure 40 is shown in FIG. The TFT structure 40 includes a glass substrate 2 on which a channel layer 41 is disposed. The source electrode 43 and the drain electrode 42 are provided on the surface of the channel layer 41 opposite the glass substrate 2. The gate insulating layer 44 is disposed on the channel layer 41, the source electrode 43, and the drain electrode 42. The gate electrode 45 is disposed on the top (vertically) of the gate insulating layer 44. That is, the gate electrode 45 and the channel layer 41 are provided on the opposite side of the gate insulating layer 44. The resulting structure defines the channel layer / gate insulating layer interface 46.

TFT structure 40 may be fabricated by, for example, depositing and patterning a thin film defining channel layer 41. For example, a 500 ns ZnO film may be sputter deposited and then patterned by shadow masking or photolithography. The ZnO film may be selectively annealed. Source electrode 43 and drain electrode 42 may then be deposited and patterned. For example, a 500 kV ITO source / drain electrode film may be sputter deposited and then patterned by shadow masking or photolithography. The source / drain electrode film may be selectively annealed. Subsequently, a gate insulating layer 44 may be deposited and patterned on the channel layer 41, the source electrode 43, and the drain electrode 42. For example, a 2000 microseconds Al2O3 film may be sputter deposited and then patterned by shadow masking or photolithography. Vias may be formed through the gate insulating layer 44 to be electrically connected to the source electrode 43 and the drain electrode 42. The Al 2 O 3 film may be selectively annealed. Gate electrode 45 is then deposited and patterned on gate insulating layer 44. For example, a 2000 microsecond ITO film can be sputter deposited and subsequently patterned by shadow masking or photolithography. The ITO film may be selectively annealed.                 

A sixth variant of the TFT structure 50 is shown in FIG. The TFT structure 50 includes a glass substrate 2 on which a channel layer 51, a source electrode 52, and a drain electrode 53 are disposed. The gate insulating layer 54 is disposed on the channel layer 51, the source electrode 52, and the drain electrode 53. The gate electrode 55 is disposed on the top (vertically) of the gate insulating layer 54. That is, the gate electrode 55 and the channel layer 51 are provided on the opposite side of the gate insulating layer 54. The resulting structure defines the channel layer / gate insulating layer interface 56.

The TFT structure 50 can be manufactured, for example, by depositing and patterning a thin film defining the channel layer 51. For example, a 500 ns ZnO film may be sputter deposited and then patterned by shadow masking or photolithography. The ZnO film may be selectively annealed. The source electrode 52 and the drain electrode 53 may be formed by selectively doping the ends of the channel layer 51 with In, Al, Ga, or other suitable n-type dopant. Subsequently, a gate insulating layer 54 may be deposited and patterned on the channel layer 51, the source electrode 52, and the drain electrode 53. For example, a 2000 micron Al 2 O 3 film can be sputter deposited and then patterned by shadow masking or photolithography. Vias may be formed through the gate insulating layer 54 to be electrically connected to the source electrode 52 and the drain electrode 53. The Al 2 O 3 film may be selectively annealed. Gate electrode 55 is then deposited and patterned on gate insulating layer 54. For example, a 2000 microsecond ITO film can be sputter deposited and subsequently patterned by shadow masking or photolithography. The ITO film may be selectively annealed.

While the principles of the disclosed apparatus and methods have been illustrated and described with reference to a number of embodiments, these apparatus and methods may be modified in arrangement and detail structure without departing from such principles.

The transistor structure according to the invention can be used as chips, integrated circuits, monolithic devices, semiconductor devices, and microelectronic devices. One example of microelectronics is an optoelectronic device. Exemplary optoelectronic devices are active-matrix liquid crystal displays (AMLCDs). Other examples of microelectronic devices include devices such as inverters, analog amplifiers, and single-transistor DRAMs.

Claims (62)

  1. As a field effect transistor,
    A channel layer comprising an insulating transparent material selected from ZnO, SnO 2 , or In 2 O 3 ;
    A gate insulating layer comprising a transparent material and adjacent the channel layer;
    Source; And
    Including a drain,
    Electrons may accumulate at an interface between the channel layer and the gate insulating layer, and the electrons flow from the source to the drain through the channel layer.
    Wherein said field effect transistor is configured for enhancement-mode operation and exhibits at least 70% light transmission in the visible region of electromagnetic waves.
  2. The field effect transistor of claim 1, further comprising a gate electrode and a substrate, wherein the source, the drain, the gate electrode, and the substrate are each formed of a transparent material.
  3. The field effect transistor of claim 1, further comprising a gate electrode and a substrate, wherein at least one of the source, the drain, the gate electrode, and the substrate is formed of an opaque material.
  4. The field effect transistor of claim 1, wherein the gate insulating layer comprises Al 2 O 3 / TiO 2 .
  5. 3. The gate insulating layer of claim 2, wherein the gate insulating layer comprises Al 2 O 3 / TiO 2 or Al 2 O 3 , wherein the source, the drain, and the gate electrode each include an indium-tin oxide film, and the substrate A field effect transistor comprising glass.
  6. 2. The field effect transistor of claim 1, wherein said field effect transistor exhibits at least 90% light transmission in the visible region of electromagnetic waves.
  7. The field effect transistor of claim 1, wherein the channel layer is not ion implanted.
  8. The field effect transistor of claim 1, wherein the ZnO, SnO 2 , or In 2 O 3 has a reduced oxygen vacancy concentration.
  9. As a field effect transistor,
    A channel layer comprising a transparent material selected from insulative ZnO, insulative SnO 2 , or insulative In 2 O 3 ;
    A gate insulating layer adjacent the channel layer;
    Source;
    drain; And
    A gate electrode,
    Wherein said field effect transistor is configured for enhancement-mode operation and exhibits at least 70% light transmission in the visible region of electromagnetic waves.
  10. 10. The field effect transistor of claim 9, wherein the channel layer comprises insulating ZnO prepared by annealing the ZnO film at a temperature of 300 to 1000 ° C. in an oxidizing or inert atmosphere for 1 minute to 2 hours.
  11. 10. The field effect transistor of claim 9, wherein the channel layer comprises undoped ZnO.
  12. 11. The field effect transistor of claim 10, wherein the insulating ZnO produced by annealing has a lower oxygen vacancy concentration than the unannealed ZnO.
  13. (i) a channel layer comprising an insulating transparent material selected from ZnO, SnO 2 , or In 2 O 3 , (ii) a gate insulating layer adjacent to the channel layer, (iii) a source, (iv) a drain, and (v) Providing a field effect transistor comprising a gate electrode; And
    Applying a positive voltage to the gate electrode such that electrons flow at an interface between the channel layer and the gate insulating layer,
    The flow of currents when no positive voltage is applied to the gate electrode is smaller than the flow of currents when positive voltage is applied to the gate electrode,
    The field effect transistor is configured to perform enhancement-mode operation and exhibits at least 70% light transmittance in the visible region of the electromagnetic wave.
  14. The method of claim 13, wherein the electrons flowing at the interface between the channel layer and the gate insulating layer have an effective mobility of 0.05 cm 2 V −1 s −1 to 20 cm 2 V −1 s −1 . A method of operating a field effect transistor, characterized in that.
  15. The method of claim 13, wherein a voltage of 5 to 40 V is applied to the gate electrode and the drain.
  16. Depositing ZnO, SnO 2 , or In 2 O 3 on at least a portion of the surface of the gate insulating layer; And
    And annealing the ZnO, SnO 2, or In 2 O 3 for 1 minute to 2 hours at a temperature of 300 to 1000 ℃ in an oxidizing or inert atmosphere of the step to create a layer comprising ZnO, SnO 2, or In 2 O 3 Method for producing an increased field effect transistor comprising a.
  17. 17. The method of claim 16 wherein ZnO is deposited.
  18. 17. The method of claim 16, wherein the gate insulating layer comprises a transparent material.
  19. Depositing ZnO, SnO 2 , or In 2 O 3 on at least a portion of the surface of the gate insulating layer; And
    Heat treating the ZnO, SnO 2 , or In 2 O 3 ;
    The thermally treated ZnO, SnO 2 , or In 2 O 3 have an increased resistivity and lower oxygen vacancy concentration than the unheated ZnO, SnO 2 , or In 2 O 3 . Manufacturing method.
  20. 13. An optoelectronic display device comprising at least one display element coupled with a switch comprising the field effect transistor of any of claims 1-12.
  21. 13. A transparent DRAM cell comprising a transparent capacitor coupled to the field effect transistor of any of claims 1-12.
  22. 13. A transparent logic inverter comprising a load device coupled with the field effect transistor of any of claims 1-12.
  23. An amplifier comprising the field effect transistor of claim 1.
  24. A continuous channel layer film including an insulating material selected from ZnO, SnO 2 , or In 2 O 3 ; And
    A plurality of electronic elements sharing the continuous channel layer film,
    Each of the plurality of electronic elements includes a patterned gate insulating layer, a source and a drain so that the plurality of electronic elements are formed discretely along the continuous channel layer film,
    The gate insulating layer is adjacent to the continuous channel layer film,
    And the continuous channel layer exhibits at least 70% light transmission in the visible region of the electromagnetic wave.
  25. 18. The method of claim 17, further comprising introducing an acceptor dopant into the ZnO.
  26. The method of claim 16, wherein depositing ZnO, SnO 2 , or In 2 O 3 comprises: at least one sputter gas and at least one gas to modify the film formed by the ZnO, SnO 2 , or In 2 O 3 . Sputter deposition of the ZnO, SnO 2 , or In 2 O 3 in an atmosphere comprising a method of manufacturing an increased field effect transistor.
  27. 27. The increased electric field of claim 26, wherein at least one gas for modifying the film formed by ZnO, SnO 2 , or In 2 O 3 comprises at least one gas selected from oxidizing gas and dopant gas. Method of manufacturing an effect transistor.
  28. 28. The method of claim 27 wherein the oxidizing gas comprises oxygen and the dopant gas comprises nitrogen.
  29. 2. The field effect transistor of claim 1, wherein the channel layer comprising ZnO is vapor deposited.
  30. 10. The field effect transistor of claim 9, wherein the insulating SnO 2 or insulating In 2 O 3 is produced by annealing, the insulating ZnO is vapor deposited and the resulting ZnO layer is subjected to annealing.
  31. 14. The method of claim 13, wherein said ZnO is produced by vapor deposition.
  32. 20. A display device comprising at least one display element coupled with a switch comprising an increased field effect transistor produced by the method of manufacturing an increased field effect transistor of any one of claims 16-19. Optoelectronic display device.
  33. 20. A transparent DRAM cell comprising a transparent capacitor coupled with an increased field effect transistor made by the method of manufacturing the increased field effect transistor of any one of claims 16-19.
  34. 20. A transparent logic inverter comprising a load device coupled with an incremental field effect transistor produced by the method of manufacturing the incremental field effect transistor of any one of claims 16-19.
  35. An amplifier comprising an increased field effect transistor produced by the method of manufacturing the increased field effect transistor of any one of claims 16-19.
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KR1020047018750A 2002-05-21 2003-05-15 Transistor structures and methods for making the same KR101023491B1 (en)

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US38269602P true 2002-05-21 2002-05-21
US60/382,696 2002-05-21
US10/307,162 US7189992B2 (en) 2002-05-21 2002-11-27 Transistor structures having a transparent channel
US10/307,162 2002-11-27
US10/350,819 2003-01-24
US10/350,819 US7339187B2 (en) 2002-05-21 2003-01-24 Transistor structures
PCT/US2003/015527 WO2004038757A2 (en) 2002-05-21 2003-05-15 Transistor structures and methods for making the same

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KR100711890B1 (en) 2005-07-28 2007-04-25 삼성에스디아이 주식회사 Organic Light Emitting Display and Fabrication Method for the same
KR100786498B1 (en) * 2005-09-27 2007-12-17 삼성에스디아이 주식회사 Transparent thin film transistor and manufacturing method thereof
KR100739297B1 (en) * 2005-09-28 2007-07-12 삼성에스디아이 주식회사 Flat panel display and method for driving the same
KR100785038B1 (en) * 2006-04-17 2007-12-12 삼성전자주식회사 Amorphous ZnO based Thin Film Transistor
KR100858818B1 (en) * 2007-03-20 2008-09-17 삼성에스디아이 주식회사 Thin film transistor and flat panel display comprising the same
KR101345378B1 (en) 2007-05-17 2013-12-24 삼성전자주식회사 Fabrication method of ZnO family Thin film transistor
KR101334182B1 (en) * 2007-05-28 2013-11-28 삼성전자주식회사 Fabrication method of ZnO family Thin film transistor
KR101345376B1 (en) 2007-05-29 2013-12-24 삼성전자주식회사 Fabrication method of ZnO family Thin film transistor
US7682882B2 (en) 2007-06-20 2010-03-23 Samsung Electronics Co., Ltd. Method of manufacturing ZnO-based thin film transistor
KR101490112B1 (en) 2008-03-28 2015-02-05 삼성전자주식회사 Inverter and logic circuit comprising the same
KR20090124527A (en) 2008-05-30 2009-12-03 삼성모바일디스플레이주식회사 Thin film transistor, method of manufacturing the thin film transistor and flat panel display device having the thin film transistor
KR102015762B1 (en) * 2010-02-19 2019-08-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor memory device, driving method thereof, and method for manufacturing semiconductor device

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