JP2001244408A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that the reliability in the electrical connection between each unit semiconductor device and an external electrical circuit is low due to the difference in the thermal coefficient of expansion between laminated unit semiconductor devices and between the external electrical circuit and the unit semiconductor device. SOLUTION: The semiconductor device is formed by laminating a plurality of unit semiconductor devices 1a, 1b, and 1c up and down, the thermal coefficient of expansion of an insulation substrate 1 of the unit semiconductor device 1a that is located, at least, at the lowest position is equal to 11×10-6/ deg.C-13×10-6/ deg.C, and the difference in the thermal coefficient of expansion of the insulation substrate 1 of the unit semiconductor devices that are adjacent up and down is equal to or less than 5×10-6/ deg.C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted on an information processing device such as a computer, and more particularly, to a semiconductor device in which semiconductor elements are mounted at a high density.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device mounted on an information processing device such as a computer, a semiconductor device of a high-density mounting type for reducing an occupied area in the information processing device generally includes an aluminum oxide sintered body, A structure in which a semiconductor element is mounted on an insulating base having an electrode terminal connected to an electrode of a semiconductor element and made of an electrically insulating material such as a glass ceramic sintered body to form a unit semiconductor device, and the unit semiconductor device is vertically stacked. have.

Further, an upper surface connection terminal and a lower surface connection terminal are formed on an upper surface and a lower surface of the insulating substrate of each of the unit semiconductor devices, respectively, and a connection is made between the electrode terminal, the upper surface connection terminal and the lower surface connection terminal. A wiring layer is formed, and by connecting the upper connection terminal of the lower unit semiconductor device between the adjacent unit semiconductor devices to the lower connection terminal of the upper unit semiconductor device via a low melting point brazing material. The wiring layers of adjacent unit semiconductor devices are electrically connected to each other, and the lower connection terminals of the lowermost unit semiconductor device are electrically and mechanically connected to the circuit wiring of the external electric circuit via a low melting point brazing material. By the connection, the semiconductor element of each unit semiconductor device is electrically connected to the circuit wiring of the external electric circuit, and the semiconductor device is mounted (secondarily mounted) on the external electric circuit.

According to this high-density mounting type semiconductor device, a plurality of semiconductor elements are mounted on top of each other, so that the area occupied by mounting a plurality of semiconductor devices on an information processing device can be reduced. Therefore, there is an advantage that the information processing apparatus can be downsized.

In some cases, different insulating materials are used for the insulating base of each unit semiconductor device depending on the function, characteristics, etc. of the semiconductor element to be mounted.
When the semiconductor element to be mounted generates a large amount of heat during operation, a sintered body of aluminum nitride having excellent thermal conductivity is used, and when the dielectric constant of the insulating base is lowered to prevent a delay of an electric signal, a low level is used. A glass ceramic sintered body having a dielectric constant is used.

[0006]

However, in the above-mentioned conventional semiconductor device, the insulating substrate is generally formed of a ceramic material such as an aluminum oxide sintered body or a glass ceramic, and has a coefficient of thermal expansion of about 2-7. × 10 ^-6 /
C., whereas the thermal expansion coefficient of a printed circuit board made of glass-epoxy or the like, which is most frequently used as an external electric circuit on which a semiconductor device is mounted, is about 12 to 18 × 10 ^−6.
/ ° C is very large. Therefore, when the lower surface connection terminal of the unit semiconductor device located at the bottom of the semiconductor device is connected to the circuit wiring of an external electric circuit such as a printed circuit board via a low melting point brazing material, heat generated when the semiconductor element operates is generated by the semiconductor device. And the external electric circuit are repeatedly applied, a large thermal stress is generated between the insulating base of the lowermost unit semiconductor device and the external electric circuit due to a difference in the coefficient of thermal expansion between the two. Due to repeated application of thermal stress, the low melting point brazing material connecting the lower connection terminal of the lowermost unit semiconductor device and the circuit wiring of the external electric circuit is broken in a short period of time and mounted on each unit semiconductor device. There is a disadvantage that the electrical connection between each semiconductor element and an external electric circuit cannot be stably maintained for a long period of time.

Also, when the insulating bases of the unit semiconductor devices vertically adjacent to each other are formed of different insulating materials, and the thermal expansion coefficients of the two are greatly different from each other, the thermal stress caused by the difference between the thermal expansion coefficients of the two units may also occur. As a result, the low melting point brazing material that connects the upper surface connection terminal of the lower unit semiconductor device and the lower surface connection terminal of the upper unit semiconductor device is broken in a short period of time. There is also a disadvantage that the electrical connection cannot be stably maintained for a long time.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to stack a plurality of unit semiconductor devices on which semiconductor elements are mounted one on top of the other so that semiconductor elements can be mounted at a high density. Another object of the present invention is to provide a semiconductor device capable of stably maintaining the electrical connection between each semiconductor element of each unit semiconductor device and an external electric circuit for a long period of time.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor element is mounted on an insulating base having an electrode terminal, an upper connection terminal and a lower connection terminal formed on the upper and lower surfaces, and a wiring layer connecting the upper connection terminal, the lower connection terminal and the electrode terminal. A unit semiconductor device in which each electrode of a semiconductor element is connected to an electrode terminal, and is formed by vertically stacking,
An upper surface connection terminal of a lower unit semiconductor device between adjacent unit semiconductor devices is connected to a lower surface connection terminal of an upper unit semiconductor device via a low melting point brazing material, and a lowermost unit semiconductor device. Wherein the lower surface connection terminal of the semiconductor device is connected to the circuit wiring of the external electric circuit via a low melting point brazing material, wherein the thermal expansion coefficient of the insulating base of at least the lowermost unit semiconductor device is 11 × 1.
0 ⁻⁶ / ° C. to 13 × 10 ⁻⁶ / ° C., and the thermal expansion coefficient difference between the insulating bases of the unit semiconductor devices vertically adjacent to each other is 5 ×.
It is characterized in that it is 10 ^-6 / ° C or less.

According to the semiconductor device of the present invention, at least the thermal expansion coefficient of the insulating base of the lowermost unit semiconductor device directly connected to the external electric circuit is from 11 × 10 ⁻⁶ / ° C. to 13 × 1.
0 ⁻⁶ / ° C., the difference in thermal expansion coefficient between the insulating base of the lowermost unit semiconductor device and the external electric circuit was 5 × 10
^-6 / ° C. or less, no large thermal stress is generated between them, and a low melting point brazing material for connecting the lower surface connection terminal of the lowermost unit semiconductor device and the circuit wiring of the external electric circuit. Can be effectively prevented from breaking, and the electrical connection between each semiconductor element mounted on each unit semiconductor device and the external electric circuit can be stably maintained for a long period of time.

Further, according to the semiconductor device of the present invention, since the difference in thermal expansion coefficient between the insulating bases of the vertically adjacent unit semiconductor devices is reduced to 5 × 10 ⁻⁶ / ° C. or less, the vertically adjacent unit semiconductor devices are reduced. A large thermal stress does not occur between the devices, effectively preventing the low melting point brazing material connecting the upper surface connection terminals and the lower surface connection terminals of the vertically adjacent unit semiconductor devices from being broken in a short period of time. The electric connection with the external electric circuit can be stably maintained for a long time.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a semiconductor device according to the present invention, wherein 1a, 1b and 1c are unit semiconductor devices. Each of the unit semiconductor devices 1a, 1b and 1c has an insulating base 1, a semiconductor element 2 and a top connection terminal. 3, lower surface connection terminals 4, electrode terminals 5, and wiring layers 6, and upper surface connection terminals 3 of the unit semiconductor device located below between adjacent unit semiconductor devices, and lower surface connection terminals of the unit semiconductor device located above. 4 via a low melting point brazing material 8, and the lower surface connection terminal 4 of the lowermost unit semiconductor device 1a is connected to a circuit wiring of an external electric circuit via a low melting point brazing material 8. ing.

The insulating substrate 1 of each of the unit semiconductor devices 1a, 1b, and 1c has a concave portion A formed on the upper surface thereof. In the concave portion A, the semiconductor element 2 is made of an adhesive such as a brazing material, glass, or resin. The electrode of the semiconductor element 2 is electrically connected to the electrode terminal 5 through the bonding wire 9 while being housed by being adhered and fixed.

A sealing resin 10 is filled in the recess A of each insulating base 1 in which the semiconductor element 2 is accommodated, and the semiconductor element 2 is hermetically sealed by the sealing resin 10. .

The unit semiconductor devices 1a, 1b and 1c are at least the lowermost unit semiconductor devices 1a, 1b and 1c.
The insulating substrate 1 of a is 11 × 10 ⁻⁶ / ° C. to 13 × 10 ⁻⁶ / ° C.
Is formed of an insulating material having a thermal expansion coefficient of
Since the thermal expansion coefficient of the insulating substrate 1 of the lowermost unit semiconductor device 1a is 11 × 10 ⁻⁶ / ° C. to 13 × 10 ⁻⁶ / ° C., the thermal expansion coefficient is about 12 × 10 ⁻⁶ / ° C. 18 × 10
^When mounted on an external electric circuit made of glass-epoxy or the like at a temperature of ⁻⁶ / ° C., the difference in thermal expansion coefficient between the insulating base 1 of the lowermost unit semiconductor device 1a and the external electric circuit is 5 × 10 ⁻⁶ / ° C. or less. As a result, even if the heat generated during the operation of the semiconductor element 2 is repeatedly applied to both the unit semiconductor device 1a and the external electric circuit, no large thermal stress is generated between them. The low melting point brazing material 8 connecting the lower surface connection terminal 4 of the lowermost unit semiconductor device 1a and the circuit wiring of the external electric circuit is effectively prevented from being broken, and mounted on each unit semiconductor device 1a, 1b, 1c. Electrical connection between each semiconductor element 2 and an external electric circuit can be stably maintained for a long period of time.

The coefficient of thermal expansion is 11 × 10 ⁻⁶ / ° C. to 13
For example, the insulating base 1 of the unit semiconductor device 1a located at the lowermost part of × 10 ⁻⁶ / ° C. has a coefficient of thermal expansion at 40 ° C. to 400 ° C. of 6 × 10 ⁻⁶ / ° C. to 18 × 10 ⁻⁶ / ° C. A crystalline or non-crystalline glass component having a deformation point of 400 ° C. to 800 ° C. is 20 to 80% by volume, and a filler having a thermal expansion coefficient of 6 × 10 ⁻⁶ / ° C. or more at 40 ° C. to 400 ° C. is 80 to 20%.
It can be formed by a sintered body formed by firing a molded body containing a volume%, and specifically, as a glass component, lithium silicate glass, PbO glass, BaO glass, ZnO glass. It is preferably used.

In the case of crystallized glass, the coefficient of thermal expansion of the glass component refers to the coefficient of thermal expansion after heat treatment at the firing temperature, and means the coefficient of linear thermal expansion.

When a lithium silicate glass is used as the glass component, it is preferable that Li ₂ O is contained in a proportion of 5 to 30% by weight, particularly 5 to 20% by weight, so that a high thermal expansion coefficient is obtained after firing. Can be precipitated. As the above lithium silicate glass, including SiO ₂ as an essential component in addition to Li ₂ O, SiO ₂ is in the glass the total amount, present in a proportion of 60 to 85 wt%, SiO ₂ and Li ₂ O Is preferably 65 to 95% by weight based on the total amount of glass in order to precipitate lithium silicate crystals. Furthermore, in addition to these components,
Al ₂ O ₃ , MgO, TiO ₂ , B ₂ O ₃ , Na ₂ O, K
₂ O, P ₂ O ₅ , ZnO, F and the like may be blended.
However, in this lithium silicate glass, B ₂ O ₃ is desirably 1% by weight or less.

When a PbO-based glass is used as a glass component, PbO is used as a main component, and further, B ₂ O ₃ , Si
A material formed of a glass powder containing at least one of O ₂ and having a high thermal expansion crystal phase such as PbSiO ₃ or PbZnSiO ₄ after firing is preferably used. Especially, PbO (65 to 85 _{wt%) - B 2 O 3 (} 5~1
5% by weight) -ZnO (6 to 20% by weight) -SiO
₂ (0.5 to 5% by weight) -crystalline glass composed of BaO (0 to 5% by weight) or PbO (50 to 60% by weight) -S
iO ₂ (35 to 50 wt%) - Al ₂ O ₃ crystalline glass consisting of (1-9 wt%) is desirable.

Furthermore when using the ZnO-based glass as a glass component, glass containing ZnO 10 wt% or more, the crystal phase of the thermal expansion coefficient of the _{ZnO · Ai 2 O 3, ZnO} · nB 2 O 3 or the like after firing It is preferable to be precipitated, and as components other than ZnO, SiO2 (60% by weight or less), A
l ₂ O ₃ (60% by weight or less), B ₂ O ₃ (30% by weight or less), P ₂ O ₅ (50% by weight or less), alkaline earth oxide (20% by weight or less), Bi ₂ O ₃ ( 30% by weight or less). From this point, particularly, ZnO
10 to 50 wt% -Al ₂ O ₃ 10~30 wt% -SiO
₂ 30-60% by weight of crystalline glass, ZnO1
0-50 wt% -SiO ₂ 5 to 40 wt% -Al ₂ O ₃ 0
~ 15% by weight-BaO0 ~ 60% by weight-MgO0 ~ 35
Crystalline glasses consisting of% by weight are preferably used.

Further, when a BaO-based glass is used as a glass component, it contains BaO in an amount of 10% by weight or more, and after firing, BaAl ₂ SiO ₂ O ₈ , BaSi ₂ O ₅ , BaB ₂ Si.
What precipitates a crystal phase such as ₂ O ₈ is employed. BaO
Components other than Al ₂ O ₃ , SiO ₂ , B ₂ O ₃ , P ₂
O ₅ , an alkaline earth oxide, an alkali metal oxide, or the like may be included.

The deformation point of the above glass component is 4
The temperature is desirably from 00 to 800 ° C, particularly preferably from 400 to 650 ° C. This effectively removes a molding binder such as an organic resin added when molding a mixture composed of a glass component and a filler component, and also includes an upper connection terminal 3 and a lower connection terminal made of copper, silver, and the like described later. 4. The purpose is to match the simultaneous firing conditions with the conductive paste to be the electrode terminals 5 and the wiring layer 6. If the yield point is lower than 400 ° C., the crystalline glass starts sintering at a low temperature. For example, the sintering start temperature of copper, silver, etc. is 600 to 800 ° C.
Is difficult to bake simultaneously with the conductive paste, and the densification of the molded body starts at a low temperature, so that the binder cannot be decomposed and volatilized, and the binder component remains to affect the properties.

If the yield point is higher than 800 ° C., sintering becomes difficult unless the amount of glass is increased, so that a large amount of expensive glass is required and the cost of the sintered body is increased.

On the other hand, the thermal expansion coefficient is 6 × 10^-6/ ℃ or more
Cristobalite (Si)
O_Two), Quartz (SiO_Two), Tridymite (Si
O_Two), Forsterite (2MgO.SiO)_Two), Spy
Flannel (MgO · Al_TwoO_Three), Wollastonite (CaO
・ SiO_Two), Monticellanite (CaO.MgO.)
SiO_Two), Nepheline (Na_TwoO ・ Al_TwoO_Three・ Si
O_Two), Lithium silicate (LiO _Two・ SiO_Two),
Opside (CaO ・ MgO ・ 2SiO_Two), Melvina
(3CaO.MgO.2SiO)_Two), Akermite
(2CaO.MgO.2SiO_Two), Magnesia (Mg
O), alumina (Al_TwoO_Three), Carnegieite (Na_Two
O ・ Al_TwoO_Three. 2SiO_Two), Enstatite (MgO)
・ SiO_Two), Magnesium borate (2MgOB
_TwoO_Three), Celsian (BaO.Al)_TwoO_Three・ 2Si
O_Two), B_TwoO_Three・ 2MgO ・ 2SiO_Two, Garnite (Z
nO · Al_TwoO_Three), Petalite (LiAlSi_FourO_Ten)
At least one selected from the group of
You.

After adding an appropriate organic binder to the mixture of the above-mentioned glass component and filler component, the mixture is formed into a sheet by a doctor blade method, a calender roll method, or the like, and a ceramic green sheet (ceramic green sheet) is formed. Thereafter, the ceramic green sheet is appropriately punched to form a predetermined shape, and a plurality of the green sheets are laminated and fired, so that the coefficient of thermal expansion is 11 × 10 ⁻⁶ / ° C. to 13 × 10 ^{6 -6} / ℃ insulating substrate 1
Is produced.

In the above-mentioned firing, first, the binder component blended for molding is removed. The binder is removed in an air atmosphere at about 700 ° C. However, when copper is used as a material for the conductor paste, for example, 1 is used.
This is performed in a nitrogen atmosphere containing steam at 00 to 700 ° C. At this time, the shrinkage start temperature of the ceramic green sheet is desirably about 700 to 850 ° C. If the shrinkage start temperature is lower than this, it is difficult to remove the binder. In particular, it is necessary to control the yield point as described above.

The calcination is performed in an oxidizing atmosphere or a non-oxidizing atmosphere at 850 ° C. to 1050 ° C., whereby the relative density is increased to 90% or more. However, in the case where a conductive paste such as copper is applied and fired simultaneously, as described later, firing is performed in a non-oxidizing atmosphere such as a nitrogen or nitrogen / hydrogen mixed atmosphere in which copper or the like is not oxidized.

The insulating substrate 1 having a thermal expansion coefficient of 11 × 10 ⁻⁶ / ° C. to 13 × 10 ⁻⁶ / ° C. produced as described above contains a crystal phase formed from a glass component and a glass component. There is a crystal phase generated by the reaction between the filler component and the filler component, a filler component, or a crystal phase generated by decomposition of the filler component, and a glass phase exists at the grain boundaries of these crystal phases.

The unit semiconductor devices 1a, 1b, 1
c, the unit semiconductor devices 1b, 1
The insulating substrate 1 of c is made of the same insulating material as the insulating substrate 1 of the lowermost unit semiconductor device 1a, or the difference in thermal expansion coefficient between the vertically adjacent unit semiconductor devices 1a, 1b, and 1c is 5 ×. Various materials having a temperature of 10 ⁻⁶ / ° C. or less, specifically, aluminum oxide sintered body, mullite sintered body, silicon carbide sintered body, aluminum nitride sintered body, glass ceramic sintered body, etc. Can be formed of the above insulating material.

When the unit semiconductor devices 1a, 1b, and 1c are vertically stacked, the difference in thermal expansion coefficient between the insulating substrates 1 of the vertically adjacent unit semiconductor devices is as small as 5 × 10 ⁻⁶ / ° C. or less. A large thermal stress does not occur between the adjacent unit semiconductor devices, so that the low melting point brazing material 7 connecting the upper surface connection terminals 3 and the lower surface connection terminals 4 of the vertically adjacent unit semiconductor devices is broken in a short period of time. Will not
Electrical connection between each semiconductor element 2 of each unit semiconductor device 1a, 1b, 1c and an external electric circuit can be stably maintained for a long time.

The unit semiconductor devices 1b, 1
For example, when the insulating substrate 1 of c is formed of an aluminum oxide-based sintered body, an appropriate organic binder, a solvent, and the like are added to and mixed with raw material powders of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. The ceramic green sheet is formed by employing a doctor blade method, a calendar roll method, or the like, and then the ceramic green sheet is appropriately punched to form a predetermined shape. Are laminated and fired at a high temperature (about 1600 ° C.).

The unit semiconductor devices 1a, 1b, 1c
Each of the insulating bases 1 has an upper surface connecting terminal 3 and a lower surface connecting terminal 4 formed on the upper and lower surfaces thereof, and an electrode terminal 5 formed on the periphery of the bottom surface of the concave portion A, respectively. Wiring layer 6 between terminal 3 and lower surface connection terminal 4
Connected by

The upper connection terminal 3 and the lower connection terminal 4
Functions as a terminal for electrically and mechanically connecting the vertically adjacent unit semiconductor devices, the electrode of the semiconductor element 2 is connected to the electrode terminal 5 via a bonding wire 9 or the like,
The electrodes of the semiconductor element 2 are connected to the upper connection terminal 3 or the lower connection terminal 4.
And has a function of connecting to the wiring layer 6 that is connected to the wiring layer 6.

The upper connection terminal 3, the lower connection terminal 4, the electrode terminal 5, and the wiring layer 6 are made of, for example, tungsten, molybdenum, manganese, copper, silver, nickel, palladium,
It is formed of a metal material such as gold, and the metal material to be used is appropriately selected depending on the insulating material forming the insulating base 1. For example, the insulating base 1 of the unit semiconductor device 1a located at the bottom is Since the insulating base 1 is formed of a glass component and a filler and has a low softening and melting temperature, at least one of copper, silver, nickel, palladium, and gold is preferably used, and the unit semiconductor device 1 located on the upper side is used.
When b and 1c are formed of an aluminum oxide-based sintered body, a mullite-based sintered body, a silicon carbide-based sintered body, an aluminum nitride-based sintered body, etc., a high melting point metal such as tungsten, molybdenum, or manganese is used. It is preferably used.

The upper connection terminal 3, the lower connection terminal 4, the electrode terminal 5, and the wiring layer 6 are made of tungsten, molybdenum,
A conductive paste is prepared by mixing a suitable organic binder and a solvent with a powder of a metal material such as manganese, copper, silver, nickel, palladium, and gold, and is then screened in advance on a sheet-like molded body that becomes the insulating substrate 1 by firing. The insulating substrate 1 is printed and applied in a predetermined pattern by a printing method or the like.
Is formed in a predetermined shape at a predetermined position.

The upper connection terminal 3, the lower connection terminal 4, and the electrode terminal 5 are connected to each other before the semiconductor element 2 is mounted.
In advance, the exposed surface is coated with a highly conductive metal (not shown) having excellent corrosion resistance such as nickel and gold, good wettability of a low melting point brazing material, and good bonding property of a bonding wire by plating or the like. When it is adhered to a thickness of 20 μm, oxidation corrosion of the upper connection terminal 3, the lower connection terminal 4, and the electrode terminal 5 can be effectively prevented, and a low melting point solder for the upper connection terminal 3 and the lower connection terminal 4. The wettability of the members 7 and 8 and the bonding property of the bonding wire 9 to the electrode terminal 5 can be improved. Therefore, before mounting the semiconductor element 2, the upper connection terminal 3, the lower connection terminal 4, and the electrode terminal 5 are coated with a metal such as nickel or gold to a thickness of 1 μm to 20 μm by plating or the like. It is preferable to keep it on.

Thus, according to the above-described semiconductor device, the unit semiconductor devices 1a, 1b, and 1c are vertically stacked, and the upper connection terminals 3 of the lower unit semiconductor device are positioned between the adjacent unit semiconductor devices. To the lower surface connection terminal 4 of the unit semiconductor device to be connected via the low melting point brazing material 7, and the lower surface connection terminal 4 of the unit semiconductor device 1 a located at the lowest position is connected to the circuit wiring of the external electric circuit by the low melting point brazing material 8. If they are connected via an external electric circuit, the semiconductor elements 2 of the unit semiconductor devices 1a, 1b, and 1c are electrically connected to the external electric circuit at the same time.

It should be noted that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the scope of the present invention.
Although an example in which the two unit semiconductor devices 1a, 1b, and 1c are stacked has been described, a stack of two unit semiconductor devices or a stack of four or more unit semiconductor devices may be used.

[0039]

According to the semiconductor device of the present invention, a plurality of unit semiconductor devices are vertically stacked, and at least the thermal expansion coefficient of the insulating base of the lowermost unit semiconductor device directly connected to an external electric circuit is reduced. 11 × 10 ^-6 / ° C to 13 × 10 ^-6 /
° C, the difference between the thermal expansion coefficient of the insulating substrate of the lowermost unit semiconductor device and the coefficient of thermal expansion of the external electric circuit is 5 × 10 ^-6 / ° C.
The low melting point brazing material connecting the lower surface connection terminal of the lowermost unit semiconductor device and the circuit wiring of the external electric circuit can be broken without generating a large thermal stress between the two. Is effectively prevented, and the electrical connection between each semiconductor element mounted on each unit semiconductor device and the external electric circuit can be stably maintained for a long period of time.

According to the semiconductor device of the present invention, the difference in thermal expansion coefficient between insulating substrates of vertically adjacent unit semiconductor devices is reduced to 5 × 10 ⁻⁶ / ° C. or less. A large thermal stress does not occur between the devices, effectively preventing the low melting point brazing material connecting the upper surface connection terminals and the lower surface connection terminals of the vertically adjacent unit semiconductor devices from being broken in a short period of time. The electric connection with the external electric circuit can be stably maintained for a long time.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

[Explanation of symbols]

 1a, 1b, 1c ... unit semiconductor device 1 ... insulating base 2 ... semiconductor element 3 ... ..Top connection terminal 4 ... Bottom connection terminal 5 ... Electrode terminal 6 ... Wiring layer 7, 8 Low-melting brazing material 9 Bonding wire A recess

Claims (1)

[Claims] An insulating substrate having an electrode terminal, an upper connection terminal and a lower connection terminal formed on the upper and lower surfaces, and a wiring layer connecting the upper connection terminal, the lower connection terminal and the electrode terminal. A semiconductor element is mounted and unit semiconductor devices in which each electrode of the semiconductor element is connected to an electrode terminal are vertically stacked, and the upper connection terminals of the unit semiconductor device located at a lower position between adjacent unit semiconductor devices are disposed at an upper position. The lower surface connection terminal of the lowermost unit semiconductor device is connected to the lower surface connection terminal of the unit semiconductor device located therethrough via a low melting point brazing material, and the lower surface connection terminal of the unit semiconductor device located at the bottom is connected to the circuit wiring of the external electric circuit via the low melting point brazing material. a semiconductor device that, said a thermal expansion coefficient of the insulating base of the unit semiconductor device positioned on at least the bottom is ^{11 × 10 -6 / ℃ ~13 ×} 10 -6 / ℃, and adjacent to the vertical Position wherein a difference in thermal expansion coefficient between the insulating substrate of the semiconductor device is 5 × 10 ^-6 / ℃ or less.