JP2001243766A - 半導体記憶装置 - Google Patents
半導体記憶装置Info
- Publication number
- JP2001243766A JP2001243766A JP2000054883A JP2000054883A JP2001243766A JP 2001243766 A JP2001243766 A JP 2001243766A JP 2000054883 A JP2000054883 A JP 2000054883A JP 2000054883 A JP2000054883 A JP 2000054883A JP 2001243766 A JP2001243766 A JP 2001243766A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- counter
- count value
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000054883A JP2001243766A (ja) | 2000-02-29 | 2000-02-29 | 半導体記憶装置 |
| US09/791,839 US6404688B2 (en) | 2000-02-29 | 2001-02-26 | Semiconductor memory device having a self-refresh operation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000054883A JP2001243766A (ja) | 2000-02-29 | 2000-02-29 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001243766A true JP2001243766A (ja) | 2001-09-07 |
| JP2001243766A5 JP2001243766A5 (enExample) | 2004-12-02 |
Family
ID=18576081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000054883A Pending JP2001243766A (ja) | 2000-02-29 | 2000-02-29 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6404688B2 (enExample) |
| JP (1) | JP2001243766A (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100431331B1 (ko) * | 2002-08-21 | 2004-05-12 | 삼성전자주식회사 | 반도체 메모리장치의 입출력 센스 앰프 구동방법 및 그구동제어회로 |
| JP2007273028A (ja) * | 2006-03-31 | 2007-10-18 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| KR100810060B1 (ko) | 2006-04-14 | 2008-03-05 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 및 그의 구동방법 |
| US7447096B2 (en) * | 2006-05-05 | 2008-11-04 | Honeywell International Inc. | Method for refreshing a non-volatile memory |
| CN103617805A (zh) * | 2013-12-09 | 2014-03-05 | 深圳市品凌科技有限公司 | 存储设备、通过存储芯片的再次利用制造存储设备的方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5243576A (en) * | 1990-08-30 | 1993-09-07 | Nec Corporation | Semiconductor memory device |
| KR0171930B1 (ko) * | 1993-12-15 | 1999-03-30 | 모리시다 요이치 | 반도체 메모리, 동화기억 메모리, 동화기억장치, 동화표시장치, 정지화기억 메모리 및 전자노트 |
| US5446695A (en) * | 1994-03-22 | 1995-08-29 | International Business Machines Corporation | Memory device with programmable self-refreshing and testing methods therefore |
| KR0122107B1 (ko) * | 1994-06-04 | 1997-12-05 | 김광호 | 저전력 셀프리프레쉬 및 번-인 기능을 가지는 반도체메모리장치 |
-
2000
- 2000-02-29 JP JP2000054883A patent/JP2001243766A/ja active Pending
-
2001
- 2001-02-26 US US09/791,839 patent/US6404688B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US6404688B2 (en) | 2002-06-11 |
| US20010017810A1 (en) | 2001-08-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20061018 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20061107 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070109 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20071002 |