JP2001237381A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: TO provide a high voltage-resistant IC for control with a small chip area which has no erroneous ignition of a switching element even if both group and stray potentials exist. SOLUTION: A GND reference circuit 3 is formed on an A substrate 2a and a stray reference circuit 4 is formed on an B substrate 2b. A level-up circuit for commonly setting the reference potential level of the GND reference circuit 3 and stray reference circuit 4 is constituted of a high voltage-resistent N-ch MOSFET 5 formed in the GND reference circuit 3, and level shift resistor 6 formed in the floating reference circuit 4. A level-down circuit for commonly setting the reference voltage level is constituted of a high voltage-resistent P-ch MOSFET 7 formed in the stray reference circuit 4, and a level shift resistor 8 formed in the GND reference circuit 3. The stray reference circuit 4 is surrounded by a HVJT 9 and is electrically insulated from the potential of the B substrate 2b itself.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a control IC used for drive control of a switching element such as a power device, and more particularly, to a circuit based on a ground potential and a fluctuation caused by switching of a power device or the like. The present invention relates to a high withstand voltage semiconductor device in which a circuit based on a floating potential is mixed.

[0002]

2. Description of the Related Art In recent years, with the commercialization of high-voltage integrated circuits (hereinafter referred to as HVICs: High Voltage Integrated Circuits) of several hundred volts, I / O devices for driving power devices such as IGBTs used in inverters for motor control and the like have been developed.
As C, this HVIC is being applied. FIG.
FIG. 3 is a circuit configuration diagram of a main circuit portion of a motor control inverter. In the figure, an inverter circuit for driving a three-phase motor Mo is configured by connecting power devices of IGBTs Q1 to Q6 and feedback diodes D1 to D6 to a three-phase bridge circuit. The IGBT is an insulated gate bipolar transistor. The main power supply Vcc of the three-phase motor Mo is normally a high voltage of about 100 to 1200 V DC. Also, the wiring U, V, W of the three-phase motor Mo
When the high potential side of the main power supply Vcc is Vcc and the low potential side is GND, the potential fluctuates between GND and Vcc according to the switching of the power device of each phase.

Therefore, in order to drive the high potential side IGBTs Q1, Q2, Q3 connected to Vcc,
A floating reference gate drive circuit using a potential fluctuating between D and Vcc as a reference potential is required. In order to control this with a GND reference signal, an insulation connection using a photocoupler or the like is provided between the GND reference control circuit and the floating reference gate drive circuit, or an HVIC having a built-in level shift circuit is used. There is a need to.

FIG. 7 shows a configuration using an HVIC having a built-in level shift circuit for driving the gates of the IGBTs Q1 to Q6. This HVIC has an input / output terminal I /
Usually, it is connected to a microcomputer (not shown) via O (Input / Output). Further, the output terminals of the gate drive circuit of the HVIC are electrically connected to the gates of the IGBTs Q1 to Q6 by wire wiring or the like. Therefore, the whole inverter is controlled by the microcomputer.

FIG. 8 shows a conventional HVIC used in FIG.
FIG. 2 is a block diagram showing an internal configuration of the device. In FIG. 1, only one arm of the inverter circuit connected to the HVIC is shown in a simplified manner. In FIG. 1, the HVIC 11 mounted on one substrate 1 includes a control circuit 12, a floating reference gate drive circuit 13, and a GND reference gate drive circuit 1.
4, a level-up circuit 15 and a level-down circuit 16. The control circuit 12 is a circuit that uses a ground (hereinafter referred to as GND) as a reference potential, exchanges signals with a microcomputer (not shown) through input / output terminals I / O, and turns on / off each IGBT.
It has a function of generating a control signal for turning it off, stopping a gate signal to the IGBT based on the received alarm signal, or transmitting an alarm signal to the microcomputer.

[0006] The floating reference gate drive circuit 13 is a circuit for providing a drive signal to the gate of each IGBT connected to the Vcc side, and the output potential to a motor (not shown) that fluctuates according to the switching of each IGBT. Is a circuit based on. That is, the IGBT generated by the control circuit 12
Is provided through the level-up circuit 15 to turn on / off the IGBT on the high potential side. Furthermore, it has functions such as temperature detection, overcurrent protection and low voltage protection, and performs I / O based on the detected information.
It has a function of turning off the GBT or transmitting an alarm signal or a warning signal based on the detection information to the control circuit 12 through the level down circuit 16.

[0007] The GND reference gate drive circuit 14 has a function of receiving the ON / OFF signal of the IGBT generated by the control circuit 12 and turning on / off the IGBT on the low potential side. In addition, it has functions such as temperature detection, overcurrent protection and low voltage protection.
It has a function of turning off T or transmitting an alarm signal or a warning signal based on such detection information to the control circuit 12.

The level up circuit 15 converts the GND reference signal from the control circuit 12 into a floating reference signal level having a higher potential than GND, and converts the signal into a floating reference gate driving circuit 13.
This is a circuit for transmitting the data. FIG. 9 is an example of a specific circuit diagram of the level-up circuit 15 of FIG. That is, the level shift resistor 6 is connected to the drain D side of the high breakdown voltage Nch MOSFET 5. High pressure resistance N
When the gate G of the ch MOSFET 5 is biased with respect to the source S electrode to a positive potential equal to or higher than the threshold value,
The ch MOSFET 5 is turned on, a current flows through the level shift resistor 6, a signal voltage is generated, and a signal is output from OUT1. Here, the resistor 40 is a resistor for improving the low current property of the high withstand voltage Nch MOSFET by applying feedback, and may be omitted.

Returning to FIG. 8, the level down circuit 16
This circuit converts a floating reference signal generated by the floating reference gate drive circuit 13 into a GND reference signal voltage and transmits the signal voltage to the control circuit 12. FIG. 10 is an example of a specific circuit diagram of the level down circuit 16 of FIG. That is, the level shift resistor 8 is connected to the drain D side of the high breakdown voltage Pch MOSFET 7. High breakdown voltage Pch M
When the gate G of the OSFET 7 is biased with respect to the source S electrode to a negative potential equal to or lower than the threshold, a high breakdown voltage Pch MO
The SFET 7 is turned on, a current flows through the level shift resistor 8, a signal voltage is generated, and a signal is output from OUT2. Here, the resistance 41 is fed back to provide a high withstand voltage Nch MO.
Low resistance to improve the low current property of SFET,
It may be omitted.

FIG. 11 is a schematic diagram showing a main part when a conventional level shift circuit is formed on a semiconductor substrate. That is, the level-up circuit of FIG. 9 and the level-down circuit of FIG. 10 are formed on one substrate 1. Therefore, the GND reference circuit 3 and the floating reference circuit 4 are formed on the same substrate. The floating reference circuit 4 is configured to be surrounded by a withstand voltage structure (HVJT: high withstand voltage termination junction structure) 9.

In FIG. 11, the level-up circuit shown in FIG.
It is composed of a ch MOSFET 5 and a level shift resistor 6 formed in the floating reference circuit 4. further,
High withstand voltage Nch MOSF configured in GND reference circuit 3
The drain portion of ET5 has an H structure similar to HVJT9.
The withstand voltage is secured by the VJT 10 '. And
The drain of the high breakdown voltage Nch MOSFET 5 and the level shift resistor 6 are electrically connected by a drain wiring.

In FIG. 11, the level down circuit shown in FIG. 10 is composed of a high breakdown voltage Pch MOSFET 7 formed in the floating reference circuit 4 and a level shift resistor 8 formed in the GND reference circuit 3. Have been.
The drain of the high breakdown voltage Pch MOSFET 7 and the level shift resistor 8 are electrically connected by a drain wiring. The floating reference circuit 4 outputs HV from the GND reference circuit 3.
It is electrically insulated through JT9. Also, the drain portion of the high-breakdown-voltage Pch MOSFET 7 formed in the floating reference circuit 4 has a structure similar to that of the HVJT 9.
0 secures the withstand voltage.

FIG. 12 is a specific sectional structural view of a conventional level down circuit. That is, an example of a cross-sectional structure of a conventional level-down circuit using a self-isolation structure is shown. This drawing is a cross-sectional structure diagram of the level shift circuit of FIG. 11 cut along AA ′, and an equivalent circuit is a cross-sectional structure diagram of a level down circuit portion using the high breakdown voltage Pch MOSFET 7 of FIG.

This structure has a structure in which GND is formed on one semiconductor substrate.
An area for the reference circuit 3 and an area for the floating reference circuit 4 are provided. A level shift resistor 8 is formed on the surface of the region of the GND reference circuit 3, and a high withstand voltage P is formed on the region of the floating reference circuit 4.
A ch MOSFET is formed. Further, a predetermined portion of the surface is subjected to aluminum wiring or wire bonding to perform predetermined wiring. Also, P ^- substrate 3
N 1 of the surface ^- the band 32 is formed to separate the high-voltage part using a reverse bias of the PN junction, and further, P ^- / N ^- in order to relax the electric field of the junction surface portion of the junction, N ^- region Doubl based on RESURF principle with P ^- region 33 formed on the surface
e The HVJTs 9 and 10 for adopting the RESURF structure and improving the breakdown voltage to near the junction breakdown voltage of the P ⁻ / N ⁻ parallel plate are provided.

The high breakdown voltage Pch MOSFET shown in FIG.
7 is formed in the floating reference circuit 4 formed on the same substrate 1 as the GND reference circuit 3, and the HVJT of the floating reference circuit 4
9 and the HVJT 10 of the high breakdown voltage Pch MOSFET 7 itself.
Thus, the structure has a double pressure-resistant structure. The level shift resistor 8 is a high-withstand-voltage Pch MOSFET.
The drain 7 is electrically connected by aluminum wiring or wire wiring. Double RESUR in Fig. 12
In the case of a withstand voltage structure having an F structure, a withstand voltage structure width of about 100 μm is required in a 600 V withstand voltage class.
A withstand voltage structure width of approximately 200 μm or more in the 00V withstand voltage class is required.

[0016]

The high withstand voltage I as described above
When driving a power device such as an IGBT used for an inverter for motor control or the like, it is important for the C (HVIC) to prevent the IGBT from malfunctioning due to noise caused by dv / dt or the like. Further, from the viewpoint of reducing the cost of the chip, it is important to reduce the area of the HVJT, which occupies a large area, as much as possible. However, the conventional HVIC has disadvantages such as erroneous firing of the IGBT due to dv / dt, and an increase in the breakdown voltage increases the area occupied by the HVJT and the size of the chip. Therefore, it is necessary to solve such a problem.

First, a problem relating to a malfunction caused by switching will be described. As shown in FIG. 8, in the conventional HVIC 11, a control circuit 12, a floating reference gate drive circuit 13, a GND reference gate drive circuit 14, a level up circuit 15 and a level down circuit 16 are formed on the same substrate 1. I have. Therefore, as shown in FIG.
Therefore, it is necessary to connect each IGBT with a long wire. Therefore, the following problem occurs due to the parasitic inductance of the wiring. This will be described with reference to the connection diagram between the conventional HVIC and the IGBT constituting a part of the inverter shown in FIG. The high-potential side IGBT 17a and the low-potential side IGBT 17b alternately repeat ON / OFF according to the control timing of the three-phase inverter, so that the potential of OUT fluctuates between GND and Vcc. Is output.

Here, when the gate G of the high potential side IGBT 17a is turned on and the potential of OUT changes from GND to Vcc, the potential of the collector C of the low potential side IGBT 17b also changes from GND to Vcc. Then, due to the dv / dt caused by the potential change at this time, the potential of the G is changed through the parasitic capacitance 18b between the collector C and the gate G of the low potential side IGBT 17b.
The ND reference gate drive circuit 14 supplies a displacement current i
(t) flows. In particular, a large dv / dt occurs in a time zone in which the low potential side feedback diode 19b connected in parallel to the low potential side IGBT 17b reversely recovers, and a large displacement current i (t) flows based on this. At this time, the wiring from the GND reference gate drive circuit 14 to the low potential side IGBT17b parasitic inductance _L L 20b both ends L _L · di of
A back electromotive force of (t) / dt occurs. If the wiring becomes longer, the parasitic inductance L _L becomes larger, and the back electromotive force becomes lower potential I
When the voltage exceeds the threshold voltage of the gate G of the GBT 17b, the low potential side IGBT 17b is turned on. At this time, since the high-potential-side IGBT 17a is naturally ON, Vcc and GN
D may short-circuit and destroy both IGBTs 17a and 17b.

Similarly, the low potential side IGBT 17b is turned on.
When the potential of OUT changes from Vcc to GND,
The potential of the collector C of the high potential side IGBT 17a becomes relatively higher than the potentials of the gate G and the emitter E by the potential difference between GND and Vcc, and passes through the parasitic capacitance 18a between the collector C and the gate G of the high potential side IGBT 17a. A displacement current i (t) flows through the floating reference gate drive circuit 13.
At this time, the floating reference gate drive circuit 13 supplies the high potential side IG
Parasitic inductance L _H 20a of wiring up to BT 17a
A back electromotive force of L _H · di (t) / dt is generated in the two cases. In particular, when the parasitic inductance L _H 20a is sufficiently large and the back electromotive force exceeds the threshold voltage of the gate of the high-potential side IGBT 17a, the high-potential side IGBT 17a turns ON and Vcc
And GND may be short-circuited, and both IGBTs 17a and 17b may be destroyed. As described above, the larger the parasitic inductance of each IGBT is, the larger the displacement current is, so that a malfunction is more likely to occur. Therefore, in order to realize a control IC for driving a large-capacity IGBT, it is essential to solve such a problem.

Next, the problem of reducing the chip size of the device by reducing the area of the HVJT occupying a large area is described. That is, the conventional HVIC shown in FIG.
In this case, the floating reference circuit 4 needs to surround the outer periphery with the HVJT 9. In addition, in order to obtain a sufficient withstand voltage, HVJ
The width of the pressure-resistant structure of T9 must be sufficiently wide. Accordingly, the area of the HVJT 9 occupying the floating reference circuit 4 may be considerably large depending on the magnitude of the withstand voltage.

When the withstand voltage structure of the Double RESURF structure as shown in FIG.
HVJT requires a withstand voltage structure width of about 100 μm, which occupies approximately 20 to 40% of the entire floating reference circuit 4 of FIG. In the 1200 V breakdown voltage class, the HVJT requires a breakdown voltage structure width of about 200 μm, which is approximately 30 to 60 of the entire floating reference circuit 4 in FIG.
% Of the area. Therefore, in the prior art, increasing the cost due to an increase in the chip size is a major issue in increasing the withstand voltage of the HVIC.

One of the problems of HVIC is a problem of long-term reliability. In the case of a level shifter using a high withstand voltage MOSFET, if the device is used for a long time, ions outside the package or in the resin may be changed to a high withstand voltage MOS by an applied voltage.
When reaching the gate of the FET, there may be a problem that the threshold value of the gate voltage fluctuates or a channel leak occurs. As a countermeasure, there are methods such as changing the resin or modification or shape of the package, or changing the device to a structure in which ions do not easily enter the gate, but these methods have limitations. The present invention has been made in view of such circumstances, and an object of the present invention is to prevent a switching element from causing erroneous firing even when a ground potential and a fluctuating potential are mixed, and to reduce a chip area. It is an object of the present invention to provide a high breakdown voltage semiconductor device.

[0023]

In order to solve the above-mentioned problems, the present invention relates to a GN which uses a GND level as a reference of potential.
In a semiconductor device having a D reference circuit and a floating reference circuit based on a potential relatively higher than a GND level, the GND reference circuit and the floating reference circuit are formed on different semiconductor substrates. is there.

According to such a configuration, the floating reference circuit and the GND reference circuit are formed on separate semiconductor substrates, so that their positional relationship can be freely set, and a wiring excellent in noise can be provided. Circuit design becomes easy, for example, wiring can be performed. For example, floating reference circuit and GN
It is also possible to shorten a wiring interval to a connection circuit such as a gate of each power device (for example, IGBT) constituting an inverter connected from each of the D reference circuits,
It is possible to reduce the parasitic inductance of the wiring and reduce the size.

Further, the present invention is characterized in that the GND reference circuit and the floating reference circuit are connected via a level shift circuit.

According to such a configuration, the level shift circuit shifts the potential levels of the GND reference circuit and the floating reference circuit, and facilitates transmission of each signal.

Further, in the semiconductor device according to the present invention,
The level shift circuit includes an Nch MOSFET and the Nc MOSFET.
h MOSFET connected to a drain of the first MOSFET, and the Nch MOSFET is connected to the GND.
The first resistor is formed on the same semiconductor substrate as the reference circuit, and the first resistor has a level-up circuit formed on the same semiconductor substrate as the floating reference circuit.

According to such a level shift circuit, the level of the GND reference can be converted to the floating reference potential level which is relatively higher than the ground reference by the level up circuit. The substrate can be easily separated from the floating reference circuit.

Further, in the semiconductor device according to the present invention,
The level shift circuit includes a Pch MOSFET and the Pc MOSFET.
h MOSFET is formed on the same semiconductor substrate as the floating reference circuit, and the second resistor is formed on the same semiconductor substrate as the GND reference circuit. It has a level down circuit formed on a substrate.

According to such a level shift circuit, the floating reference level can be converted to the GND reference potential level, which is relatively lower than the floating reference, by the level down circuit. The substrate can be easily separated from the reference circuit.

In the semiconductor device according to the present invention,
The level shift circuit includes a Pch MOSFET and the Pc MOSFET.
h PMOSFET and a third resistor connected to the drain of the MOSFET, wherein the Pch MOSFET and the third resistor both have a level down circuit formed on the same semiconductor substrate as the GND reference circuit. It is a feature.

According to such a configuration, the Pch MOSFET formed in the GND reference circuit may have a withstand voltage structure, and the entire floating reference circuit and the PchM formed therein may be used.
A double withstand voltage structure in which the OSFET has a high withstand voltage structure is not required, and the chip size can be reduced.

Further, in the semiconductor device according to the present invention,
The floating reference circuit is for driving a gate of a switching device connected to a high potential side among switching devices at least two of which are connected in series between a high potential side and a ground side of a power supply. A floating reference gate drive circuit, wherein the GND reference circuit is a GND reference control circuit that supplies or receives a signal to or from the floating reference gate drive circuit;
A GND reference gate drive circuit for driving a gate of a switching device connected to a low potential side among at least two switching devices connected in series between a high potential side and a ground side of a power supply is provided. The switching devices are provided near gates of the respective switching devices.

According to such a configuration, the wiring distance from each of the floating reference gate drive circuit and the GND reference gate drive circuit to the gate of the switching device can be reduced, and the parasitic inductance of the wiring can be reduced. It is possible to reduce switching malfunctions and the like caused by this.

Also, the semiconductor device according to the present invention is a semiconductor device for controlling at least two switching devices connected in series between different potentials, wherein a gate drive circuit for turning on / off the switching device; A control circuit for controlling the gate drive circuit,
The invention is characterized in that the gate drive circuit and the control circuit are formed on different semiconductor substrates.

According to such a configuration, the gate drive circuit and the control circuit can have a separated structure, so that the degree of freedom in circuit wiring design is increased.

Further, in the semiconductor device according to the present invention,
The level shift circuit includes an NPN bipolar transistor and a fourth resistor connected to a collector of the NPN bipolar transistor. The NPN bipolar transistor is formed on the same semiconductor substrate as the GND reference circuit. The fourth resistor has a level-up circuit formed on the same semiconductor substrate as the floating reference circuit.

According to such a level-up circuit, the level-up circuit can convert a GND reference level to a floating reference potential level that is relatively higher than the ground reference. The board can be easily separated from the floating reference circuit.
The problem of long-term reliability, such as a change in the threshold value of the gate and a resulting channel leak, as seen in S, can be solved.

Further, in the semiconductor device according to the present invention,
The level shift circuit includes a PNP bipolar transistor and a fifth resistor connected to the PNP bipolar transistor. The PNP bipolar transistor is formed on the same semiconductor substrate as the floating reference circuit. Is characterized by having a level-down circuit formed on the same semiconductor substrate as the GND reference circuit.

According to such a level shift circuit, the floating reference level can be converted to the GND reference potential level, which is relatively lower than the floating reference, by the level down circuit. In addition to easily separating the substrate from the reference circuit, it is also possible to eliminate long-term reliability problems such as fluctuations in the gate threshold voltage and the accompanying channel leakage, which are observed in MOS.

Further, in the semiconductor device according to the present invention,
The level shift circuit includes a PNP bipolar transistor and a sixth resistor connected to the collector of the PNP bipolar transistor. The PNP bipolar transistor and the sixth resistor are the same as the GND reference circuit. And a level down circuit formed on the semiconductor substrate.

According to such a configuration, the PNP bipolar transistor withstand voltage structure formed in the GND reference circuit may be formed, and the entire floating reference circuit and the PNP bipolar transistor formed therein have a high withstand voltage structure. A heavy withstand voltage structure is not required, and the chip size can be reduced. In addition, long-term reliability problems such as fluctuations in gate threshold voltage and associated channel leakage, which are observed in MOS, can be solved.

Further, the semiconductor device according to the present invention has a switching device connected to the high potential side among at least two switching devices connected in series between the high potential side and the ground side of the power supply. Reference gate drive for driving the gate of the switching device and G for driving the gate of the switching device connected to the low potential side.
It comprises an ND reference gate drive circuit and a GND reference control circuit for controlling these gate drive circuits. Among them, the floating reference circuit is the floating reference gate drive circuit, and the GND reference circuit is the GND reference control circuit.

According to such a configuration, the floating reference gate drive circuit and the GND reference gate drive circuit are
Since the floating reference gate drive circuit and the ND control circuit can be formed on different semiconductor substrates respectively,
The ND reference gate drive circuit can be installed near the gate of each of the switching devices, and the wiring distance from each of the floating reference gate drive circuit and the GND reference gate drive circuit to the gate of the switching device can be shortened. The parasitic inductance of the wiring can be reduced, and switching malfunction and the like due to the parasitic inductance can be reduced.

Further, according to such a configuration, the floating reference gate drive circuit, the GND reference gate drive circuit, and the GND reference control circuit can have a separated structure, so that the degree of freedom in circuit wiring design increases, and It is easy to reduce the size of the device by optimizing the circuit configuration.

[0046]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings used in the embodiments of the present invention, the same parts as those in the drawings used in the prior art are denoted by the same reference numerals.

Embodiment 1 First, a first embodiment of the present invention will be described. FIG. 1 is a schematic diagram showing a main part of the level shift circuit according to the first embodiment of the present invention. The first embodiment in FIG. 1 differs from the prior art in FIG. 11 in that the GND reference circuit 3 and the floating reference circuit 4 are formed on different substrates. That is, in FIG. 1, the GND reference circuit 3 is formed on the A substrate 2a, and the floating reference circuit 4 is formed on the B substrate 2b.

The level-up circuit shown in FIG. 9 is formed in FIG. 1 with a high breakdown voltage Nch MOSFET 5 formed in the GND reference circuit 3 on the A substrate 2a and in the floating reference circuit 4 on the B substrate 2b. And a level shift resistor 6. The drain of the high breakdown voltage Nch MOSFET 5 and the level shift resistor 6 are electrically connected by wiring such as wire bonding. It should be noted that the high withstand voltage Nch MOSFE formed in the GND reference circuit 3 of the A substrate 2a.
The drain portion of T5 is surrounded by HVJT10 'and GND
The structure is such that the breakdown voltage is maintained with respect to the reference circuit 3.

On the other hand, in the level down circuit shown in FIG. 10, the high breakdown voltage Pch MOSFET 7 formed in the floating reference circuit 4 of the B substrate 2b and the A substrate 2a in FIG.
Level shift resistor 8 formed in the GND reference circuit 3 of FIG.
And is constituted by. This high voltage Pch MOSF
The drain of the ET 7 and the level shift resistor 8 are electrically connected by a wire such as a wire bond. The floating reference circuit 4 is surrounded by HVJT 9 and is electrically insulated from the potential of the B substrate 2b itself. Further, the drain of the high breakdown voltage Pch MOSFET 7 formed in the floating reference circuit 4 is connected to the floating reference circuit 4 through the HVJT 10.
The structure is such that the pressure resistance is maintained.

FIG. 2 is a circuit diagram of the level shift circuit shown in FIG.
FIG. 3 is a structural view of A ′ section. That is, this figure is a specific cross-sectional structure of the level down circuit using the self-isolation structure according to the first embodiment.
4 shows a cross-sectional structure of a level down circuit portion using ET. In FIG. 2, GND is provided on the A substrate 2a of the semiconductor substrate.
A region of the reference circuit 3 is formed, and a B substrate 2b of a semiconductor substrate is formed.
Is formed with a region of the floating reference circuit 4. And
In the area of the GND reference circuit 3, a level shift resistor 8 is formed. In the region of the floating reference circuit 4, the portion of the drain D is surrounded by HVJT10, and the outer periphery is further surrounded by HVJT9. And the floating reference circuit 4
The aluminum wiring is drawn out from the drain D, the source S, and the gate G, and the wiring is drawn out from the level shift resistor 8 of the GND reference circuit 3 by wire bonding or the like, and predetermined connections are made.

The structure of the HVJT is such that an N ⁻ region 22 is formed on the surface of a P ⁻ substrate 21, a high breakdown voltage portion is separated by using a reverse bias of a PN junction, and a junction at a P ⁻ / N ⁻ junction is formed. A P ^- region 23 is formed on the surface of the N ^- region 22 in order to alleviate the electric field at the curvature portion of
It adopted a Double RESURF structure based on the principle, P ^- / N ^-
It has withstand voltage structures HVJT9 and HVJT10 for improving the withstand voltage to near the junction withstand voltage of the parallel plate at the junction.

That is, the high breakdown voltage Pch MOSFET 7 forming the level down circuit is formed in the floating reference circuit 4 surrounded by the HVJT 9, and the drain D portion is further surrounded by the internal HVJT 10. Therefore, high withstand voltage P
The drain D portion of the ch MOSFET 7 is connected to the HVJT 9 of the floating reference circuit 4 and the HV of the high withstand voltage Pch MOSFET itself.
JT10 has a double pressure-resistant structure. The level shift resistor 8 is formed on the same substrate 2a as the GND reference circuit 3, and is electrically connected to the drain D of the high-breakdown-voltage Pch MOSFET by a wire or the like.

FIG. 3 is a block diagram showing the internal configuration of the HVIC according to the first embodiment of the present invention. Note that, for simplification, only one arm of an externally connected inverter circuit (not shown) is shown in FIG. In FIG. 1, an HVIC 11 includes a control circuit 12, a floating reference gate drive circuit 13, and a GND reference gate drive circuit 1.
4, the level-up circuit 15 and the level-down circuit 16 are the same as in the prior art. The respective operations are the same as those in the prior art.

The feature of this embodiment is that the floating reference gate drive circuit 13 and the GND reference gate drive circuit 14 are separated as ICs on a substrate different from the control circuit 12 and are arranged near the IGBTs to be driven. That is. That is, the control circuit 12 is formed on the A substrate 2a,
The floating reference gate drive circuit 13 is formed on the B substrate 2b,
The GND reference gate drive circuit 14 is formed on the C substrate 2c. Further, the level-up circuit 15 includes the A substrate 2a
And the B substrate 2b. That is, the level-up circuit 15 includes the same A substrate 2 as the control circuit 12.
A high voltage Nch MOSFET 5 is formed in a, and a level shift resistor 6 is formed separately on the same B substrate 2b as the floating reference gate circuit 13, and both are connected by wiring.

Similarly, the level down circuit 16 has the same A substrate 2a and floating reference gate circuit 1 as the control circuit 12.
3 are formed separately on the same B substrate 2b. That is, the high breakdown voltage Pch MO constituting the level down circuit 16
The SFET 7 is formed on the same B substrate 2b as the floating reference gate drive circuit 13, and the level shift resistor 8 is connected to the control circuit 1
2 are formed on the same A substrate 2a and are connected by wire wiring.

The B substrate 2b which forms the floating reference gate drive circuit 13 is disposed near the high potential side IGBT 17a, and the floating reference gate drive circuit 13 and the high potential side I
The C substrate 2c that reduces the distance of the GBT 17a and forms the GND reference gate drive circuit 14 is the low potential side IGBT 1
7b, the GND reference gate drive circuit 1
4 and the low-potential-side IGBT 17b, the parasitic inductance of each wiring can be reduced.

As a result, due to dv / dt generated at the time of commutation between the high-potential side IGBT 17a and the low-potential side IGBT 17b, even if a mutated current flows through the parasitic capacitances 18a and 18b of each IGBT, the parasitic inductances 20a and 20b are reduced. Since it is small, the back electromotive force of L · di (t) / dt generated in both parasitic inductances 20a and 20b can be reduced. That is, the back electromotive force causes IG
There is no possibility that a voltage higher than the threshold value is applied to the gate of the BT, and either the IGBT 17a or the IGBT 17b is erroneously fired and the one-arm IGBTs 17a and 17b connected between Vcc and GND are short-circuited. No more.

Embodiment 2 Next, a second embodiment of the present invention will be described. FIG. 4 is a schematic diagram showing a main part of a level shift circuit according to the second embodiment of the present invention.
That is, in the second embodiment in FIG.
The point that the reference circuit 35 and the floating reference circuit 34 are formed on different substrates is the same as that of the first embodiment shown in FIG.
7 is not provided and the HVJ surrounding the floating reference circuit 34 is not provided.
The difference from FIG. 1 is that T is not provided.

That is, the GND reference circuit 35 is formed on the A board 32a, and the floating reference circuit 34 is formed on the B board 32b.
Are formed. The level-up circuit shown in FIG. 9 is a high-voltage Nch MOSFET 5 formed in the GND reference circuit 35 of the A substrate 32a in FIG.
And a level shift resistor 6 formed in the floating reference circuit 34 of the B substrate 32b. The drain of the high voltage Nch MOSFET 5 and the level shift resistor 6 are electrically connected by wiring.

On the other hand, in the level down circuit shown in FIG. 10, in FIG. 4, both the high breakdown voltage Pch MOSFET 7 and the level shift resistor 8 are formed in the GND reference circuit 35 of the A substrate 32a. And this high breakdown voltage Pch
The MOSFET 7 is electrically connected to a floating reference circuit 34 formed on the B substrate 32b through wiring from each of a source and a gate. In the case of the structure according to the second embodiment, since the high breakdown voltage Pch MOSFET 7 is not formed in the floating reference circuit 34 of the B substrate 32b,
It is not necessary to ground the potential of the substrate of the floating reference circuit 34 itself. Therefore, it is not necessary to surround the floating reference circuit 34 with HVJT. Therefore, the potential of the substrate itself of the floating reference circuit 34 can be used as the floating potential reference. For this reason, the HVJT 10 ′ surrounding the drain of the high withstand voltage Nch MOSFET 5 formed in the GND reference circuit 35 and the high withstand voltage Pch MOSFET
Only the HVJT 10 around the source and gate 7 need be formed.

FIG. 5 is a circuit diagram of the level shift circuit of FIG.
FIG. 3 is a structural view of A ′ section. That is, this figure shows an example of a level-down circuit using a self-isolation structure as a specific cross-sectional structure, and shows a cross-sectional structure of a level-down circuit portion using a high-breakdown-voltage Pch MOSFET 7. In FIG. 5, only the A substrate 32a forming the GND reference circuit 35 of FIG. 4 is shown, and the floating reference circuit 34 formed on the B substrate 32b is omitted. In addition, high breakdown voltage Pch
The source and gate of MOSFET7 are HVJ
The HVJT is surrounded by T10, and the breakdown voltage structure of each HVJT is as described above.

High voltage Pch constituting a level down circuit
The MOSFET 7 and the level shift resistor 8 are formed on the same A substrate 32a as the GND reference circuit 35, and have a high breakdown voltage Pch
The MOSFET 7 is surrounded by the HVJT 10, and its source S and gate G electrodes are electrically connected via wiring to a floating reference circuit 34 formed on the B substrate 32b.
The level shift resistor 8 has one terminal grounded to GND, and the other terminal electrically connected to the drain of the high-breakdown-voltage Pch MOSFET 7. The level shift resistor 8 and the drain D are connected by a wiring.

FIG. 6 is a block diagram showing the internal configuration of the HVIC according to the second embodiment of the present invention. In the figure, for the sake of simplicity, only one arm of the externally connected inverter circuit is shown. In FIG.
The IC 11 includes a control circuit 12 and a floating reference gate drive circuit 1
3 and a GND reference gate drive circuit 14, a level up circuit 15, and a level down circuit 16 are the same as those in the first embodiment shown in FIG. The respective operations are the same as those in the prior art.

In this embodiment, as in the first embodiment, the floating reference gate drive circuit 13 and the GND reference gate drive circuit 14
And arranged near the IGBTs to be driven. In other words, the control circuit 12
a, and the floating reference gate drive circuit 13 is
2b, and the GND reference gate drive circuit 14 is formed on the C substrate 2c.

Further, the level-up circuit 15 is formed separately for the A substrate 32a and the B substrate 32b. In other words, the level-up circuit 15 has the same high-voltage Nch MOSFET 5 formed on the same A substrate 32 a as the control circuit 12, and has the same B substrate 32 b
The level shift resistor 6 is formed separately, and both are connected by wiring. On the other hand, in the level-down circuit 16, the high-breakdown-voltage Pch MOSFET 7 and the level shift resistor 8 are both formed on the same A substrate 32a as the control circuit 12, and the floating reference gate is connected from the source and the drain of the high-breakdown-voltage Pch MOSFET 7 by wire wiring or the like. It is electrically connected to the drive circuit 13. That is, the A substrate 32a and the B substrate 32b
Is a high withstand voltage Nch M
The drain of the OSFET 5 and the source and gate of the high-breakdown-voltage Pch MOSFET 7 constituting the level-down circuit 16 are connected to each other.

In the case of the second embodiment, such a configuration makes it possible to arrange the floating reference gate drive circuit 13 and the GND reference gate drive circuit 14 near the IGBTs 17a and 17b. Therefore, each IGBT1
The effect of inductance due to wiring between the gates 7a and 17b and the floating reference potential can be reduced. Further, the configuration of the HVIC having the withstand voltage structure is the same as the control circuit 1
2, the level up circuit 15 and the level down circuit 16 only need to be provided on the A substrate 32a, and it is not necessary to surround the entire floating reference circuit 34 with HVJT, so that the area of the entire substrate is smaller than that of the first embodiment. Can be further reduced.

According to this embodiment, the reduction ratio of the chip size of the floating reference circuit is approximately 20 in the 600 V withstand voltage class.
The size can be reduced by about 40%, and the size can be reduced by about 30% to 50% in the 1200V breakdown voltage class, so that the cost of the control IC can be greatly reduced by reducing the material cost and improving the yield. Can contribute.

Embodiment 3 A third embodiment of the present invention will be described. FIG. 13 is a schematic diagram showing a main part of a level shift circuit according to the third embodiment of the present invention. The basic configuration is almost the same as that of the first embodiment of the present invention. The third embodiment in FIG. 13 corresponds to the first embodiment in FIG.
The difference from this embodiment is that a high breakdown voltage bipolar transistor is used instead of the high breakdown voltage MOSFET. That is, in FIG. 13, a high breakdown voltage NPN bipolar transistor is used instead of the high breakdown voltage Nch MOSFET as the level up circuit, and a high breakdown voltage PNP bipolar transistor is used instead of the high breakdown voltage Pch MOSFET as the level down circuit. is there.

FIG. 19 is an example of a specific circuit diagram of the level up circuit. That is, a level shift resistor is connected to the collector side of the high breakdown voltage NPN bipolar transistor. When the base of the high-breakdown-voltage NPN bipolar transistor is biased with respect to the emitter electrode to a positive potential equal to or higher than the threshold, the high-breakdown-voltage NPN bipolar transistor is turned on, a current flows through the level shift resistor, and a signal voltage is generated. Outputs more signals.

Here, the resistor 42 is a resistor for limiting the base current, and may be omitted. Further, the resistor 43 is a resistor for improving the constant current property by applying feedback to the high breakdown voltage NPN bipolar transistor and for limiting the base current, and may be omitted. FIG. 20 is an example of a specific circuit of the level down circuit. That is, the high withstand voltage P
The configuration is such that a level shift resistor is connected to the collector side of the NP bipolar transistor. The base of the high breakdown voltage PNP bipolar transistor with respect to the emitter electrode
When biased to a negative potential higher than the threshold value,
The bipolar transistor is turned on, a current flows through the level shift resistor to generate a signal voltage, and a signal is output from OUT1.

Here, the resistor 44 is a resistor for limiting the base current, and may be omitted. Further, the resistor 45 is a resistor for feeding back the high voltage PNP bipolar transistor to improve the constant current property and for limiting the base current, and may be omitted. The third embodiment shown in FIG. 13 differs from the prior art shown in FIG. 11 in that the GND reference circuit 3 and the floating reference circuit 4 are formed on different substrates. That is, in FIG. 13, the GND reference circuit 3 is formed on the A substrate 2a, and the floating reference circuit 4 is formed on the B substrate 2b.

The level-up circuit shown in FIG.
3, a high-voltage NPN bipolar transistor 5 formed in the GND reference circuit 3 of the A substrate 2a and a level shift resistor 6 formed in the floating reference circuit 4 of the B substrate 2b. The collector of this high breakdown voltage NPN bipolar transistor 5 and the level shift resistor 6
Are electrically connected by a wire such as a wire bond. The collector of the high voltage NPN bipolar transistor 5 formed in the GND reference circuit 3 of the A substrate 2a is surrounded by the HVJT 10 ', and has a structure in which the withstand voltage is maintained with respect to the GND reference circuit 3.

On the other hand, the level down circuit shown in FIG. 20 corresponds to the high breakdown voltage PNP bipolar transistor 7 formed in the floating reference circuit 4 of the B substrate 2b in FIG.
And a level shift resistor 8 formed in the GND reference circuit 3 of the A substrate 2a. The collector of the high breakdown voltage PNP bipolar transistor 7 and the level shift resistor 8 are electrically connected by wiring such as wire bonds. The floating reference circuit 4 is surrounded by HVJT 9 and is electrically insulated from the potential of the B substrate 2b itself. Further, the collector of the high breakdown voltage PNP bipolar transistor 7 formed in the floating reference circuit 4 is H
The structure is such that the breakdown voltage is maintained with respect to the floating reference circuit 4 via the VJT 10.

FIG. 14 shows A of the level shift circuit of FIG.
FIG. 4 is a structural view of a section taken along a line −A ′. That is, FIG.
10 shows a specific cross-sectional structure of the level-down circuit using the self-isolation structure in the embodiment, and shows a cross-sectional structure of a level-down circuit using a high breakdown voltage PNP bipolar transistor. In FIG. 14, a region of the GND reference circuit 3 is formed on the A substrate 2a of the semiconductor substrate, and a region of the floating reference circuit 4 is formed on the B substrate 2b of the semiconductor substrate. The level shift resistor 8 is formed in the area of the GND reference circuit 3. In the area of the floating reference circuit 4, the collector C is surrounded by HVJT10, and the outer periphery is further surrounded by HVJT9. Then, the aluminum wiring is drawn out from the collector C, the emitter E, and the base B of the floating reference circuit 4, and the wiring is drawn out from the level shift resistor 8 of the GND reference circuit 3 by wire bonding or the like. Have been done.

In the HVJT structure, an N ⁻ region 22 is formed on the surface of a P ⁻ substrate 21, a high breakdown voltage portion is separated by using a reverse bias of a PN junction, and a junction of a P ⁻ / N ⁻ junction is further separated. In order to alleviate the electric field at the curvature, the N ⁻ region 2
So-called RESU in which a P ^- region 23 is formed on the surface of
Adopted the Double RESURF structure based on RF principle, ^{P -} / N - has a breakdown voltage structure HVJT9,10 for improving the breakdown voltage to near the junction withstand voltage of the parallel plate of the junction.

That is, the high breakdown voltage PNP bipolar transistor 7 forming the level down circuit is formed in the floating reference circuit 4 surrounded by the HVJT 9 and its collector C
The part is further surrounded by an internal HVJT 10. Therefore, the collector C portion of the high voltage PNP bipolar transistor 7 is connected to the HVJT 9 of the floating reference circuit 4 and the high voltage PNP.
The HVJT 10 of the bipolar transistor itself has a double withstand voltage structure. The level shift resistor 8 is formed on the same substrate 2a as the GND reference circuit 3 and has a collector C of a high breakdown voltage PNP bipolar transistor.
And are electrically connected by wire wiring or the like.

FIG. 15 is a block diagram showing the internal structure of the HVIC according to the third embodiment of the present invention. still,
In the figure, for the sake of simplicity, only one arm of an externally connected inverter circuit (not shown) is shown. In FIG. 1, an HVIC 11 includes a control circuit 12, a floating reference gate drive circuit 13, and a GND reference gate drive circuit 1.
4, the level-up circuit 15 and the level-down circuit 16 are the same as in the prior art.

The feature of this embodiment is that the floating reference gate drive circuit 13 and the GND reference gate drive circuit 14 are separated as ICs on a substrate different from the control circuit 12 and are arranged near the IGBTs to be driven. That is. That is, the control circuit 12 is formed on the A substrate 2a,
The floating reference gate drive circuit 13 is formed on the B substrate 2b,
The GND reference gate drive circuit 14 is formed on the C substrate 2c. Further, the level-up circuit 15 includes the A substrate 2a
And the B substrate 2b. That is, the level-up circuit 15 includes the same A substrate 2 as the control circuit 12.
A high voltage NPN bipolar transistor 5 is formed in a, and a level shift 6 resistor is formed separately on the same B substrate 2b as the floating reference gate drive circuit 13, and both are connected by wiring.

Similarly, the level down circuit 16 is also formed separately on the same A substrate 2a as the control circuit 12 and the same B substrate 2b as the floating reference gate drive circuit 13. That is, the high breakdown voltage PNP constituting the level down circuit 16
Bipolar transistor 7 is floating reference gate drive circuit 1
3, the level shift resistor 8 is formed on the same A substrate 2a as the control circuit 12, and is connected by wire wiring.

The B substrate 2b forming the floating reference gate drive circuit 13 is arranged near the high potential side IGBT 17a, and the floating reference gate drive circuit 13 and the high potential side I
The C substrate 2c that reduces the distance of the GBT 17a and forms the GND reference gate drive circuit 14 is the low potential side IGBT 1
7b, the GND reference gate drive circuit 1
4 and the low-potential-side IGBT 17b, the parasitic inductance of each wiring can be reduced.

As a result, dv / d generated at the time of commutation between the high potential side IGBT 17a and the low potential side IGBT 17b
t, the parasitic inductances 20a, 20b, 20c, 20c, even if the mutated current flows through the parasitic capacitances 18a, 18b of each IGBT.
b is small, each parasitic inductance 20a, 20b
Back-electromotive force of L · di (t) / dt generated at both ends of the. That is, there is no possibility that a voltage higher than the threshold value is applied to the gate of the IGBT due to the back electromotive force, and the IGBT 17a or IGBT 17b
IGBTs 17a and 17b of one arm connected between Vcc and GND are not short-circuited.

Furthermore, in this embodiment, since a high-breakdown-voltage bipolar transistor is used instead of a high-breakdown-voltage MOSFET for the level shifter, there is a problem of long-term reliability such as fluctuation of a gate threshold value and accompanying channel leak. Can be eliminated.

Embodiment 4 A fourth embodiment of the present invention will be described. FIG. 16 is a schematic diagram showing a main part of a level shift circuit according to the fourth embodiment of the present invention. The basic configuration is almost the same as the second embodiment of the present invention. The difference between the fourth embodiment in FIG. 16 and the second embodiment in FIG.
Instead of using a high breakdown voltage bipolar transistor. That is, in FIG. 16, a high-breakdown-voltage NPN bipolar transistor is used instead of the high-breakdown-voltage Nch MOSFET as a level-up circuit, and a high-breakdown-voltage PNP bipolar transistor is used instead of the high-breakdown-voltage Pch MOSFET as a level-down circuit. is there.

That is, the GND reference circuit 35 is formed on the A board 32a, and the floating reference circuit 34 is formed on the B board 32b.
Are formed. The level up circuit shown in FIG. 19 is formed in the high voltage NPN bipolar transistor 5 formed in the GND reference circuit 35 of the A substrate 32a and the floating reference circuit 34 of the B substrate 32b in FIG. And a level shift resistor 6. The collector of the high breakdown voltage NPN bipolar transistor 5 and the level shift resistor 6 are electrically connected by wiring.

On the other hand, in the level down circuit shown in FIG. 20, in FIG. 16, both the high breakdown voltage PNP bipolar transistor 7 and the level shift resistor 8 are formed in the GND reference circuit 35 of the A substrate 32a. The high-breakdown-voltage PNP bipolar transistor 7 is electrically connected to a floating reference circuit 34 formed on the B substrate 32b via wiring from each of an emitter and a base. In the case of the structure according to the fourth embodiment, the B substrate 3
Since the high voltage PNP bipolar transistor 7 is not formed in the floating reference circuit 34 of FIG.
It is not necessary to ground the potential of the substrate itself. Therefore,
There is no need to surround the floating reference circuit 34 with HVJT. Therefore, the potential of the substrate itself of the floating reference circuit 34 can be used as the floating potential reference. For this reason, the high withstand voltage N formed in the GND reference circuit 35 is used as the withstand voltage structure.
Only the HVJT 10 'surrounding the collector of the PN bipolar transistor 5 and the HVJT 10 surrounding the emitter and base of the high breakdown voltage PNP bipolar transistor 7 need be formed.

FIG. 17 shows A of the level shift circuit of FIG.
FIG. 4 is a structural view of a section taken along a line −A ′. That is, this figure shows an example of a level-down circuit using a self-isolation structure as a specific cross-sectional structure, and shows a cross-sectional structure of a level-down circuit using a high-breakdown-voltage PNP bipolar transistor 7. In FIG. 17, only the A substrate 32a forming the GND reference circuit 35 of FIG. 16 is shown, and the floating reference circuit 34 formed on the B substrate 32b is omitted. The emitter and base of the high-breakdown-voltage PNP bipolar transistor 7 are surrounded by the HVJT 10, and the breakdown voltage structure of each HVJT is as described above.

High Voltage PNP Constituting Level Down Circuit
The bipolar transistor 7 and the level shift resistor 8
Formed on the same A substrate 32a as the ND reference circuit 35,
The high withstand voltage PNP bipolar transistor 7 is HVJT1
The electrodes of the emitter E and the base B are electrically connected to a floating reference circuit 34 formed on the B substrate 32b via wiring. The level shift resistor 8
Has one terminal grounded to GND and the other terminal electrically connected to the collector of the high voltage PNP bipolar transistor 7. The level shift resistor 8 and the collector C are connected by a wiring.

FIG. 18 is a block diagram showing the internal structure of the HVIC according to the fourth embodiment of the present invention. still,
In the figure, for simplification, only one arm of an externally connected inverter circuit is shown. In FIG.
The VIC 11 includes a control circuit 12, a floating reference gate drive circuit 13, a GND reference gate drive circuit 14, a level up circuit 15, and a level down circuit 16, which are the same as the third embodiment of FIG. The respective operations are the same as those in the prior art.

In this embodiment, as in the third embodiment, the floating reference gate drive circuit 13 and the GND reference gate drive circuit 14
And arranged near the IGBTs to be driven. In other words, the control circuit 12
a, and the floating reference gate drive circuit 13 is
2b, and the GND reference gate drive circuit 14 is formed on the C substrate 2c.

Further, the level-up circuit 15 is formed separately for the A substrate 32a and the B substrate 32b. That is, the level-up circuit 15 includes the high-breakdown-voltage NPN bipolar transistor 5 on the same A substrate 32 a as the control circuit 12.
Are formed, and the level shift resistor 6 is formed separately on the same B substrate 32b as the floating reference gate drive circuit 13, and both are connected by wiring. On the other hand, the level down circuit 16
The high voltage PNP bipolar transistor 7 and the level shift resistor 8 are both formed on the same A substrate 32a as the control circuit 12, and the floating reference gate is driven from the base and the emitter of the high voltage PNP bipolar transistor 7 by wire wiring or the like. It is electrically connected to the circuit 13. That is, the A substrate 32a and the B substrate 32b connect the collector wiring of the high breakdown voltage NPN bipolar transistor 5 forming the level up circuit 15 and the wiring of the emitter and base of the high breakdown voltage PNP bipolar transistor 7 forming the level down circuit 16. Connected through.

In the case of the fourth embodiment, such a configuration makes it possible to arrange the floating reference gate drive circuit 13 and the GND reference gate drive circuit 14 near the IGBTs 17a and 17b. Therefore, each IGBT 17
It is possible to reduce the influence of inductance due to the wiring between the gates a and 17b and the floating reference potential. Further, the configuration of the HVIC having the breakdown voltage structure is the same as that of the control circuit 12.
And only the A substrate 32a composed of the level-up circuit 15 and the level-down circuit 16 suffices, and there is no need to surround the entire floating reference circuit 34 with HVJT. Therefore, the area of the entire substrate is smaller than that of the first embodiment. Can be further reduced.

According to the present embodiment, the reduction ratio of the chip size of the floating reference circuit is approximately 20 in the 600 V breakdown voltage class.
The size can be reduced by about 40%, and the size can be reduced by about 30% to 50% in the 1200V breakdown voltage class, so that the cost of the control IC can be greatly reduced by reducing the material cost and improving the yield. Can contribute. Further, in the case of this embodiment, since a high-breakdown-voltage bipolar transistor is used instead of a high-breakdown-voltage MOSFET for the level shifter, a problem of long-term reliability such as fluctuation of a gate threshold value and associated channel leak can be solved. .

[0093]

As described above, according to the control IC as the semiconductor device of the present invention, the floating reference gate drive circuit and the GND reference gate drive circuit can be installed near the IGBT. Therefore, each gate drive circuit and each I
The wire wiring for connecting to the GBT can be shortened as compared with the related art, and the parasitic inductance due to the wiring can be reduced. Therefore, even if a displacement current flows through the parasitic capacitance between the collector and the gate of the IGBT due to the commutation phenomenon of the two IGBTs, the back electromotive force of the parasitic inductance caused by the displacement current can be reduced, and the IGBT of the IGBT can be reduced. Malfunction can be prevented. Also,
According to the semiconductor device of the present invention, it is not necessary to surround the periphery of the floating reference circuit with the withstand voltage structure (HVJT), so that the chip size of the floating reference circuit can be reduced, and the cost of the product can be reduced. it can. Further, according to the semiconductor device of the present invention, the level shifter is provided with a high withstand voltage MOSFET.
Since a high-withstand-voltage bipolar transistor is used without using a transistor, the problem of long-term reliability, such as a change in gate threshold voltage and a resulting channel leak, can be solved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a main part of a level shift circuit according to a first embodiment of the present invention.

FIG. 2 is a structural diagram of an AA ′ section of the level shift circuit of FIG. 1;

FIG. 3 is a block diagram showing an internal configuration of the HVIC according to the first embodiment of the present invention.

FIG. 4 is a schematic diagram of a main part of a level shift circuit according to a second embodiment of the present invention.

FIG. 5 is a structural diagram of an AA ′ section of the level shift circuit of FIG. 4;

FIG. 6 is a block diagram showing an internal configuration of an HVIC according to a second embodiment of the present invention.

FIG. 7 is a circuit configuration diagram of a main circuit portion of the motor control inverter.

FIG. 8 is a block diagram showing an internal configuration of the conventional HVIC used in FIG.

FIG. 9 is an example of a specific circuit diagram of a level-up circuit.

FIG. 10 is an example of a specific circuit diagram of a level down circuit.

FIG. 11 is a schematic diagram of a main part when a conventional level shift circuit is formed on a semiconductor substrate.

FIG. 12 is a structural diagram of an AA ′ section of the level shift circuit of FIG. 11;

FIG. 13 is a schematic diagram of a main part of a level shift circuit according to a third embodiment of the present invention.

FIG. 14 is a structural diagram of an AA ′ section of the level shift circuit of FIG. 13;

FIG. 15 shows an HVIC according to a third embodiment of the present invention.
FIG. 2 is a block diagram showing an internal configuration of the device.

FIG. 16 is a schematic diagram of a main part of a level shift circuit according to a fourth embodiment of the present invention.

FIG. 17 is a structural view of the level shift circuit of FIG. 16 taken along the line AA ′;

FIG. 18 shows an HVIC according to a fourth embodiment of the present invention.
FIG. 2 is a block diagram showing an internal configuration of the device.

FIG. 19 is an example of a specific circuit diagram of a level-up circuit using a high breakdown voltage NPN bipolar transistor.

FIG. 20 is an example of a specific circuit diagram of a level down circuit using a high breakdown voltage PNP bipolar transistor.

[Explanation of symbols]

Reference Signs List 1 substrate 2a, 32a A substrate 2b, 32b B substrate 2c C substrate 3, 33 GND reference circuit 4, 34 Floating reference circuit 5 High voltage Nch MOSFET 6, 8 level shift resistor 7 High voltage Pch MOSFET 9, 10, 10 'HVJT (High breakdown voltage termination junction structure) 11 HVIC 12 Control circuit 13 Floating reference gate drive circuit 14 GND reference gate drive circuit 15 Level up circuit 16 Level down circuit 17a High potential side IGBT 17b Low potential side IGBT 18a, 18b Parasitic capacitance 19a High potential Side feedback diode 19b Low-potential-side feedback diode 20a High-potential-side parasitic inductance 20b Low-potential-side parasitic inductance 21, 31 P ^- substrate 22, 32 N ^- region 23, 33 P ^- region

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (13)

[Claims] 1. A GND which uses a GND level as a reference of potential
A semiconductor device having a reference circuit and a floating reference circuit based on a potential relatively higher than a GND level, wherein the GND reference circuit and the floating reference circuit are formed on different semiconductor substrates. 2. The semiconductor device according to claim 1, wherein said GND reference circuit and said floating reference circuit are connected via a level shift circuit. 3. The semiconductor device according to claim 2, wherein said level shift circuit includes an Nch MOSFET and said Nc MOSFET.
h MOSFET connected to a drain of the first MOSFET, and the Nch MOSFET is connected to the GND.
A semiconductor device formed on the same semiconductor substrate as a reference circuit, wherein the first resistor has a level-up circuit formed on the same semiconductor substrate as the floating reference circuit. 4. The semiconductor device according to claim 2, wherein said level shift circuit includes a Pch MOSFET and said Pc MOSFET.
h MOSFET is formed on the same semiconductor substrate as the floating reference circuit, and the second resistor is formed on the same semiconductor substrate as the GND reference circuit. A semiconductor device having a level down circuit formed on a substrate. 5. The semiconductor device according to claim 2, wherein said level shift circuit includes a Pch MOSFET and said Pc MOSFET.
h PMOSFET and a third resistor connected to the drain of the MOSFET, wherein the Pch MOSFET and the third resistor both have a level down circuit formed on the same semiconductor substrate as the GND reference circuit. Characteristic semiconductor device. 6. The semiconductor device according to claim 1, wherein at least two of said floating reference circuits are connected in series between a high potential side and a ground side of a power supply. A floating reference gate drive circuit for driving a gate of a switching device connected to a high potential side of the switching device, wherein the GND reference circuit supplies or receives a signal to or from the floating reference gate drive circuit. A semiconductor device, which is a control circuit based on GND. 7. The semiconductor device according to claim 6, wherein at least two of the switching devices are connected in series between a high potential side and a ground side of the power supply, and are connected to a low potential side of the switching devices. A GND reference gate drive circuit for driving a gate of the switching device;
A semiconductor device formed on a semiconductor substrate different from the D reference circuit. 8. The semiconductor device according to claim 7, wherein the floating reference gate drive circuit and the GND reference gate drive circuit are provided near the gate of each of the switching devices. . 9. A semiconductor device for controlling at least two switching devices connected in series between different potentials, a gate drive circuit for turning on / off the switching device, and a control circuit for controlling the gate drive circuit. Wherein the gate drive circuit and the control circuit are formed on different semiconductor substrates, respectively. 10. The semiconductor device according to claim 2, wherein the level shift circuit includes an NPN bipolar transistor and a fourth resistor connected to a collector of the NPN bipolar transistor, wherein the NPN bipolar transistor is And a fourth resistor formed on the same semiconductor substrate as the GND reference circuit, and wherein the fourth resistor has a level-up circuit formed on the same semiconductor substrate as the floating reference circuit. 11. The semiconductor device according to claim 2, wherein the level shift circuit includes a PNP bipolar transistor and a fifth resistor connected to the PNP bipolar transistor, wherein the PNP bipolar transistor is A semiconductor device, wherein the fourth resistor is formed on the same semiconductor substrate as the floating reference circuit, and the fourth resistor has a level down circuit formed on the same semiconductor substrate as the GND reference circuit. 12. The semiconductor device according to claim 2, wherein the level shift circuit includes a PNP bipolar transistor and a sixth resistor connected to a collector of the PNP bipolar transistor. The semiconductor device, wherein both the sixth resistors have a level down circuit formed on the same semiconductor substrate as the GND reference circuit. 13. The semiconductor device according to claim 10, wherein at least two of said floating reference circuits are connected in series between a high potential side and a ground side of a power supply. A floating reference gate drive circuit for driving a gate of a switching device connected to a high potential side of the switching device, wherein the GND reference circuit supplies or receives a signal to or from the floating reference gate drive circuit. And a control circuit based on GND.