JP2007242719A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the impact of a supporting substrate potential under a buried oxide film can be lessened, and a high breakdown voltage can be ensured as a whole by distributing the voltage between the GND potential and a predetermined potential uniformly to MOS transistors. <P>SOLUTION: Between the ground (GND) potential and a predetermined potential V<SB>E</SB>, n (n≥2) N channel MOS transistor elements isolated from each other are connected sequentially in series, with the GND potential side as the first stage and the predetermined potential side as the n-th stage. The n (n≥2) N channel MOS transistor elements are formed in the SOI layer of an SOI structure semiconductor substrate having a buried oxide film and isolated from each other by a first isolation trench reaching the buried oxide film. During operation of the semiconductor device, the potential V<SB>sub</SB>of a supporting substrate under a buried oxide film is set equal to or lower than 0.8 times of the predetermined potential V<SB>E</SB>. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a plurality of MOS transistors formed in an SOI layer and insulated from each other are connected in series, and in particular, a high voltage IC that can be applied to a high voltage IC for driving an inverter or the like. The present invention relates to a withstand voltage semiconductor device.

  A high voltage IC for driving an inverter is disclosed in, for example, Japanese Patent No. 3384399 (Patent Document 1) and Proc. of ISPSD '04 (Non-patent Document 1).

  FIG. 15 is a schematic cross-sectional view of a conventional high-voltage IC 90 using an SOI substrate and trench isolation.

  A high voltage IC 90 shown in FIG. 15 is provided with a low potential (GND) reference circuit, a high potential (floating) reference circuit, and a level shift circuit in the SOI layer 1a of the SOI substrate 1 having the buried oxide film 3, respectively. Yes. In addition, the formation regions of the GND reference circuit, the floating reference circuit, and the level shift circuit are insulated (dielectric) separated by the buried oxide film 3 of the SOI substrate 1 and the sidewall oxide film 4s of the trench 4. The SOI substrate 1 is formed by bonding the substrates, and below the buried oxide film 3 is a thick support substrate 2 made of silicon (Si).

  In the level shift circuit of the high voltage IC 90, a high voltage circuit element is required to connect the low potential reference circuit and the high potential reference circuit. The lateral MOS transistor (LDMOS) 9 in the level shift circuit formation region shown in FIG. 15 employs a so-called SOI-RESURF structure in order to ensure a breakdown voltage.

The high voltage in the level shift circuit is applied to the drain D of the LDMOS 9 as shown in the figure. In the LDMOS 9 of FIG. 15, the lateral breakdown voltage of the cross section is ensured by the SOI-RESURF structure formed by the surface p-type impurity layer and the buried oxide film 3. As for the breakdown voltage in the vertical direction of the cross section, as disclosed in Non-Patent Document 1, the high voltage applied between the drain D and the ground (GND) is divided between the low concentration SOI layer 1a and the buried oxide film 3. To relieve the electric field in the SOI layer 1a.
Japanese Patent No. 3384399 Proc. Of ISPSD '04, p385, H. Akiyama, et al (Mitsubishi Electric)

  In a semiconductor device in which an insulated LDMOS is formed in an SOI layer on a buried oxide film like the LDMOS 9 in FIG. 15, the impurity concentration and thickness of the SOI layer are secured in order to ensure a breakdown voltage in the vertical direction of the cross section. It is necessary to optimally design the thickness of the buried oxide film.

  However, in order to obtain a high breakdown voltage of 1000 V or more by this method, a buried oxide film thicker than 5 μm and an SOI layer thicker than 50 μm are required. On the other hand, the upper limit film thickness of the buried oxide film that can be achieved is about 4 μm because of warpage of the SOI substrate. Moreover, the thickness of the SOI layer is usually about several μm to 20 μm, and the trench processing load increases when the thickness of the SOI layer is increased. For this reason, in the LDMOS 9 in the level shift circuit formation region of FIG. 15, the withstand voltage of about 600 V is the limit, and the withstand voltage of 1200 V required by the 400 V power supply system, EV cars, etc. cannot be ensured.

  In order to solve the above problems, the following novel semiconductor device 10 has been invented.

  FIG. 16 is a basic equivalent circuit diagram of the semiconductor device 10.

In the semiconductor device 10 shown in FIG. 16, the transistor elements _Tr 1 to Tr _n of n that are insulated and separated from each other (n ≧ 2), between the ground (GND) potential and the predetermined potential Vs, the GND potential side first One stage is connected in series with the predetermined potential Vs side as the nth stage. The gate terminal of the first-stage transistor element Tr ₁ is an input terminal of the semiconductor device 10. The output of the semiconductor device 10 is taken out from a terminal on the side of the predetermined potential Vs in the n-th stage transistor element Tr _n via a load resistor (not shown) having a predetermined resistance value. The output signal is extracted in a state where the reference potential is converted (level shift) from the GND potential of the input signal to the predetermined potential Vs and inverted with respect to the input signal.

In operation of the semiconductor device 10 of FIG. 16, the voltage between the GND potential and the predetermined potential Vs is divided by the n transistor elements _Tr 1 to Tr _n, each transistor elements _Tr 1 ~ of the n stages from the first stage Tr _n shares the respective voltage ranges. Therefore, the breakdown voltage required for each of the transistor elements Tr _{1 to} Tr _n is approximately ₁ / _n compared to the case where the voltage between the GND potential and the predetermined potential Vs is shared by _one transistor element. Therefore, even a transistor element having a normal withstand voltage that can be manufactured inexpensively using a general manufacturing method is required as a whole by appropriately setting the number n of transistor elements in the semiconductor device 10 of FIG. The semiconductor device can ensure a high breakdown voltage. In the semiconductor device 10 of FIG. 16, it is preferable that the _n transistor elements Tr _{1 to} Tr _n have the same breakdown voltage. Thereby, the voltage (withstand voltage) shared by the transistor elements Tr _{1 to} Tr _n inserted between the GND potential and the predetermined potential can be equalized and minimized.

Specifically, for example, a MOS transistor element having a breakdown voltage of about 150 V can be easily formed by a general manufacturing method using an SOI substrate having a buried oxide film having a thickness of about 2 μm. Thus, the n-number of transistor elements Tr ₁ to Tr _n, which are insulated and separated from each other by isolation trenches formed in the SOI substrate, that a semiconductor device 10 comprising a transistor element series-connected n-stage, high-voltage The semiconductor device can be realized. For example, by connecting transistor elements having a withstand voltage of 150 V in series in two stages, four stages, and eight stages as shown in FIG. 16, the semiconductor devices 10 having a withstand voltage of 300 V, 600 V, and 1200 V can be obtained. Therefore, it is not necessary to change the wafer structure (the thickness of the SOI layer or the buried oxide film, the impurity concentration of the SOI layer, etc.) according to the breakdown voltage. Further, the processing depth of the insulating isolation trench is also constant, and can be easily realized even if the required breakdown voltage is 1000 V or more.

  As described above, the semiconductor device 10 illustrated in FIG. 16 can secure a desired withstand voltage and can be manufactured at low cost by using a general method for manufacturing a semiconductor device. be able to.

  FIG. 17 is a diagram showing in detail the level shift circuit section and the floating reference gate drive circuit section in the high voltage IC 100. Each of the semiconductor devices 10 shown in the basic equivalent circuit diagram of FIG. 16 applied to the level shift circuit is shown. It is a figure which shows arrangement | positioning of a circuit element. 18 is a cross-sectional view taken along one-dot chain line AA in FIG. 17 and shows the structure of each transistor element.

As shown in the sectional view of FIG. 18, the high in voltage IC 100, n-number of transistor elements _Tr 1 to Tr _n in the semiconductor device 10 of FIG. 16, which is applied to the level shift circuit, SOI structure having a buried oxide film 3 semiconductor The n-type SOI layer 1a of the substrate 1 is formed. The SOI substrate 1 is formed by bonding the substrates, and a thick support substrate 2 made of silicon (Si) is formed under the buried oxide film 3.

The n transistor elements Tr _{1 to} Tr _n are LDMOS (Lateral Double-diffused MOS) transistor elements, and are isolated from each other by an insulating isolation trench 4 reaching the buried oxide film 3. In the semiconductor device 10 shown in FIG. 18, unlike the high-voltage IC 90 shown in FIG. 15, in order to shield the high-frequency potential interference caused by switching in the floating reference gate drive circuit, the buried oxide film 3 on the SOI layer 1a. A high concentration impurity layer 1b is formed.

As shown in FIG. 17, in the semiconductor device 10 of the high voltage IC100 is, n heavy isolated separating trenches _T 1 through T _n is formed, the n-number of transistor elements _Tr 1 to Tr _n, which are insulated and separated from each other, n Each field region surrounded by the heavy insulating isolation trenches T _{1 to} T _n is sequentially arranged one by one so as to include high-stage transistor elements therein. As a result, the voltage applied to each field region surrounded by the n-layer insulation isolation trench is equalized in accordance with the voltage increase from the GND potential to the predetermined potential, and the voltage range assigned to the _n transistor elements Tr _{1 to} Tr _n Can be sequentially shifted from the GND potential toward the predetermined potential. Note that there is only one _n- layer insulation isolation trench T _{1 to} T _n between adjacent transistor elements, and the connection wiring of the _n transistor elements Tr _{1 to} Tr _n is facilitated. The occupied area can be reduced and the semiconductor device 10 can be downsized.

As described above, in the semiconductor device 10, the n transistor elements Tr _{1 to} Tr _n may be transistor elements having a normal withstand voltage. Accordingly, the high voltage IC 100 shown in FIG. 17 can secure a withstand voltage of 1200 V, and is a high voltage IC suitable for driving an inverter of a vehicle-mounted motor or an inverter of a vehicle-mounted air conditioner. In addition, about the said invention, patent application has already been filed (application number 2005-227058, application number 2005-318679).

On the other hand, in the semiconductor device 10 (high voltage IC 100) of FIG. 18, the support substrate 2 is in a floating state (floating potential), and the transistor elements Tr _{1 to} Tr _n formed in the SOI layer 1a are embedded oxide films. 3 is considered to be influenced by the potential of the support substrate 2 via 3. That is, when the support substrate 2 is in a floating state, the potential affects the potential of each field region of the SOI layer 1a capacitively coupled via the buried oxide film 3, which is formed in the SOI layer 1a. It is considered that the withstand voltage characteristics of the transistor elements Tr _{1 to} Tr _n are also affected.

  Therefore, the present invention is a semiconductor device in which a plurality of MOS transistors formed in an SOI layer and isolated from each other are connected in series, and the influence of the support substrate potential under the buried oxide film can be reduced, and the GND potential can be reduced. An object of the present invention is to provide a semiconductor device in which a voltage between a predetermined potential and a predetermined potential is evenly distributed to MOS transistors so that a high breakdown voltage can be secured as a whole.

  The semiconductor device according to claim 1 is a semiconductor device in which a plurality of N-channel MOS transistors are connected in series.

  The semiconductor device according to claim 1, wherein n (n ≧ 2) N-channel MOS transistor elements that are insulated from each other are arranged between a ground (GND) potential and a predetermined potential, and the GND potential side is a first stage, A predetermined potential side is an n-th stage and is sequentially connected in series. A gate terminal of the first-stage N-channel MOS transistor element is an input terminal, and n resistance elements and / or capacitance elements are connected to the GND potential. Between the predetermined potentials, the GND potential side is the first stage and the predetermined potential side is the nth stage, which are sequentially connected in series, and the N-channel MOS transistors of each stage excluding the first-stage N-channel MOS transistor elements. A gate terminal of the transistor element is sequentially connected to a connection point between the resistor element and / or the capacitor element of each stage connected in series. A semiconductor device in which an output is taken out from a terminal on the predetermined potential side in a channel MOS transistor element, wherein the n N-channel MOS transistor elements are formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film. And the first insulating isolation trench that reaches the buried oxide film is insulated from each other, and the support substrate under the buried oxide film is not more than 0.8 times the predetermined potential during the operation of the semiconductor device. It is characterized by being set to a potential.

  In the semiconductor device, n N-channel MOS transistors are sequentially connected in series between the GND potential and a predetermined potential. Therefore, in the semiconductor device, the voltage between the GND potential and the predetermined potential is divided by n N-channel MOS transistors, and the N-channel MOS transistors from the first stage to the n-th stage share the respective voltage ranges. ing. Therefore, the DC withstand voltage required for each N-channel MOS transistor can be reduced as compared with the case where the voltage between the GND potential and the predetermined potential is shared by one N-channel MOS transistor.

  Further, based on the simulation results, in the semiconductor device in which a plurality of N-channel MOS transistor elements are formed, the support substrate under the buried oxide film is set to a potential not more than 0.8 times the predetermined potential during operation. Has been. Thus, in the semiconductor device, the voltage between the GND potential and the predetermined potential is evenly distributed to each N-channel MOS transistor regardless of the support substrate potential, and a high breakdown voltage can be ensured as a whole.

  As described above, the semiconductor device in which a plurality of N-channel MOS transistors are formed is a semiconductor device in which MOS transistors formed in an SOI layer and isolated from each other are connected in series, and embedded oxide The influence of the potential of the support substrate under the film can be reduced, and the voltage between the GND potential and the predetermined potential is evenly distributed to the MOS transistors, so that a semiconductor device capable of ensuring a high breakdown voltage as a whole can be obtained.

  In the semiconductor device, it is preferable that the n N-channel MOS transistor elements have the same breakdown voltage.

  As a result, the voltage (withstand voltage) shared by each N-channel MOS transistor inserted between the GND potential and the predetermined potential can be made uniform and minimized.

  According to a third aspect of the present invention, in the semiconductor device, the breakdown voltage of the N-channel MOS transistor element is preferably 200 V or less. According to this, the semiconductor device (N-channel MOS transistor element) can be manufactured at low cost by using a general manufacturing method.

  According to the simulation result, as described in claim 4, in the semiconductor device in which the support substrate potential is set to 0.8 times or less of the predetermined potential, the n, which is the number of N-channel MOS transistors connected in series, is It is preferable that it is 6 or less.

According to a fifth aspect of the present invention, when the n is 12 or less, the support substrate under the buried oxide film is 0.25 times or less the predetermined potential during the operation of the semiconductor device. It is preferable to be set to a potential of.

  According to another aspect of the present invention, in the semiconductor device, the second insulating isolation trench reaching the buried oxide film is formed in (n + 2) layers and surrounded by the (n + 2) layers of second insulating isolation trenches. Of the (n + 2) SOI field layers, the potential of the field region surrounded by the innermost second insulating isolation trench is fixed to the predetermined potential, and the (n + 2) overlapping second region Of the field regions composed of (n + 2) SOI layers surrounded by the insulating isolation trench, the potential of the field region surrounded by the outermost second insulating isolation trench is fixed to the GND potential, and the innermost In each field region composed of n SOI layers surrounded by a second insulating isolation trench excluding the outer periphery and the outermost outer periphery, an N channel insulated by the first insulating isolation trench is provided. Channel MOS transistor, so that are arranged one by one, respectively, can be configured.

  As a result, as the voltage increases from the GND potential to the predetermined potential, the voltage applied to each field region surrounded by the (n + 2) -fold second insulating isolation trench is equalized, and the n N-channel MOS transistor elements are in charge. The voltage range can be sequentially shifted from the GND potential toward the predetermined potential. In addition, since there is only one n-layer insulation isolation trench between adjacent N-channel MOS transistor elements that are isolated from each other, connection wiring of n transistor elements is facilitated and occupied. The area can be reduced and the semiconductor device can be downsized.

  In the semiconductor device, as described in claim 7, it is preferable that the potential of the support substrate is a floating potential that does not require a new DC power source for potential setting. The potential of the substrate is set approximately by the ratio of the occupied area of the field region surrounded by the innermost second insulating isolation trench and the occupied area of the field region surrounded by the outermost second insulating isolation trench. Can be configured.

  In addition, as described in claim 8, the thickness of the buried oxide film and the outermost periphery of the support substrate are approximately equal to a field region surrounded by the innermost second insulating isolation trench. It may be configured to be set by the ratio of the thickness of the buried oxide film immediately below the field region surrounded by the second insulating isolation trench.

  The semiconductor device according to any one of claims 9 to 15 is a semiconductor device in which a plurality of P-channel MOS transistors are connected in series.

  The semiconductor device according to claim 9, wherein m (m ≧ 2) P-channel MOS transistor elements that are insulated from each other are arranged between a predetermined potential and a ground (GND) potential at a predetermined potential side in the first stage. The GND potential side is the m-th stage and is sequentially connected in series. The gate terminal of the first-stage P-channel MOS transistor element is an input terminal, and m resistance elements and / or capacitance elements are connected to the predetermined potential. Between the GND potentials, a predetermined potential side is a first stage, and a GND potential side is an m-th stage, which are sequentially connected in series, and the P channel MOS transistors of each stage excluding the first stage P channel MOS transistor elements. A gate terminal of the transistor element is sequentially connected to a connection point between the resistor element and / or the capacitor element of each stage connected in series. A semiconductor device in which an output is extracted from a terminal on the GND potential side in a channel MOS transistor element, wherein the m P-channel MOS transistor elements are formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film. And the third insulating isolation trench that reaches the buried oxide film is isolated from each other, and the support substrate under the buried oxide film is at least 0.8 times the predetermined potential during the operation of the semiconductor device. It is characterized by being set to a potential.

  In the semiconductor device, m P-channel MOS transistors are sequentially connected in series between a predetermined potential and a GND potential. Therefore, in the semiconductor device, the voltage between the predetermined potential and the GND potential is divided by the m P-channel MOS transistors, and the P-channel MOS transistors from the first stage to the m-th stage share the respective voltage ranges. ing. Therefore, also in the semiconductor device in which a plurality of P-channel MOS transistors are connected in series, each P-channel MOS transistor is compared with a case where the voltage between the predetermined potential and the GND potential is shared by one P-channel MOS transistor. The DC withstand voltage required for this can be reduced.

  Further, based on the simulation results, in the semiconductor device in which a plurality of P-channel MOS transistors are formed, the support substrate under the buried oxide film is set to a potential of 0.8 times or more the predetermined potential during operation. ing. Thus, in the semiconductor device, regardless of the support substrate potential, the voltage between the predetermined potential and the GND potential is evenly distributed to each P-channel MOS transistor, thereby ensuring a high breakdown voltage as a whole.

  As described above, the semiconductor device in which a plurality of P-channel MOS transistors are formed is also a semiconductor device in which MOS transistors formed in an SOI layer and isolated from each other are connected in series, and embedded oxide The influence of the potential of the support substrate under the film can be reduced, and the voltage between the GND potential and the predetermined potential is evenly distributed to the MOS transistors, so that a semiconductor device capable of ensuring a high breakdown voltage as a whole can be obtained.

  The effects of the semiconductor device according to claims 10 to 15 are the same as those of the semiconductor device in which the N-channel MOS transistor described in claims 2 to 8 is formed, and the description thereof is omitted.

  The semiconductor device according to claim 16 is a semiconductor device in which a plurality of N-channel MOS transistors connected in series and a plurality of P-channel MOS transistors connected in series are formed on the same SOI substrate. .

  The semiconductor device according to claim 16, wherein n (n ≧ 2) N-channel MOS transistor elements that are insulated from each other are arranged between a ground (GND) potential and a predetermined potential, and the GND potential side is a first stage, A predetermined potential side is an n-th stage and is sequentially connected in series. A gate terminal of the first-stage N-channel MOS transistor element is an input terminal, and n resistance elements and / or capacitance elements are connected to the GND potential. Between the predetermined potentials, the GND potential side is the first stage and the predetermined potential side is the nth stage, which are sequentially connected in series, and the N-channel MOS transistors of each stage excluding the first-stage N-channel MOS transistor elements. A gate terminal of the transistor element is sequentially connected to a connection point between the resistor element and / or the capacitor element of each stage connected in series. An output is taken out from the terminal on the predetermined potential side of the channel MOS transistor element, and m (m ≧ 2) P channel MOS transistor elements that are insulated from each other have the predetermined potential and the ground (GND) potential. The first potential stage is the first stage, the GND potential side is the mth stage, and they are sequentially connected in series. The gate terminal of the first stage P-channel MOS transistor element is the input terminal, and m resistance elements And / or capacitive elements are sequentially connected in series between the predetermined potential and the GND potential, with the predetermined potential side being the first stage and the GND potential side being the m-th stage. The gate terminals of the P-channel MOS transistor elements at each stage excluding the transistor elements are connected to the resistor elements and / or capacitors at the stages connected in series. The n n-channel MOS transistors are sequentially connected to the connection points between the children, and output is taken out from the GND potential side terminal of the m-th stage P-channel MOS transistor element. An element and the m P-channel MOS transistor elements are respectively formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film, and the n N-channel MOS transistor elements reach the buried oxide film. The m P-channel MOS transistor elements are isolated from each other by an isolation trench, and the m P-channel MOS transistor elements are isolated from each other by a third isolation trench that reaches the buried oxide film, and are supported under the buried oxide film. When the substrate is in operation of the semiconductor device, 0.7 times or more of the predetermined potential, 0. It is characterized in that the potential is set to 9 times or less.

  Also in the above semiconductor device, for n n-channel MOS transistors and m P-channel MOS transistors connected in series between a predetermined potential and a GND potential, a voltage between the predetermined potential and the GND potential is set to one. It goes without saying that the DC withstand voltage required for each MOS transistor can be reduced as compared with the case of sharing with the MOS transistors.

  Further, based on the simulation results, in the semiconductor device in which a plurality of N-channel MOS transistors connected in series and a plurality of P-channel MOS transistors connected in series are formed on the same SOI substrate, The support substrate under the buried oxide film is set to a potential of 0.7 to 0.9 times the predetermined potential. As a result, in the semiconductor device as well, the voltage between the predetermined potential and the GND potential is evenly distributed to each N-channel MOS transistor and each P-channel MOS transistor regardless of the support substrate potential, thereby ensuring a high breakdown voltage as a whole. can do.

  As described above, the above-described semiconductor device in which a plurality of N-channel MOS transistors and P-channel MOS transistors are formed on the same SOI substrate also includes MOS transistors formed in the SOI layer and isolated from each other in series. In this semiconductor device, the influence of the potential of the support substrate under the buried oxide film can be reduced, and the voltage between the GND potential and the predetermined potential can be evenly distributed to the MOS transistors, thereby ensuring a high breakdown voltage as a whole. A semiconductor device can be obtained.

  In particular, as described in claim 19, when the n and the m in the semiconductor device are 6 or less, the support substrate under the buried oxide film is in the predetermined state during the operation of the semiconductor device. It is preferable that the potential is set to approximately 0.8 times the potential.

  The effects of the semiconductor device described in claims 17 to 18 and 20 to 22 are the same as those of the semiconductor device in which the N-channel MOS transistor described in claims 2 to 8 is formed. Omitted.

  25. The semiconductor device according to claim 23, wherein the semiconductor device includes a GND reference gate drive circuit based on a GND potential, a floating reference gate drive circuit based on a floating potential, and an input / output between the GND potential and the floating potential. In a high voltage IC for driving an inverter having a level shift circuit for level shifting a signal, the predetermined power supply potential is set as a floating potential, which is suitable for the level shift circuit.

  The high-voltage IC may be, for example, a high-voltage IC for driving an inverter of an in-vehicle motor as described in claim 24, or an inverter for driving an inverter of an in-vehicle air conditioner, as described in claim 25. It may be a high voltage IC.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a semiconductor device 11 as an example of the semiconductor device of the present invention.

  The semiconductor device 11 shown in FIG. 1 has a simplified configuration of the semiconductor device 10 shown in FIG.

The cross-sectional structure of the semiconductor device 11 shown in FIG. 1 is the same as the cross-sectional structure of the semiconductor device 10 shown in FIG. That is, the semiconductor device 11 shown in FIG. 1 uses an SOI substrate having a buried oxide film formed by bonding the substrates, similar to the SOI substrate 1 shown in FIG. Further, the first isolation trench Z1 of the semiconductor device 11 shown in FIG. 1 corresponds to the isolation trench 4 of the semiconductor device 10 shown in FIG. 18, and the second isolation trench of the semiconductor device 11 shown in FIG. Z2 corresponds to the isolation trenches _T 1 through T _n of the semiconductor device 10 shown in FIG. 18. In the following description of the semiconductor device 11 of FIG. 1, the same reference numerals as those of the respective parts in the cross section shown in FIG. 18 are used.

  The semiconductor device 11 shown in FIG. 1 uses an SOI substrate 1 having a buried oxide film 3, and n (n ≧ 2) N-channel lateral MOS transistors (LDMOS) 11 t are formed on the buried oxide film 3. It is formed in the SOI layer 1a. Each LDMOS 11t has a pattern in which the drain D, the gate G, and the source S are arranged concentrically as shown in FIG. Each LDMOS 11t is surrounded by a first insulating isolation trench Z1 reaching the buried oxide film 3, which is indicated by a thick solid circle in FIG.

  In the semiconductor device 11 shown in FIG. 1, the second insulating isolation trenches Z <b> 2 indicated by thick solid squares in the drawing that reaches the buried oxide film 3 are formed in multiple. Each LDMOS 11t insulated and separated by the first insulation isolation trench Z1 is arranged one by one in each field region F1 to Fn surrounded by the multiple second insulation isolation trenches Z2. The field region Fh inside the field region Fn is a region where a high voltage (HV) circuit, a power supply pad, an output pad, etc. are formed, and the field region Fg outside the field region F1 is grounded ( GND) A region where pads, input pads, and the like are formed.

In the semiconductor device 11 of FIG. 1, n LDMOSs 11t are arranged between the ground (GND) potential and a predetermined power supply potential so that the outer peripheral side of the n-th second insulating isolation trench Z2 is the first stage on the GND potential side, The inner periphery side is sequentially connected in series with the nth stage on the power supply potential side. The symbol R _in is an input resistance, and the symbol R _out is an output resistance. In the semiconductor device 11, the gate terminal in the first stage LDMOS 11t is used as the input terminal. In addition, an output resistor R _out is connected between the nth stage LDMOS 11t and the power supply pad, and an output is taken _out between the power supply potential side terminal of the nth stage LDMOS 11t and the output resistor Rout. In the semiconductor device 11, the combination of the resistor element R and the capacitor element C connected in parallel is connected in series in multiple stages, the GND potential and the power supply potential are divided, and the gate of the LDMOS 11 t in the second and subsequent stages is connected to the series connection. Connected to each branch point. In the semiconductor device 11 of FIG. 1, the combination of the resistor element R and the capacitor element C is connected in series in multiple stages, but only the resistor element R or the capacitor element C may be connected in series in multiple stages.

  In the semiconductor device 11 of FIG. 1, as the voltage increases from the GND potential to a predetermined potential, the voltages applied to the field regions Fg, F1 to Fn, Fh surrounded by the (n + 2) -fold second insulating isolation trenches are equalized. Thus, the assigned voltage range of the n N-channel MOS transistor elements (LDMOS 11t) can be sequentially shifted from the GND potential toward the predetermined potential. In other words, in the semiconductor device 11 shown in FIG. 1, the voltage between the GND potential and the power supply potential is divided by n LDMOSs 11t, and the LDMOSs 11t from the first stage to the nth stage share the respective voltage ranges. Yes. Therefore, the DC breakdown voltage required for each LDMOS 11t can be reduced as compared with the case where the voltage between the GND potential and the power supply potential is shared by one MOS transistor element. In addition, since there is only one n-layer insulation isolation trench between adjacent N-channel MOS transistor elements that are isolated from each other, connection wiring of n transistor elements is facilitated and occupied. The area can be reduced and the semiconductor device 11 can be downsized.

  In the semiconductor device 11 shown in FIG. 1, it is preferable that n LDMOSs 11t have the same breakdown voltage. As a result, the voltage (withstand voltage) shared by the LDMOS 11t inserted between the GND potential and the power supply potential can be equalized and minimized. The breakdown voltage of each LDMOS 11t is preferably 200V or less. As a result, the semiconductor device 11 (LDMOS 11t) can be manufactured at low cost using a general manufacturing method.

  Next, as pointed out in the semiconductor device 10 (high voltage IC 100) of FIG. 18, the semiconductor device 11 shown in FIG. 1 is formed in the SOI layer 1a because the support substrate 2 is in a floating state (floating potential). Each LDMOS 11t is considered to be affected by the potential of the support substrate 2 through the buried oxide film 3. Therefore, the preferred setting range of the potential of the support substrate 2 that does not adversely affect each LDMOS 11t in the semiconductor device 11 of FIG.

  FIG. 2 is a diagram showing an equivalent circuit of the semiconductor device 11 shown in FIG. In the model of FIG. 2, parasitic capacitances C1 to Cn through the buried oxide film 3 between the field regions F1 to Fn in which the transistors M1 to Mn are arranged and the support substrate 2 are inserted. In FIG. 2, the field regions F1 to Fn in which the transistors M1 to Mn are arranged have an area of 200 μm □, the buried oxide film has a thickness of 3 μm, and the parasitic capacitances C_box of the parasitic capacitances C1 to Cn = 0.5 pF. .

Figure 3 and Figure 4 is a simulation result example using the equivalent circuit of FIG. 2 shows the relationship between the drain-source voltage of the N-channel MOS transistor M1~Mn constituting the power supply potential V _E and the semiconductor device 11 It is a figure. 3A and 3B, the set potential of the support substrate is set to ½ of the power supply potential, and the number of N-channel MOS transistors connected in series is changed. 4A and 4B, the number of N-channel MOS transistors connected in series is 12, and the set potential of the support substrate is changed.

FIG. 3A shows a result obtained by connecting four N-channel MOS transistors M1 to M4 in series in the equivalent circuit of FIG. 2, and FIG. 3B shows 12 N-channel MOS transistors M1. It is the result obtained by connecting ~ M12 in series. Incidentally, FIG. 3 (a), is set (b), the both, in the equivalent circuit of FIG. 2, the potential _{V sub} of the support substrate 2 to a half of the power supply potential _{V E.}

FIG. 3A assumes a case where four N-channel MOS transistors having a withstand voltage of 200V are connected in series, and is an example in which a system with an overall withstand voltage of 800V is designed. In FIG. 3 (a), the power supply potential _{V E} simulates source-drain voltages of the transistors M1~M4 when a linearly increased potential to 800V over a period of 10 seconds from 0V.

As she is shown in FIG. 3 (a), in the case of series connection of four N-channel MOS transistor M1~M4, by setting the potential _{V sub} of the support substrate 2 to a half of the power supply potential _{V E,} the power supply potential _{V E} can be equally shared by each N-channel MOS transistors M1 to M4.

  On the other hand, FIG. 3B assumes a case where 12 N-channel MOS transistors having a withstand voltage of 200V are connected in series, and is an example of designing a system in which the overall withstand voltage is 2400V.

As shown in FIG. 3B, when twelve transistors M1 to M12 are connected in series, the voltage between the source and drain of each transistor M1 to M12 is not necessarily equal even if the voltage rise time is 10 seconds. It will not be the same value. In particular, the transistor on the low potential side breaks down because the source-drain voltage exceeds 200V. Thus, when the 12 by increasing the number of transistors connected in series, setting the half of the same power supply potential V _E in the case of the four potential V _sub of the support substrate 2, a power supply can not be evenly shared by the potential _{V E} each N-channel MOS transistors M1 to M12, the variation occurs.

4 (a) and 4 (b) are the results obtained by connecting 12 N-channel MOS transistors M1 to M12 in series in the equivalent circuit of FIG. FIG. 4 (a), in the equivalent circuit of FIG. 2, the potential _{V sub} support substrate 2 is set to 3/4 of the power supply potential _{V E.} FIG. 4 (b), the potential _{V sub} support substrate 2 is set to 1/4 of the power supply potential _{V E.}

As shown in FIG. 3 (b) and 4 (a), the N-channel MOS transistor M1~M12 when connected in series, the closer the potential _{V sub} of the support substrate 2 to the power supply potential _{V E,} the power supply potential V _E cannot be shared equally among the N-channel MOS transistors M1 to M12, and variations occur. On the other hand, as shown in FIG. 4 (b), in the case of series connection the 12 N-channel MOS transistor M1~M12 is possible to set the potential _{V sub} of the support substrate 2 to 1/4 of a power supply potential _{V E} in, it can be equally share the power supply potential _{V E} on the N-channel MOS transistor M1 to M12.

  As described above, the overall breakdown voltage varies depending on the number of stages of MOS transistors connected in series and the potential of the support substrate, and the overall breakdown voltage is not necessarily double the number of stages of breakdown voltage of each MOS transistor. Therefore, in order to increase the overall breakdown voltage, it is necessary to control the potential of the support substrate 2 to equalize the voltage shared by the MOS transistors connected in series.

  FIG. 5 is a diagram showing an equivalent circuit of the semiconductor device 11 shown in FIG. 1 used in the simulation as another simulation example. In the equivalent circuit of FIG. 5, six N-channel MOS transistors M1 to M6 are connected in series. In the equivalent circuit of FIG. 5, the diodes connected in parallel to the N-channel MOS transistors M1 to M6 set the withstand voltage of the N-channel MOS transistors M1 to M6 to 200 V, and therefore are modeled as reverse withstand voltages of the diodes. It was inserted into the form.

6 to 8 are examples of simulation results using the equivalent circuit of FIG. 5, and the power supply potential _VE and each N-channel MOS transistor constituting the semiconductor device 11 when the set potential V _sub of the support substrate is changed. It is the figure which showed the relationship of the drain-source voltage of M1-M6. 6 to 8, the parameters shown in FIG. 5 (buried oxide film capacitance at each stage: C_box = 0.35 pF, input resistance: Rin = 100 kΩ, division resistance: R_div = 1 MΩ, output resistance: Rout = 100 kΩ) is used. The buried oxide film capacitance at each stage: C_box = 0.35 pF is a representative value obtained when the device size is 100 μm □ and the buried oxide film thickness is 1 μm.

_6A is a result obtained by setting the potential V _sub of the support substrate 2 to the GND potential (0 V) in the equivalent circuit of FIG. 5, and FIG. the potential _{V sub,} a result obtained by setting 0.5 times the power supply potential _{V E.} 7 (a) is a potential _{V sub} of the support substrate 2, the result obtained by setting 0.7 times the power supply potential _{V E,} FIG. 7 (b), the supporting substrate 2 potential _{V sub} and a result obtained by setting 0.8 times the power supply potential V _E. Further, FIG. 8 (a), the potential _{V sub} of the support substrate 2, the result obtained by setting 0.9 times the power supply potential _{V E,} FIG. 8 (b), the supporting substrate 2 potential the V _sub, a result obtained by setting the same potential as the power supply potential V _E. In this example, the simulation was performed using a model in which the power supply potential _VE is connected to the support substrate 2 by a simple capacitive coupling equivalent circuit shown in FIG. 5 on SPICE (Simulation Program with Integrated Circuit Emphasis). In an analysis performed by simple device simulation, the same results as those shown below are obtained.

The simulation results when the six N-channel MOS transistors shown in FIGS. 6 to 8 are connected in series are also supported in the same manner as in the case of the twelve shown in FIGS. 3 (b), 4 (a), and 4 (b). the closer the potential _{V sub} of the substrate 2 to the power supply potential _{V E,} it can not be evenly shared by the N-channel MOS transistors M1-M6, variation occurs.

Further, as can be seen by comparing the results of FIGS. 6 to 8 with the results of FIGS. 3B and 4A and 4B, the power supply increases as the number of N-channel MOS transistors connected in series increases. set potential V range _sub of the support substrate 2 which can be shared equally potential V _E on the N-channel MOS transistor is gradually narrowed.

In particular, as can be seen from the results of FIGS. 6 to 8, in the circuit in which the N-channel MOS transistors are connected in series, the drain potential of the MOS transistor on the lowest potential (GND potential) side becomes higher as the potential V _sub of the support substrate 2 becomes higher. It is easy to become. Therefore, in this transistor, the electric field tends to concentrate between the source and the drain. This can be attributed to the following factors. First, when the potential V _sub of the support substrate 2 is high, the amount of charge to be accumulated increases due to the parasitic capacitance between the support substrate 2 and the field region F1 on the GND potential side. However, the DC voltage does not actually take an infinite time, but the potential V _sub of the support substrate 2 rises in a finite time. Therefore, a time lag occurs until the parasitic capacitance is charged. The potential of the MOS transistor near the GND potential side rises transiently. In addition, since the current due to the movement of charges passes through these MOS transistors and is absorbed, the tendency for the tendency to increase is considered because the charges are less likely to move between the MOS transistors as the number of stages is increased.

According to the simulation results shown in FIGS. 3, 4 and 6 to 8 described above, the semiconductor device 11 of FIG. 1 in which a plurality of N-channel MOS transistor elements (LDMOSs 11t) are formed is embedded during operation. The potential V _sub of the support substrate 2 under the oxide film 3 is preferably set to be 0.8 times or less of a predetermined potential (power supply potential V _E ).
As a result, in the semiconductor device 11 of FIG. 1, the voltage between the GND potential and the predetermined potential is evenly distributed to each N-channel MOS transistor element (LDMOS 11t) regardless of the support substrate potential, thereby ensuring a high breakdown voltage as a whole. can do.

  In particular, in the semiconductor device 11 of FIG. 1 in which the support substrate potential is set to 0.8 times or less of the predetermined potential, as can be seen from the simulation results of FIG. 6 and FIG. n is preferably 6 or less. Further, as can be seen from the simulation result of FIG. 4B, when n is 12 or less, the support substrate 2 under the buried oxide film 3 has a predetermined potential of 0 during the operation of the semiconductor device 11. It is preferable that the potential is set to 25 times or less.

  As described above, the semiconductor device in which a plurality of N-channel MOS transistors are formed is a semiconductor device in which MOS transistors formed in an SOI layer and isolated from each other are connected in series, and embedded oxide The influence of the potential of the support substrate under the film can be reduced, and the voltage between the GND potential and the predetermined potential is evenly distributed to the MOS transistors, so that the semiconductor device can secure a high breakdown voltage as a whole.

  The semiconductor device described above is a semiconductor device in which a plurality of N-channel MOS transistors are formed. Next, a semiconductor device in which a plurality of P-channel MOS transistors are formed will be described.

  FIG. 9 is an example of a simulation of a semiconductor device in which a plurality of P-channel MOS transistors are formed, and shows an equivalent circuit used for the simulation. In the equivalent circuit of FIG. 9, six P-channel MOS transistors M1 to M6 having the same number as in FIG. 5 are connected in series. Note that the diodes connected in parallel to the N-channel MOS transistors M1 to M6 in the equivalent circuit of FIG. 9 are also for setting the withstand voltage of the P-channel MOS transistors M1 to M6 to 200V. Further, each parameter value shown in FIG. 9 (filled oxide film capacitance at each stage: C_box = 0.35 pF, input resistance: Rin = 100 kΩ, division resistance: R_div = 1 MΩ, output resistance: Rout = 100 kΩ) is shown in FIG. The same value is used as in the case of the N channel MOS transistor.

10-12 is a simulation result example using the equivalent circuit of FIG. 9, the case of changing the set potential of the support substrate, between the power supply potential V _E and the drain and source of each P-channel MOS transistor M1~M6 It is the figure which showed the relationship of the voltage.

FIG. 10A shows the result obtained by setting the potential V _sub of the support substrate 2 to the GND potential (0 V) in the equivalent circuit of FIG. 9, and FIG. the potential _{V sub,} a result obtained by setting 0.5 times the power supply potential _{V E.} 11 (a) shows the potential _{V sub} support substrate 2, the result obtained by setting 0.7 times the power supply potential _{V E,} FIG. 11 (b), the supporting substrate 2 potential _{V sub} and a result obtained by setting 0.8 times the power supply potential V _E. Further, FIG. 12 (a), the potential _{V sub} of the support substrate 2, a power supply potential _V results obtained set 0.9 times _E, FIG. 12 (b), the supporting substrate 2 potential the V _sub, a result obtained by setting the same potential as the power supply potential V _E.

10 to 12 in the simulation result when the P-channel MOS transistor connected in series shown, when the reverse connected in series to N-channel MOS transistor shown in FIGS. 6-8, the power supply potential V _sub of the support substrate 2 The power supply potential V _E can be equally shared among the P channel MOS transistors M1 to M6 as the potential V _E approaches.

According to the simulation results of FIGS. 10 to 12 described above, in the semiconductor device in which a plurality of P-channel MOS transistor elements are formed, the support substrate 2 under the buried oxide film 3 shown in FIG. The potential V _sub is preferably set to 0.8 times or more the predetermined potential (power supply potential V _E ).
Thus, in the semiconductor device, a voltage between the GND potential and the predetermined potential is evenly distributed to each P-channel MOS transistor element regardless of the support substrate potential, and a high breakdown voltage can be ensured as a whole. In particular, in the semiconductor device in which the support substrate potential is set to 0.8 times or more the predetermined potential, as can be seen from the simulation results of FIG. 11B and FIG. 12, the number of P-channel MOS transistors connected in series is m. (M ≧ 2) is preferably 6 or less.

  As described above, the semiconductor device in which a plurality of P-channel MOS transistors are formed is also a semiconductor device in which MOS transistors formed in an SOI layer and isolated from each other are connected in series, and embedded oxide The influence of the potential of the support substrate under the film can be reduced, and the voltage between the GND potential and the predetermined potential is evenly distributed to the MOS transistors, so that a semiconductor device capable of ensuring a high breakdown voltage as a whole can be obtained.

  The same applies to a semiconductor device in which a plurality of N-channel MOS transistors connected in series and a plurality of P-channel MOS transistors connected in series are formed on the same SOI substrate.

  Also in the semiconductor device, n (n ≧ 2) N channel MOS transistors and m (m ≧ 2) P channel MOS transistors connected in series between a predetermined potential and a GND potential It goes without saying that the DC withstand voltage required for each MOS transistor can be reduced as compared with the case where the voltage between the GND potentials is shared by one MOS transistor.

  As can be seen from the simulation results of FIGS. 6 to 9 and FIGS. 10 to 12, a plurality of N-channel MOS transistors connected in series and a plurality of P-channel MOS transistors connected in series have the same SOI. In the semiconductor device formed on the substrate, during operation, the support substrate under the buried oxide film is preferably set to a potential not less than 0.7 times and not more than 0.9 times the predetermined potential. As a result, in the semiconductor device as well, the voltage between the predetermined potential and the GND potential is evenly distributed to each N-channel MOS transistor and each P-channel MOS transistor regardless of the support substrate potential, thereby ensuring a high breakdown voltage as a whole. can do. In particular, as can be seen from the simulation results of FIGS. 7B and 11B, n, which is the number of N channel MOS transistors connected in series, and m, which is the number of P channel MOS transistors connected in series, is 6 or less. In this case, it is preferable that the support substrate under the buried oxide film is set to a potential approximately 0.8 times the predetermined potential during the operation of the semiconductor device.

  As described above, the above-described semiconductor device in which a plurality of N-channel MOS transistors and P-channel MOS transistors are formed on the same SOI substrate also includes MOS transistors formed in the SOI layer and isolated from each other in series. In this semiconductor device, the influence of the potential of the support substrate under the buried oxide film can be reduced, and the voltage between the GND potential and the predetermined potential can be evenly distributed to the MOS transistors, thereby ensuring a high breakdown voltage as a whole. A semiconductor device can be obtained.

  Next, with reference to the semiconductor device 11 shown in FIG. 1 as an example, a method for setting the potential of the support substrate related to the semiconductor device described above will be described.

  In the semiconductor device described above, the potential of the support substrate is preferably a floating potential that does not require a new DC power source for setting the potential.

  In the case of the semiconductor device 11 of FIG. 1, the potential of the support substrate 2 shown in FIG. 18 is approximately equal to the occupied area of the field region Fh surrounded by the innermost second insulating isolation train Z2 and the second outermost periphery. It can be set by the ratio of the occupied area of the field region Fg surrounded by the insulating isolation trench Z2.

FIG. 13 is a diagram schematically showing a method for setting the support substrate potential. The high potential region Fh in FIG. 13 corresponds to the field region Fh in FIG. 1, and corresponds to the region in which the floating reference gate drive circuit unit is formed in the high voltage IC 100 shown in FIG. In this region, the inverter driving transistor and the like are formed in the SOI region at the power supply potential. Low potential region Fg in Figure 13, with corresponding to the field region Fg in Figure 1, in the high voltage IC100 shown in FIG. 17, corresponding to the outer region of the isolation trenches T _1. In this region, signal input pads, protection circuits, and the like are formed in the SOI region at the ground potential. The transistor regions F1 to Fn in FIG. 13 correspond to the field regions F1 to Fn in FIG. 1, and in the high voltage IC 100 shown in FIG. 17, the transistors Tr _{1 to} Tr _n of the level shift circuit unit are arranged. It corresponds to a region surrounded by n-fold insulating isolation trenches T _{1 to} T _n . The transistor regions F1 to Fn are provided with a predetermined area in the vicinity of potentials shared by the MOS transistors connected in series.

  FIG. 13 shows the power supply potential Ve of the field region Fh when the thickness of the buried oxide film 3 is constant and the occupied area ratio (S1: S2: S3) of the field regions Fg, F1 to Fn, Fh is changed. An example of the calculation result related to the potential of the support substrate 2 derived from the GND potential of the field region Fg is shown.

The potential of the support substrate 2 in the system of FIG. 13, in conjunction with the power supply potential V _E, is substantially proportional to the potential. For example, the high potential region Fh in the hands potential region Fg and the power source potential V _E at the GND potential is 1: 1 when an area ratio, the potential of the support substrate 2 is approximately half of the power supply potential V _E Become.

  In general, since the area of the low potential side field region Fg is larger than that of the high potential side field region Fh, the potential of the support substrate 2 is equal to that of the high potential side field region Fh. The potential is extremely lower than the average potential of the field region Fg. Therefore, the potentials of the field regions F1 to Fn in which the MOS transistors are formed are lowered, and it is difficult to distribute the potentials evenly, so that the overall breakdown voltage is lowered. Therefore, in order to control the potential of the support substrate 2 to a high potential, the withstand voltage is improved by adopting a structure in which capacitive coupling between the field region Fh on the high potential side and the support substrate 2 is increased.

  In the semiconductor device using the support substrate potential setting method shown in FIG. 13, the layout of each field region is first devised so that the area of the field region with a higher potential becomes larger. For example, a wiring, a pad, etc. are laid out above the field region Fh of the power supply potential as much as possible. Conversely, wiring, pads, etc. are not laid out in the field region Fg at the GND potential. Alternatively, by providing a dummy field region, the area ratio on the power supply potential side is increased. Further, the field regions F1 to Fn in which the transistors are arranged are also arranged so that the area of the field region scheduled to be high near the power supply potential is increased, and conversely, the area near the GND potential is reduced.

  As can be seen from the calculation result of FIG. 13, in the semiconductor device 11 of FIG. 1, the potential of the support substrate 2 is between the field regions Fg, F1 to Fn, Fh and the support substrate 2 via the buried oxide film 3. It is determined by the capacity ratio. That is, the potential of the support substrate 2 in the floating state is determined by capacitive coupling between the support substrate 2 and the field regions Fg, F1 to Fn, Fh via the buried oxide film 3. Therefore, in the case of the semiconductor device 11 of FIG. 1, the buried oxide film 3 immediately below the field region Fh surrounded by the innermost second insulating isolation train Z2 is set to the potential of the support substrate 2 shown in FIG. And the thickness of the buried oxide film 3 immediately below the field region Fg surrounded by the outermost second insulating isolation trench Z2.

  FIG. 14 is a diagram schematically showing a method for setting the support substrate potential. Also in this case, the capacity ratio (C1: C2: C3) shown in FIG. 13 is supported when the thickness of the buried oxide film 3 is changed while the occupation area ratio of each field region Fg, F1 to Fn, Fh is constant. The result is the same as the calculation result regarding the potential of the substrate 2.

  In order to change the thickness of the buried oxide film 3, for example, the following means can be used.

  At a minimum, a buried oxide film having a certain thickness is formed on a silicon (Si) wafer by means such as thermal oxidation or film deposition. Next, the buried oxide film in the field region to be thinned in advance is removed by etching, and re-oxidation is performed, thereby making a difference in the oxide film thickness for each field region. Next, an SOI (silicon) layer to be an active layer is formed by epitaxial growth. The SOI layer may be formed by epitaxial growth to a required film thickness. In the case of a flat epitaxial layer, a silicon substrate may be further bonded by wafer bonding, and then etched to the required film thickness.

  As another means, first, in the field region where the thick buried oxide film is formed, the Si wafer may be removed by etching by the film thickness to be increased, and the oxide film may be buried there. Alternatively, after the entire surface is thermally oxidized, the buried oxide film thickness is differentiated by embedding an oxide film in the recess. In this case, since the surface of the buried oxide film in the middle of processing becomes flat (or can be processed so as to do so), an SOI layer can be formed thereafter by a normal wafer bonding technique.

  Instead of changing the thickness of the buried oxide film, a high dielectric constant film such as an ONO film may be used to increase the capacitance ratio of the field region on the high potential side. The method of introducing a high dielectric constant film is particularly safe in terms of breakdown voltage. As another method for obtaining the same effect, the buried oxide film in the field region on the high potential side may be provided with unevenness so as to increase the capacitance area.

  In order to control the capacitance of the buried oxide film, means for changing the relative dielectric constant of the buried oxide film material include forming an ONO film having a different film thickness in each field region during the buried oxide film forming process, and silicon nitride (SiN ) Etc., various dielectric materials can be used. As a means for making the buried oxide film uneven, for example, the silicon oxide may be first made fine and then the buried oxide film may be formed by thermal oxidation.

Further, the occupation area ratio of each field region Fg, F1 to Fn, Fh and the thickness ratio of the buried oxide film immediately below each field region Fg, F1 to Fn, Fh may be changed. For example, as shown in FIG. 13, in a system in which the area of the low potential region S1: the area of the transistor region S2: the area of the high potential region S3 = 1: 1: 1, the potential of the support substrate 2 is set to the power supply potential _VE . On the other hand, it is 0.5 times 1/2. Here, the buried oxide film thickness just below the low potential region is doubled to double the capacitance, and the buried oxide film thickness just below the high potential region is halved to double the capacitance. The substrate potential can be 0.8 times (C1: C2: C3 = 0.5: 1: 2 system).

  As described above, the semiconductor device is a semiconductor device in which a plurality of MOS transistors formed in an SOI layer and isolated from each other are connected in series, and is affected by the potential of the support substrate under the buried oxide film. As a result, the voltage between the GND potential and the predetermined potential is evenly distributed to the MOS transistors, and the semiconductor device can secure a high breakdown voltage as a whole.

  Therefore, the semiconductor device includes, for example, a GND reference gate drive circuit based on the GND potential, a floating reference gate drive circuit based on the floating potential, and a level at which an input / output signal is level-shifted between the GND potential and the floating potential. In a high voltage IC for driving an inverter having a shift circuit, it is suitable for the level shift circuit in which a predetermined power supply potential is a floating potential. The high voltage IC may be, for example, a high voltage IC for driving an inverter of an in-vehicle motor, or a high voltage IC for driving an inverter of an in-vehicle air conditioner. Further, the present invention is not limited to this, and can be applied to the field of consumer / industrial motor control.

1 is a diagram showing a schematic configuration of a semiconductor device 11 as an example of a semiconductor device of the present invention. It is an example of simulation, and is a figure which shows the equivalent circuit of the semiconductor device 11 shown in FIG. 1 used for simulation. (A) and (b) are examples of simulation results using the equivalent circuit of FIG. 2, and the power supply potential and the drain-source voltage of each transistor are changed when the number of N-channel MOS transistors connected in series is changed. It is the figure which showed the relationship. (A), (b) is an example of a simulation result using the equivalent circuit of FIG. 2, and shows the relationship between the power supply potential and the drain-source voltage of each transistor when the set potential of the support substrate is changed. FIG. It is a figure which shows the equivalent circuit of the semiconductor device 11 shown in FIG. 1 used for simulation in the example of another simulation. (A), (b) is an example of the simulation result using the equivalent circuit of FIG. 5, and the relationship between the power supply potential and the drain-source voltage of each N-channel MOS transistor when the set potential of the support substrate is changed. FIG. (A), (b) is an example of the simulation result using the equivalent circuit of FIG. 5, and the relationship between the power supply potential and the drain-source voltage of each N-channel MOS transistor when the set potential of the support substrate is changed. FIG. (A), (b) is an example of the simulation result using the equivalent circuit of FIG. 5, and the relationship between the power supply potential and the drain-source voltage of each N-channel MOS transistor when the set potential of the support substrate is changed. FIG. It is an example of simulation of a semiconductor device in which a plurality of P-channel MOS transistors are formed, and is a diagram showing an equivalent circuit used for the simulation. FIGS. 9A and 9B are examples of simulation results using the equivalent circuit of FIG. 9, and the power supply potential and the drain-source voltage of each N-channel MOS transistor when the set potential V _sub of the support substrate is changed. FIG. FIGS. 9A and 9B are examples of simulation results using the equivalent circuit of FIG. 9, and the power supply potential and the drain-source voltage of each N-channel MOS transistor when the set potential V _sub of the support substrate is changed. FIG. FIGS. 9A and 9B are examples of simulation results using the equivalent circuit of FIG. 9, and the power supply potential and the drain-source voltage of each N-channel MOS transistor when the set potential V _sub of the support substrate is changed. FIG. It is the figure which showed typically the setting method of the support substrate electric potential. It is the figure which showed typically the setting method of another support substrate electric potential. It is a typical sectional view of conventional high voltage IC90 using SOI substrate and trench isolation. 1 is a basic equivalent circuit diagram of a novel semiconductor device 10. FIG. It is a figure which shows the level shift circuit part and floating reference gate drive circuit part in high voltage IC100 in detail, and is a figure which shows arrangement | positioning of each circuit element of the semiconductor device 10 of FIG. 16 applied to the level shift circuit. It is sectional drawing in the dashed-dotted line AA of FIG. 17, and is a figure which shows the structure of each transistor element.

Explanation of symbols

10, 11 Semiconductor device 11t MOS transistor (LDMOS)
S source D drain G gate Z1 first isolation trench Z2 second isolation trenches Fg, F1 to F6, Fh field region V _E power supply potential V _sub of the support substrate potential R _in the input resistance R _out output resistance R the resistance element 1 SOI Substrate 1a SOI layer 2 Support substrate 3 Buried oxide film 90,100 High voltage IC

Claims (25)

N (n ≧ 2) N-channel MOS transistor elements that are insulated from each other are sequentially arranged between a ground (GND) potential and a predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage. Connected in series,
The gate terminal in the first-stage N-channel MOS transistor element is an input terminal,
n resistance elements and / or capacitive elements are sequentially connected in series between the GND potential and the predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage,
The gate terminals of the N-channel MOS transistor elements in the respective stages excluding the first-stage N-channel MOS transistor element are connected to the connection points between the resistor elements and / or the capacitor elements in the respective stages connected in series. Connected sequentially,
A semiconductor device in which an output is taken out from a terminal on the predetermined potential side in the n-th stage N-channel MOS transistor element,
The n N-channel MOS transistor elements are formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film,
Isolated from each other by the first isolation trenches reaching the buried oxide layer;
The semiconductor device, wherein the support substrate under the buried oxide film is set to a potential not more than 0.8 times the predetermined potential during the operation of the semiconductor device.   2. The semiconductor device according to claim 1, wherein the n N-channel MOS transistor elements have the same breakdown voltage.   3. The semiconductor device according to claim 1, wherein a breakdown voltage of the N channel MOS transistor element is 200 V or less.   The semiconductor device according to claim 3, wherein the n is 6 or less. N is 12 or less,
4. The semiconductor device according to claim 3, wherein the support substrate under the buried oxide film is set to a potential not more than 0.25 times the predetermined potential during operation of the semiconductor device. Second insulating isolation trenches reaching the buried oxide film are formed (n + 2) layers,
Of the field regions composed of (n + 2) SOI layers surrounded by the (n + 2) heavy second insulating isolation trenches, the potential of the field region surrounded by the innermost second insulating isolation trench is: Fixed to the predetermined potential;
Of the field regions composed of (n + 2) SOI layers surrounded by the (n + 2) -thick second insulating isolation trench, the potential of the field region surrounded by the outermost second insulating isolation trench is GND. Fixed to potential,
N-channel MOS transistor elements insulated and separated by the first insulation isolation trenches are respectively formed in the field regions composed of n SOI layers surrounded by the second insulation isolation trench excluding the innermost circumference and the outermost circumference. 6. The semiconductor device according to claim 1, wherein the semiconductor devices are arranged one by one. The potential of the support substrate is a floating potential;
The potential of the support substrate is approximately the ratio of the occupied area of the field region surrounded by the innermost second insulating isolation trench and the occupied area of the field region surrounded by the outermost second insulating isolation trench. The semiconductor device according to claim 6, wherein the semiconductor device is set. The potential of the support substrate is a floating potential;
The potential of the support substrate is approximately the thickness of the buried oxide film immediately below the field region surrounded by the innermost second insulating isolation trench and the field surrounded by the outermost second insulating isolation trench. 7. The semiconductor device according to claim 6, wherein the semiconductor device is set by a ratio of a thickness of the buried oxide film immediately below the region. M (m ≧ 2) P-channel MOS transistor elements that are insulated from each other are sequentially arranged between a predetermined potential and a ground (GND) potential, with the predetermined potential side being the first stage and the GND potential side being the mth stage. Connected in series,
The gate terminal in the first-stage P-channel MOS transistor element is an input terminal,
m resistance elements and / or capacitance elements are sequentially connected in series between the predetermined potential and the GND potential, with the predetermined potential side as the first stage and the GND potential side as the mth stage,
The gate terminals of the P-channel MOS transistor elements of each stage excluding the first-stage P-channel MOS transistor element are respectively connected to the connection points between the resistor elements and / or the capacitor elements of the respective stages connected in series. Connected sequentially,
A semiconductor device in which an output is extracted from a terminal on the GND potential side in the m-th stage P-channel MOS transistor element,
The m P-channel MOS transistor elements are formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film,
Insulated and isolated from each other by a third isolation trench that reaches the buried oxide film,
A semiconductor device, wherein the support substrate under the buried oxide film is set to a potential of 0.8 times or more the predetermined potential during the operation of the semiconductor device.   10. The semiconductor device according to claim 9, wherein the m P-channel MOS transistor elements have the same breakdown voltage.   11. The semiconductor device according to claim 9, wherein a breakdown voltage of the P-channel MOS transistor element is 200 V or less.   The semiconductor device according to claim 11, wherein the m is 6 or less. A fourth insulating isolation trench reaching the buried oxide film is formed (m + 2) layers;
Of the field regions composed of (m + 2) SOI layers surrounded by the (m + 2) -thick fourth insulating isolation trench, the potential of the field region surrounded by the innermost peripheral fourth insulating isolation trench is: Fixed to the predetermined potential;
Of the field regions made up of (m + 2) individual SOI layers surrounded by the (m + 2) heavy fourth insulating isolation trench, the potential of the field region surrounded by the outermost fourth insulating isolation trench is GND. Fixed to potential,
P-channel MOS transistor elements insulated and separated by the third insulation isolation trench are respectively formed in the field regions composed of m SOI layers surrounded by the fourth insulation isolation trench excluding the innermost circumference and the outermost circumference. The semiconductor device according to claim 9, wherein the semiconductor devices are arranged one by one. The potential of the support substrate is a floating potential;
The potential of the support substrate is approximately the ratio of the occupied area of the field region surrounded by the innermost fourth insulating isolation trench and the occupied area of the field region surrounded by the outermost fourth insulating isolation trench. 14. The semiconductor device according to claim 13, wherein the semiconductor device is set. The potential of the support substrate is a floating potential;
The potential of the support substrate is approximately the thickness of the buried oxide film immediately below the field region surrounded by the innermost fourth insulating isolation trench and the field surrounded by the outermost fourth insulating isolation trench. The semiconductor device according to claim 13, wherein the semiconductor device is set by a ratio of a thickness of the buried oxide film immediately below the region. N (n ≧ 2) N-channel MOS transistor elements that are insulated from each other are sequentially arranged between a ground (GND) potential and a predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage. Connected in series,
The gate terminal in the first-stage N-channel MOS transistor element is an input terminal,
n resistance elements and / or capacitive elements are sequentially connected in series between the GND potential and the predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage,
The gate terminals of the N-channel MOS transistor elements in the respective stages excluding the first-stage N-channel MOS transistor element are connected to the connection points between the resistor elements and / or the capacitor elements in the respective stages connected in series. Connected sequentially,
An output is taken out from the terminal on the predetermined potential side in the n-th stage N-channel MOS transistor element,
M (m ≧ 2) P-channel MOS transistor elements that are isolated from each other have a predetermined potential side as a first stage and a GND potential side as an mth stage between the predetermined potential and the ground (GND) potential, Connected in series,
The gate terminal in the first-stage P-channel MOS transistor element is an input terminal,
m resistance elements and / or capacitance elements are sequentially connected in series between the predetermined potential and the GND potential, with the predetermined potential side being the first stage and the GND potential side being the mth stage,
The gate terminals of the P-channel MOS transistor elements of each stage excluding the first-stage P-channel MOS transistor element are respectively connected to the connection points between the resistor elements and / or the capacitor elements of the respective stages connected in series. Connected sequentially,
An output is taken out from the terminal on the GND potential side in the m-th stage P-channel MOS transistor element,
The n N-channel MOS transistor elements and the m P-channel MOS transistor elements are respectively formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film.
The n N-channel MOS transistor elements are insulated from each other by a first insulation isolation trench reaching the buried oxide film,
The m P-channel MOS transistor elements are insulated from each other by a third insulation isolation trench reaching the buried oxide film,
A semiconductor device, wherein the support substrate under the buried oxide film is set to a potential not less than 0.7 times and not more than 0.9 times the predetermined potential during operation of the semiconductor device. The n N-channel MOS transistor elements have the same breakdown voltage;
The semiconductor device according to claim 16, wherein the m P-channel MOS transistor elements have the same breakdown voltage.   18. The semiconductor device according to claim 16, wherein a breakdown voltage of the N channel MOS transistor element and the P channel MOS transistor element is 200 V or less. N and m are 6 or less,
19. The semiconductor device according to claim 18, wherein the support substrate under the buried oxide film is set to a potential that is approximately 0.8 times the predetermined potential during the operation of the semiconductor device. Second insulating isolation trenches reaching the buried oxide film are formed (n + 2) layers,
Of the field regions composed of (n + 2) SOI layers surrounded by the (n + 2) heavy second insulating isolation trenches, the potential of the field region surrounded by the innermost second insulating isolation trench is: Fixed to the predetermined potential;
Of the field regions composed of (n + 2) OI layers surrounded by the (n + 2) -thick second insulating isolation trench, the potential of the field region surrounded by the outermost second insulating isolation trench is GND. Fixed to potential,
N-channel MOS transistor elements insulated and separated by the first insulation isolation trenches are respectively formed in the field regions composed of n SOI layers surrounded by the second insulation isolation trench excluding the innermost circumference and the outermost circumference. One by one,
A fourth insulating isolation trench reaching the buried oxide film is formed (m + 2) layers;
Of the field regions composed of (m + 2) SOI layers surrounded by the (m + 2) -thick fourth insulating isolation trench, the potential of the field region surrounded by the innermost peripheral fourth insulating isolation trench is: Fixed to the predetermined potential;
Of the field regions composed of (m + 2) SOI layers surrounded by the (m + 2) heavy fourth insulating isolation trench, the potential of the field region surrounded by the outermost fourth insulating isolation trench is GND. Fixed to potential,
P-channel MOS transistor elements insulated and separated by the third insulation isolation trench are respectively formed in the field regions composed of m SOI layers surrounded by the fourth insulation isolation trench excluding the innermost circumference and the outermost circumference. 20. The semiconductor device according to claim 16, wherein the semiconductor devices are arranged one by one. The potential of the support substrate is a floating potential;
The potential of the support substrate is approximately the sum of the occupied area of the field region surrounded by the innermost second insulating isolation trench and the occupied area of the field region surrounded by the innermost fourth insulating isolation trench. And the ratio of the occupied area of the field region surrounded by the outermost second insulating isolation trench and the sum of the occupied area of the field region surrounded by the outermost fourth insulating isolation trench. The semiconductor device according to claim 20. The potential of the support substrate is a floating potential;
The potential of the support substrate is substantially surrounded by the thickness of the buried oxide film immediately below the field region surrounded by the innermost second insulating isolation trench and the innermost fourth insulating isolation trench. The thickness of the buried oxide film immediately below the field region, the thickness of the buried oxide film immediately below the field region surrounded by the second outermost isolation trench, and the fourth outermost isolation trench 21. The semiconductor device according to claim 20, wherein the semiconductor device is set by a ratio of the thickness of the buried oxide film immediately below the enclosed field region. The semiconductor device is
An inverter having a GND reference gate drive circuit based on the GND potential, a floating reference gate drive circuit based on the floating potential, and a level shift circuit for level-shifting an input / output signal between the GND potential and the floating potential In high voltage IC for driving,
23. The semiconductor device according to claim 1, wherein the semiconductor device is applied to the level shift circuit with the predetermined potential as a floating potential.   24. The semiconductor device according to claim 23, wherein the high voltage IC is a high voltage IC for driving an inverter of an in-vehicle motor.   24. The semiconductor device according to claim 23, wherein the high voltage IC is a high voltage IC for driving an inverter of an in-vehicle air conditioner.

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