JP4967498B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device applicable to a high voltage IC for driving an inverter or the like.

  High voltage ICs for driving an inverter are disclosed in, for example, Japanese Patent No. 3384399 (Patent Document 1) and Proc. Of ISPSD'04 (Non-Patent Document 1). A high voltage IC that is suitable for controlling motors for automobiles such as electric vehicles (EV) and hybrid (HEV) vehicles that require a particularly high withstand voltage (about 1200 V) and that can comprehensively cover a withstand voltage of 150 V to 1200 V is disclosed in JP-A-2006. -148058 (patent document 2).

  FIG. 14 is a basic equivalent circuit diagram of the semiconductor device 10 of the semiconductor device disclosed in Patent Document 2 used in the high voltage IC of the inverter driving circuit.

In the semiconductor device 10 shown in FIG. 14, the MOS transistor elements _Tr 1 to Tr _n of n that are insulated and separated from each other (n ≧ 2), between the ground (GND) potential and the predetermined potential Vs, the GND potential The first stage is sequentially connected in series with the predetermined potential Vs side being the nth stage. The gate terminal of the first-stage MOS transistor element Tr ₁ is an input terminal of the semiconductor device 10. The output of the semiconductor device 10 is taken out from a terminal on the predetermined potential Vs side in the n-th stage MOS transistor element Tr _n via a load resistor (not shown) having a predetermined resistance value. The output signal is extracted in a state where the reference potential is converted (level shift) from the GND potential of the input signal to the predetermined potential Vs and inverted with respect to the input signal.

In the operation of the semiconductor device 10 of FIG. 14, the voltage between the GND potential and the predetermined potential Vs is divided by _n MOS transistor elements Tr _{1 to} Tr n, and the MOS transistor elements Tr from the first stage to the n-th stage are divided. ₁ to Tr _n has shared a respective voltage range. Therefore, the breakdown voltage required for each of the MOS transistor elements Tr _{1 to} Tr _n is approximately ₁ / _n compared to the case where the voltage between the GND potential and the predetermined potential Vs is shared by _one MOS transistor element. . Accordingly, even a MOS transistor element having a normal withstand voltage that can be manufactured at low cost using a general manufacturing method is necessary as a whole by appropriately setting the number n of MOS transistor elements in the semiconductor device 10 of FIG. Therefore, the semiconductor device can ensure a high breakdown voltage.

  FIG. 15 is a diagram showing in detail the level shift circuit section and floating reference gate drive circuit section of the high voltage IC disclosed in Patent Document 2, and is the basic structure of FIG. 14 applied to the level shift circuit of the high voltage IC 100. FIG. 3 is a diagram illustrating an arrangement of circuit elements of the semiconductor device 10 illustrated in an equivalent circuit diagram. FIG. 16 is a cross-sectional view taken along one-dot chain line AA in FIG. 15 and shows the structure of each MOS transistor element.

As shown in the sectional view of FIG. 16, the high voltage IC 100, n pieces of MOS transistor elements _Tr 1 to Tr _n in the semiconductor device 10 of FIG. 14 which is applied to the level shift circuit, SOI having a buried oxide film 3 structure It is formed on the n-conductivity type SOI layer 1 a of the semiconductor substrate 1. Under the buried oxide film 3 is a thick support substrate 2 made of silicon (Si), and the SOI substrate 1 is formed by bonding the substrates.

The n MOS transistor elements Tr _{1 to} Tr _n are lateral MOS (Lateral Diffused Metal Oxide Semiconductor) transistor elements, and are isolated from each other by an insulating isolation trench 4 that reaches the buried oxide film 3. In the semiconductor device 10 shown in FIG. 16, a high-concentration impurity layer 1b is formed on the buried oxide film 3 in the SOI layer 1a in order to shield high-frequency potential interference caused by switching in the floating reference gate drive circuit. Yes.

As shown in FIG. 15, in the semiconductor device 10 of the high voltage IC100 is, n heavy isolated separating trenches _T 1 through T _n are formed, are n MOS transistor elements _Tr 1 to Tr _n, which are insulated and separated from each other, In each field region surrounded by n-fold insulating isolation trenches T _{1 to} T _n , one by one is sequentially arranged so as to include high-stage MOS transistor elements therein.

  FIG. 17 is a schematic top view showing a configuration of a main part of the semiconductor device 11 in which the semiconductor device 10 shown in FIGS. 14 and 15 is simplified.

  The semiconductor device 11 shown in FIG. 17 uses an SOI substrate having a buried oxide film, and six lateral MOS (LDMOS) transistor elements Tr are formed in the SOI layer on the buried oxide film. Each MOS transistor element Tr has a pattern in which a drain D, a gate G, and a source S are arranged concentrically as shown in the figure. Each MOS transistor element Tr is surrounded and surrounded by a first insulating isolation trench Z1 reaching the buried oxide film, which is indicated by a thick solid line circle in the drawing.

  In the semiconductor device 11 of FIG. 17, the second insulating isolation trenches Z2 indicated by thick solid squares in the same figure reaching the buried oxide film are formed in multiple. Each MOS transistor element Tr insulated and separated by the first insulation isolation trench Z1 is arranged one by one in each field region F1 to F6 surrounded by the multiple second insulation isolation trenches Z2. In the field region F6, a high voltage (HV) circuit, a power supply pad, an output pad, and the like are formed. In a region outside the field region F1, a ground (GND) pad, an input pad, and the like are formed. Yes.

In the semiconductor device 11 of FIG. 17, the six MOS transistor elements Tr are arranged between the ground (GND) potential and a predetermined power supply potential so that the outer peripheral side of the six-fold second isolation trench Z2 is connected to the GND potential side. One stage is connected in series with the inner peripheral side as the sixth stage on the power supply potential side. Reference sign _Rout is an output resistance. In the semiconductor device 11, the gate terminal in the first-stage MOS transistor element Tr is used as an input terminal. Further, an output resistor R _out is connected between the sixth-stage MOS transistor element Tr and the power supply pad, and an output is taken _out between the terminal on the power supply potential side of the sixth-stage MOS transistor element Tr and the output resistor R _out . In the semiconductor device 11, the resistor elements R formed of thin films are connected in series in multiple stages, the GND potential and the power supply potential are divided, and the gates of the MOS transistor elements Tr in the second and subsequent stages are connected to the branch points of the series connection. It is connected to the.
Japanese Patent No. 3384399 Proc. Of ISPSD '04, p385, H. Akiyama, et al (Mitsubishi Electric) JP 2006-148058 A

In the semiconductor devices 10 and 11 shown in FIGS. 14 to 17, the voltage applied to each field region surrounded by the n-fold insulating isolation trenches is equalized in accordance with the increase in voltage from the GND potential to a predetermined power supply potential, and n The assigned voltage range of each of the MOS transistor elements Tr (Tr _{1 to} Tr _n ) can be sequentially shifted from the GND potential toward a predetermined power supply potential. In addition, since there is only one n-fold insulation isolation trench T _{1 to} T _n between adjacent MOS transistor elements, connection of _n MOS transistor elements Tr (Tr _{1 to} Tr _n ). Wiring becomes easy and the occupied area can be reduced to reduce the size of the semiconductor devices 10 and 11.

As described above, in the semiconductor devices 10 and 11, the n MOS transistor elements Tr (Tr _{1 to} Tr _n ) may be MOS transistor elements having a normal withstand voltage. Accordingly, the high voltage IC 100 shown in FIGS. 15 and 16 can ensure a withstand voltage of 1200 V, and is a high voltage IC suitable for driving an inverter of an in-vehicle motor or an inverter of an in-vehicle air conditioner.

On the other hand, in the semiconductor devices 10 and 11 shown in FIGS. 14 to 17, it is necessary to always pass a weak current through the voltage _dividing resistor R (R _{1 to} R _n ). Since a high power supply voltage is applied to the line of the resistors R (R _{1 to} R _n ) connected in series between the GND potential and a predetermined power supply potential, a current (leakage) current flows through the line in a steady state and is consumed. There is a problem that electric power becomes large. In order to reduce the leakage current and reduce the power consumption, it is necessary to increase the resistance value of the voltage dividing resistor R (R _{1 to} R _n ) to about 2 to 14 MΩ. For this reason, the occupation area of the resistance elements R (R _{1 to} R _n ) increases, and the chip size of the integrated circuit increases.

  Therefore, the present invention is a semiconductor device in which n (n ≧ 2) MOS transistor elements that are insulated from each other are sequentially connected in series, and can ensure a high breakdown voltage required as a whole, and can be compact. An object of the present invention is to provide a semiconductor device with low power consumption.

The semiconductor device according to claim 1, wherein n (n ≧ 2) MOS transistor elements that are insulated from each other are arranged between a ground (GND) potential and a predetermined potential, and the GND potential side is a first stage. The n-th potential side is sequentially connected in series, the gate terminal in the first-stage MOS transistor element is used as an input terminal, and n-sources are formed so as to be conductive between the source and drain without gate input. Short-circuit MOS transistor elements are sequentially connected in series between the GND potential and the predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage, except for the first-stage MOS transistor element. The gate terminals of the MOS transistor elements at each stage are sequentially connected between the short-circuit MOS transistor elements at each stage connected in series, and the n-th stage MO From the predetermined potential side terminal of the transistor element, a semiconductor device comprising an output is taken out, the short MOS transistor element is constituted by a gate electrode which is in a floating state, electric charge in the gate electrode are injected In this state, the source and the drain are formed to be conductive, the gate electrode is connected to the floating second gate electrode formed on the tunnel oxide film, and the second gate electrode is It is characterized by being connected to a pad electrode in a floating state formed on the substrate .

The short-circuit MOS transistor element formed so as to be conductive between the source and drain without the gate input in the semiconductor device can function as a high resistance element. For this reason, in the semiconductor device, the gate voltage dividing circuit of the MOS transistor elements of the main line sequentially connected in series between the GND potential and the predetermined potential is similarly a high resistance connected in series between the GND potential and the predetermined potential. It is composed of a short-circuit MOS transistor element that functions as an element. With this short-circuit MOS transistor element that functions as a high-resistance element, the semiconductor device can suppress a (leakage) current in a steady state that flows through the gate voltage dividing circuit line, thereby reducing power consumption. . Further, the area of the short-circuit MOS transistor element in the chip is much smaller than that of a conventional resistance element formed of a thin film, and this does not increase the cost.
In the semiconductor device, the short-circuit MOS transistor element has a gate electrode in a floating state, and the source and the drain are formed to be conductive in a state where charges are injected into the gate electrode. It has become. As a result, a short-circuit MOS transistor element (high resistance element) having a desired high resistance value in a wide range is realized by injecting charge into the floating gate electrode and appropriately setting the amount of charge to be injected. be able to.
In the semiconductor device, the gate electrode is connected to a floating second gate electrode formed on the tunnel oxide film in order to stably control the amount of charge injected into the gate electrode. The second gate electrode is connected to a pad electrode in a floating state formed on the substrate.

  In the semiconductor device, as in the case where the conventional thin film resistor element is used in the gate voltage dividing circuit, an input signal is applied to the gate terminal of the first-stage MOS transistor element, so that the n short-circuit MOS transistor elements can be obtained. Thus, the second-stage to n-th stage MOS transistor elements can be operated simultaneously. In the semiconductor device, the voltage between the GND potential and the predetermined potential is divided by n MOS transistor elements, and each MOS transistor element from the first stage to the n-th stage shares a voltage range. . Therefore, the breakdown voltage required for each MOS transistor element can be reduced as compared with the case where the voltage between the GND potential and the predetermined potential is shared by one MOS transistor element.

  As described above, the semiconductor device is a semiconductor device in which n (n ≧ 2) MOS transistor elements that are insulated and separated from each other are sequentially connected in series, and the high breakdown voltage required as a whole is ensured. Therefore, a small and inexpensive semiconductor device with low power consumption can be obtained.

  According to a second aspect of the present invention, in the semiconductor device, the MOS transistor element and the short-circuit MOS transistor element preferably have the same cross-sectional structure in the channel length direction.

  In the semiconductor device in which the GND potential and the predetermined potential are divided and shared by the MOS transistor elements at each stage of the main line, generally, the gate voltage dividing circuit line together with the breakdown voltage of the MOS transistor elements at each stage constituting the main line. Each of the short-circuit MOS transistor elements (high-resistance elements) constituting the same voltage needs to have the same withstand voltage.

  On the other hand, the breakdown voltage of the MOS transistor element is generally determined by the cross-sectional structure in the channel length direction. For this reason, by making the cross-sectional structure in the channel length direction of the MOS transistor element in the main line and the short-circuit MOS transistor element in the gate voltage dividing circuit line the same, the withstand voltage design is simplified and the withstand voltage characteristics of both elements are improved. Can be matched exactly. Also, in each line, since the breakdown voltage of each element constituting it is equal, the voltage (withstand voltage) shared by each element inserted between the GND potential and a predetermined potential must be equalized and minimized. Can do.

  Further, the above-described semiconductor device in which the main line and the gate voltage dividing circuit line are basically composed of the MOS transistor element and the short-circuit MOS transistor element having the same cross-sectional structure has a very simple manufacturing process. That is, the formation of the MOS transistor element and the short-circuit MOS transistor element in the semiconductor device can be largely covered by a common process. For example, the MOS transistor element and the short-circuit MOS transistor element can be made separately by only making the threshold voltage adjustment process different. Accordingly, the manufacture of the semiconductor device has a small number of processes and is easy to manage, and the semiconductor device can be manufactured at low cost.

  In the semiconductor device, for example, as described in claim 3, the MOS transistor element and the short-circuit MOS transistor element may be a horizontal type or a vertical type as described in claim 4. Also good.

6. The insulating isolation trench according to claim 5 , wherein the MOS transistor element and the short-circuit MOS transistor element in the semiconductor device are formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film and reach the buried oxide film. Therefore, it can be configured to be insulated and separated from each other.

In this case, as described in claim 6 , n-layer insulation isolation trenches reaching the buried oxide film are formed, and the n MOS transistor elements isolated from each other are separated by the n-layer insulation isolation trenches. It is preferable that each of the enclosed regions is sequentially arranged one by one so as to include high-stage MOS transistor elements therein. In addition, as described in claim 7 , the n short-circuited MOS transistor elements isolated from each other are also provided with a high-stage short-circuited MOS transistor element in each region surrounded by the n-fold insulated isolation trenches. It is preferable that they are sequentially arranged one by one so as to be included.

  This equalizes the voltage applied to each region surrounded by the n-fold insulation isolation trench in accordance with the voltage increase from the GND potential to the predetermined potential, and the voltage ranges assigned to the n MOS transistor elements and the short MOS transistor elements Can be sequentially shifted from the GND potential toward the predetermined potential. Since there is only one n-fold isolation trench between adjacent insulated MOS transistor elements and between adjacent insulated short-circuit MOS transistor elements, n MOS transistors The connection wiring of the elements and the connection wiring of the n short-circuit MOS transistor elements can be facilitated, the occupied area can be reduced, and the semiconductor device can be downsized.

In this case, for example, as described in claim 8 , the n short-circuit MOS transistor elements may be divided into a plurality of parts. This makes it possible to set the desired high resistance value of each stage of the short-circuit MOS transistor element (high resistance element) in a simple, precise and wide range by appropriately connecting the divided elements formed in a plurality of lines. Is possible.

As described in claim 9, wherein the semiconductor device, GND reference gate drive circuit referenced to GND potential, the floating reference gate drive circuit referenced to a floating potential, the floating reference gate drive to the GND reference gate drive circuit A control circuit for controlling the circuit, and a level shift circuit which is interposed between the control circuit and the floating reference gate drive circuit and shifts an input / output signal of the control circuit between the GND potential and the floating potential. The inverter-driven high voltage IC is suitable for the level shift circuit. In this case, the predetermined potential becomes the floating potential.

It said high voltage IC includes, for example, as described in claim 1 0, may be a high voltage IC for inverter drive of the in-vehicle motor, as described in claim 1 1, vehicle air conditioner inverter drive It may be a high voltage IC.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic top view showing a configuration of a main part of a semiconductor device 20, which is an example of a semiconductor device which is not the present invention but is a reference . 2A and 2B are schematic cross-sectional views of the MOS transistor element Tr and the short-circuit MOS transistor element RTr1 in the semiconductor device 20, respectively. FIGS. 3A and 3B are diagrams showing gate voltage-drain current (Vg-Id) characteristics with respect to the MOS transistor element Tr and the short-circuit MOS transistor element RTr1, respectively.

In the semiconductor device 20 of FIG. 1, the same parts as those of the conventional semiconductor device 11 shown in FIG. Further, the SOI substrate 1 in FIG. 2 corresponds to the SOI substrate 1 in FIG. 16, and the corresponding parts are denoted by the same reference numerals. In FIG. 2, the high-concentration impurity layer 1b is not shown on the buried oxide film 3, but the high-concentration impurity layer 1b may or may not be present. Further, the insulating isolation trench Z1 surrounding the MOS transistor element Tr and the short-circuit MOS transistor element RTr1 shown in FIGS. 1 and 2 is an insulating isolation trench surrounding the MOS transistor elements Tr _{1 to} Tr _n shown by reference numeral 4 in FIG. It corresponds.

  A semiconductor device 20 shown in FIG. 1 is a short-circuit MOS transistor in which a resistance element R formed of a thin film in the conventional semiconductor device 11 shown in FIG. 17 is formed to be conductive between a source and a drain without a gate input. The structure is replaced with the element RTr1.

  That is, the semiconductor device 20 shown in FIG. 1 uses the SOI substrate 1 having the buried oxide film 3 shown in FIG. 2 as in the semiconductor device 11 shown in FIG. N-channel lateral MOS (LDMOS) transistor element Tr shown in FIG. 2 is formed in SOI layer 1a on buried oxide film 3. Each MOS transistor element Tr has a pattern in which a drain D, a gate G, and a source S are arranged concentrically as shown in FIG. Each MOS transistor element Tr is surrounded by a first insulating isolation trench Z1 reaching the buried oxide film 3 shown in FIG. 2A, which is indicated by a thick solid circle in FIG. ing.

  In the semiconductor device 20, the second insulating isolation trenches Z <b> 2 indicated by thick solid squares in FIG. 1 that reach the buried oxide film 3 are formed in multiple. Each MOS transistor element Tr insulated and separated by the first insulation isolation trench Z1 is arranged one by one in each field region F1 to F6 surrounded by the multiple second insulation isolation trenches Z2. In the field region F6, a high voltage (HV) circuit, a power supply pad, an output pad, and the like are formed. In a region outside the field region F1, a ground (GND) pad, an input pad, and the like are formed. Yes.

In the semiconductor device 20, the six MOS transistor elements Tr are arranged between the ground (GND) potential and a predetermined power supply potential so that the outer periphery of the six-fold second isolation trench Z <b> 2 is the first potential on the GND potential side. The stages and the inner periphery side are sequentially connected in series with the sixth stage on the power supply potential side. Reference numeral _{R out} in Figure 1 is the output resistance. In the semiconductor device 20, the gate terminal in the first-stage MOS transistor element Tr is used as an input terminal. Further, an output resistor R _out is connected between the sixth-stage MOS transistor element Tr and the power supply pad, and an output is taken _out between the terminal on the power supply potential side of the sixth-stage MOS transistor element Tr and the output resistor R _out .

  On the other hand, the semiconductor device 20 shown in FIG. 1 is different from the conventional semiconductor device 11 shown in FIG. 17 in that the short-circuit MOS transistor elements RTr1 formed so as to be conductive between the source and drain without any gate input are connected in series. As a result, the GND potential and the power supply potential are divided, and the gates of the MOS transistor elements Tr in the second and subsequent stages are connected to each branch point of the series connection.

Although the short-circuit MOS transistor element RTr1 in the semiconductor device 20 of FIG. 1 is not the short-circuit MOS transistor element in the semiconductor device of the present invention, as shown in FIG. 2B, the MOS transistor element Tr shown in FIG. Although they have the same cross-sectional structure in the channel length direction, they are adjusted to have different threshold voltages in the threshold voltage adjustment step. That is, the N-channel MOS transistor element Tr shown in FIG. 2A adjusts the threshold voltage Vt by ion-implanting P-conductivity type impurities into the channel region. As a result, as shown in FIG. 3A, a normal Vg-Id characteristic having a positive threshold voltage Vt0 is obtained. On the other hand, in the N-channel short-circuit MOS transistor element RTr1 shown in FIG. 2B, a large amount of N-conductivity type impurities are ion-implanted into the channel region immediately below the gate G in the threshold voltage adjustment step. Therefore, in the short-circuit MOS transistor element RTr1, as shown in FIG. 2B, a high-resistance short-circuit channel (inversion layer channel) n1 is formed in the channel region. As a result, as shown in FIG. 3B, the short-circuit MOS transistor element RTr1 has a threshold voltage Vt1 lower than the threshold voltage Vt0 of the MOS transistor element Tr, and the weak current Id1 is reduced even at the gate voltage Vg = 0V. Flowing. That is, the source and drain are formed to be conductive when the gate voltage with respect to the source S is 0 V, thereby enabling the source and drain to be conductive without a gate input.

The threshold voltage adjusting process for the MOS transistor element Tr and the short-circuit MOS transistor element RTr1 can be performed, for example, between the LOCOS and gate oxide film forming process and the polysilicon gate electrode forming process. When adjusting the threshold voltage of one of the MOS transistor element Tr and the short-circuit MOS transistor element RTr1, the other is masked with a resist and ion implantation is performed. When adjusting the threshold voltage of the normal N-channel MOS transistor element Tr shown in FIG. 2A, for example, boron (B +) is ion-implanted as a P conductivity type impurity. On the other hand, when adjusting the threshold voltage of the N-channel short-circuit MOS transistor element RTr1 shown in FIG. 2B, for example, phosphorus (P +) is used as an N-conductivity type impurity with an acceleration voltage of 30 kV and a dose of 1.3 × 10 ^13. A large amount of ions are implanted at about / cm ² .

  The short-circuit MOS transistor element RTr1 formed between the source and the drain so as to be conductive without a gate input in the semiconductor device 20 of FIG. 1 can function as a high resistance element as described above. For this reason, in the semiconductor device 20, the gate voltage dividing circuit of the MOS transistor element Tr in the main line sequentially connected in series between the GND potential and the predetermined potential is similarly connected to the high potential connected in series in series between the GND potential and the predetermined potential. The short-circuit MOS transistor element RTr1 functioning as a resistance element is formed. With this short-circuit MOS transistor element RTr1 functioning as a high resistance element, the semiconductor device 20 can suppress a (leakage) current in a steady state flowing through the gate voltage dividing circuit line, thereby reducing power consumption. it can. Further, the area occupied by the short MOS transistor element RTr1 in the chip is much smaller than the resistance element R formed of the conventional thin film shown in FIG. 17, and this does not increase the cost.

  Also in the semiconductor device 20 of FIG. 1, the input to the gate terminal of the first-stage MOS transistor element Tr is the same as the semiconductor device 11 using the conventional thin film resistor element R shown in FIG. 17 in the gate voltage dividing circuit. By applying a signal, the second to n-th stage MOS transistor elements Tr can be simultaneously operated via the n short-circuit MOS transistor elements RTr1. Also in the semiconductor device 20 of FIG. 1, similarly to the semiconductor device 11 of FIG. 17, the voltage between the GND potential and the predetermined potential is divided by the n MOS transistor elements Tr, and the first to n-th stages are divided. Each MOS transistor element Tr shares its voltage range. Therefore, the breakdown voltage required for each MOS transistor element Tr can be reduced as compared with the case where the voltage between the GND potential and the predetermined potential is shared by one MOS transistor element. Since there is only one n-fold insulation isolation trench Z2 between adjacent insulated MOS transistor elements Tr and between adjacent insulated MOS transistor elements RTr1, n The connection wiring of the MOS transistor element Tr and the connection wiring of the n short-circuit MOS transistor elements RTr1 can be facilitated, and the occupied area can be reduced and the size can be reduced.

  As described above, the semiconductor device 20 shown in FIG. 1 is a semiconductor device in which n (n ≧ 2) MOS transistor elements Tr that are insulated and separated from each other are sequentially connected in series, and is required as a whole. A high breakdown voltage can be ensured, power consumption is small, and a small and inexpensive semiconductor device can be obtained.

  In the semiconductor device 20, as described above, the MOS transistor element Tr and the short-circuit MOS transistor element RTr1 have the same cross-sectional structure in the channel length direction. In a semiconductor device in which the GND potential and the predetermined potential are divided and shared by the MOS transistor elements at each stage of the main line, generally, the gate voltage dividing circuit line is set together with the breakdown voltage of the MOS transistor elements at each stage constituting the main line. The same breakdown voltage is required for each short-circuit MOS transistor element (high resistance element) to be configured. On the other hand, the breakdown voltage of the MOS transistor element is generally determined by the cross-sectional structure in the channel length direction. Therefore, the withstand voltage design is simplified by making the cross-sectional structures in the channel length direction of the MOS transistor element Tr of the main line and the short-circuit MOS transistor element RTr1 of the gate voltage dividing circuit line the same as in the semiconductor device 20. In addition, the breakdown voltage characteristics of the two elements Tr and RTr1 can be matched accurately. Also, in each line, since the breakdown voltage of each element Tr and RTr1 constituting the same is equal, the voltage (withstand voltage) shared by each element Tr and RTr1 inserted between the GND potential and the predetermined potential is equalized. Can be minimized.

  Furthermore, the manufacturing process of the semiconductor device 20 including the MOS transistor element Tr and the short-circuit MOS transistor element RTr1 in which the main line and the gate voltage dividing circuit line are basically the same in cross-sectional structure is very simple. In other words, the formation of the MOS transistor element Tr and the short-circuit MOS transistor element RTr1 in the semiconductor device 20 can be largely covered by a common process. For example, the MOS transistor element Tr and the short-circuit MOS transistor element RTr1 can be made different from each other by only making the threshold voltage adjustment process different as described above. Therefore, the manufacture of the semiconductor device 20 has a small number of processes and easy process management, and the semiconductor device 20 can be manufactured at low cost.

  In the semiconductor device 20, as described above, impurities are ion-implanted to adjust the threshold voltage of the short-circuit MOS transistor element RTr1. Therefore, by appropriately setting the ion implantation amount, it is possible to realize a short-circuit MOS transistor element (high resistance element) RTr1 having a desired wide range of high resistance values.

  FIG. 4 is a diagram showing gate voltage-drain current (Vg-Id) characteristics when the threshold voltage of the short-circuit MOS transistor element RTr1 is changed by changing the ion implantation amount. As the impurity ion implantation amount increases, the Vg-Id characteristic shifts to the left as shown by the white arrow in the figure, the threshold voltage decreases from Vt1a to Vt1b, and the short-circuit MOS transistor element having a low resistance value (High resistance element) RTr1. In other words, the short-circuit MOS transistor element (high resistance element) RTr1 having a high resistance value can be obtained by reducing the impurity ion implantation amount as much as possible. In the semiconductor device 20 of FIG. 1, all of the six short-circuit MOS transistor elements (high resistance elements) RTr1 may have the same resistance value. However, the present invention is not limited to this, and the ion implantation amount for each of the six short-circuit MOS transistor elements RTr1 may be changed using the characteristics shown in FIG. 4 to have different resistance values. Thereby, for example, the response of the MOS transistor element Tr at each stage to a fast surge such as a dV / dt surge can be equalized.

  FIG. 5 is a schematic cross-sectional view of a more preferred short-circuit MOS transistor element RTr1a that can be used in the configuration of the semiconductor device 20 of FIG. 1 in combination with the MOS transistor element Tr of FIG.

  The short-circuit MOS transistor element RTr1a of FIG. 5 is different from the short-circuit MOS transistor element RTr1 shown in FIG. 2B in that the wiring of the source electrode S is connected to the gate electrode Ga. As described above, the short-circuit MOS transistor element RTr1 shown in FIG. 2B is formed to be conductive between the source and the drain while the gate voltage with respect to the source is 0V. Therefore, like the short-circuit MOS transistor element RTr1a of FIG. 5, the gate Ga and the source Sa are short-circuited to each other, so that the state where the gate voltage with respect to the source is 0V can be stabilized. For this reason, the resistance value of the short-circuit MOS transistor element RTr1a that functions as a high-resistance element is also stable. In FIG. 1 showing the configuration of the main part of the semiconductor device 20, the gate G and the source S of each short-circuit MOS transistor element RTr1 are connected by wiring and are short-circuited to each other.

  6A and 6B are schematic cross-sectional views of another MOS transistor element Trb and a short-circuit MOS transistor element RTr1b that can be applied to the configuration of the semiconductor device 20 of FIG. 6A and 6B, the MOS transistor element Trb and the short-circuit MOS transistor element RTr1b shown in FIGS. 6A and 6B are the same as the MOS transistor element Tr and the short-circuit MOS transistor element RTr1 shown in FIGS. About the part, the same code | symbol was attached | subjected.

  The MOS transistor element Tr and the short-circuit MOS transistor element RTr1 shown in FIGS. 2A and 2B are horizontal elements having the same cross-sectional structure in the channel length direction. In contrast, in the MOS transistor element Trb and the short-circuit MOS transistor element RTr1b shown in FIGS. 6A and 6B, the source Sb is arranged on both sides of the gate Gb, and the drain Db is arranged outside the source Sb. Thus, the vertical element flows in the vertical direction of the SOI layer 1a. The MOS transistor element Trb and the short-circuit MOS transistor element RTr1b in FIGS. 6A and 6B are also adjusted to have different threshold voltages in the threshold voltage adjustment step, but have the same cross section in the channel length direction. It has a structure. In the vertical short-circuit MOS transistor element RTr1b shown in FIG. 6B, not only the adjustment of the threshold voltage but also the width w of the gate electrode Gb shown in FIG. It is also possible to adjust the resistance value of the element RTr1b. That is, as the width w of the gate electrode Gb shown in the figure is reduced, the conductive path of carriers flowing out from the left and right high-resistance short-circuit channels n1 is narrowed, so that a higher-resistance short-circuit MOS transistor element (high-resistance element) RTr1b. Furthermore, since the current path is directed downward, the injection of hot carriers into the gate Gb is suppressed, and as a result, characteristic fluctuations are suppressed. Further, since the current path is formed inside the semiconductor, it is possible to reduce the influence from the outside such as contamination by movable ions such as Na, and to stabilize the element characteristics.

  As described above, the MOS transistor element and the short-circuit MOS transistor element applicable to the configuration of the semiconductor device 20 of FIG. 1 may be a horizontal type or a vertical type.

Next, an example of a semiconductor device on which the present invention is based will be shown.

  FIG. 7 is a schematic top view showing the main configuration of the semiconductor device 21. FIG. 8 is a schematic cross-sectional view of the short-circuit MOS transistor element RTr2 in the semiconductor device 21. FIG. 9 is a diagram showing a gate voltage-drain current (Vg-Id) characteristic regarding the short-circuit MOS transistor element RTr2. In the semiconductor device 21 shown in FIG. 7 and the short-circuit MOS transistor element RTr2 shown in FIG. 8, the same portions as those of the semiconductor device 21 shown in FIG. 1 and the short-circuit MOS transistor element RTr1 shown in FIG. The same reference numerals are attached.

  The MOS transistor element Tr used in the configuration of the semiconductor device 21 in FIG. 7 is the same as the MOS transistor element Tr used in the configuration of the semiconductor device 20 in FIG. 1, and the cross section shown in FIG. The structure and the Vg-Id characteristic shown in FIG. Further, the MOS transistor element Tr shown in FIG. 2A and the short-circuit MOS transistor element RTr2 shown in FIG. 8 have the same cross-sectional structure in the channel length direction.

  The semiconductor device 21 shown in FIG. 7 has a configuration in which the short-circuit MOS transistor element RTr1 in the semiconductor device 20 shown in FIG. 1 is replaced with another short-circuit MOS transistor element RTr2. Similarly to the short-circuit MOS transistor element RTr1 shown in FIGS. 1 and 2A, the short-circuit MOS transistor element RTr2 shown in FIG. 7 and FIG. 8 is formed to be conductive between the source and drain without any gate input. It is a short-circuit MOS transistor element.

  On the other hand, in the short-circuit MOS transistor element RTr1 shown in FIGS. 1 and 2A, the threshold voltage is adjusted, and the source-drain is formed to be conductive while the gate voltage with respect to the source is 0V. On the other hand, the short-circuit MOS transistor element RTr2 shown in FIGS. 7 and 8 has the gate electrode Gc in a floating state. FIG. 7 showing the configuration of the main part of the semiconductor device 21 shows that the gate Gc of each short-circuit MOS transistor element RTr2 is not connected to another wiring and is in a floating state.

  The short-circuit MOS transistor element RTr2 shown in FIG. 7 and FIG. 8 is capable of conducting between source and drain in a state where charges (holes) h indicated by + circles are injected into the gate electrode Gc made of polysilicon. Is formed. That is, in the short-circuit MOS transistor element RTr2 of FIG. 8, the charge (hole) h is injected into the floating gate electrode Gc, whereby the n-conductivity type carriers in the channel region are attracted near the gate electrode Gc. As a result, in the short-circuit MOS transistor element RTr2 of FIG. 8, the threshold voltage of the short-circuit MOS transistor element RTr1 of FIG. 2A is adjusted to form a high-resistance short-circuit channel (inversion layer channel) n1 in the channel region. Similar effects can be obtained. In the N-channel short-circuit MOS transistor element RTr2 in FIG. 8, positive charge holes h are accumulated in the polysilicon gate electrode Gc. However, in the P-channel short-circuit MOS transistor element, the polysilicon gate electrode Gc is negative. Charged electrons accumulate.

  As shown in FIG. 9, in the short-circuit MOS transistor element RTr2, as the charge injection amount to the gate electrode Gc increases, the Vg-Id characteristic moves to the left as shown by the white arrow in the figure, and the threshold value The voltage drops from Vt2a to Vt2b, and becomes a short-circuit MOS transistor element (high resistance element) RTr2 having a low resistance value. Conversely, a short-circuit MOS transistor element (high resistance element) RTr2 having a high resistance value can be obtained by reducing the amount of charge injected into the gate electrode Gc as much as possible. As described above, in the short-circuit MOS transistor element RTr2, a short-circuit MOS transistor having a high resistance value in a wide range desired by injecting charges into the gate electrode Gc in a floating state and appropriately setting the amount of charges to be injected. An element (high resistance element) can be realized.

  As described above, the short-circuit MOS transistor element RTr2 in FIG. 8 can also function as a high-resistance element because it can conduct electricity between the source and drain without gate input. Therefore, also in the semiconductor device 21 of FIG. 7, it is possible to suppress a (leakage) current in a steady state flowing in the gate voltage dividing circuit line, thereby reducing power consumption. Further, the area occupied by the short MOS transistor element RTr2 in the chip is much smaller than that of the resistance element R formed of the conventional thin film shown in FIG. 17, and this does not increase the cost.

  Accordingly, the semiconductor device 21 of FIG. 7 is also a semiconductor device in which n (n ≧ 2) MOS transistor elements Tr that are insulated and isolated from each other are sequentially connected in series as in the semiconductor device 20 shown in FIG. Therefore, a high breakdown voltage required as a whole can be ensured, and a small and inexpensive semiconductor device with low power consumption can be obtained.

  Also in the semiconductor device 21 of FIG. 7, the MOS transistor element Tr and the short-circuit MOS transistor element RTr2 have the same cross-sectional structure in the channel length direction. Therefore, the withstand voltage design can be simplified, and the withstand voltage characteristics of both the elements Tr and RTr2 can be matched accurately. Also, in each line, since the breakdown voltage of each element Tr and RTr2 constituting the same becomes equal, the voltage (withstand voltage) shared by each element Tr and RTr2 inserted between the GND potential and the predetermined potential is made equal. Can be minimized.

  Further, the semiconductor device 21 including the MOS transistor element Tr and the short-circuit MOS transistor element RTr2 having the same cross-sectional structure in the main line and the gate voltage dividing circuit line can cover the formation of the MOS transistor element Tr and the short-circuit MOS transistor element RTr1 in a common process. be able to. Therefore, the manufacture of the semiconductor device 21 has a small number of processes and is easy to manage, and the semiconductor device 21 can be manufactured at low cost.

  Further, the MOS transistor element and the short-circuit MOS transistor element applicable to the configuration of the semiconductor device 21 in FIG. 7 may be a horizontal type or a vertical type as in the case of the semiconductor device 20 shown in FIG. Also good.

  FIG. 10 is a more preferable example of the semiconductor device 21 shown in FIG. 7, and is a schematic top view showing the configuration of the main part of the semiconductor device 21a. FIG. 11 is a schematic cross-sectional view of the short-circuit MOS transistor element RTr2 and the second gate electrode component SGc2 in the semiconductor device 21a. In the semiconductor device 21a of FIG. 10, the same reference numerals are given to the same parts as those of the semiconductor device 21 shown in FIG. Further, the short-circuit MOS transistor element RTr2 in FIG. 11 is the same as the short-circuit MOS transistor element RTr2 in FIG. 8, and the MOS transistor element Tr in FIG. 11 is the same as the MOS transistor element Tr in FIG. .

  The semiconductor device 21a shown in FIG. 10 has a configuration in which a second gate electrode configuration unit SGc2 serving as charge injection means is added to the short-circuit MOS transistor element RTr2 with respect to the semiconductor device 21 shown in FIG. In the semiconductor device 21a of FIG. 10, as shown in FIG. 11, the gate electrode Gc of the short-circuit MOS transistor element RTr2 is in a floating state formed on the tunnel oxide film tn in the second gate electrode configuration unit SGc2. It is configured to be connected to the gate electrode Gc2. The second gate electrode Gc2 is the same as the floating gate electrode in a rewritable nonvolatile memory transistor (not shown) having two gate electrodes, a control gate electrode and a floating gate electrode. Thereby, hot carriers (electrons or holes) generated by a high electric field are stably injected into the second gate electrode Gc2 through the tunnel oxide film tn, and the amount of charge injected into the gate electrode Gc of the short-circuit MOS transistor element RTr2 The injection can be controlled.

FIG. 12 is a schematic top view showing the main configuration of the semiconductor device 21b according to the present invention . Compared to the semiconductor device 21a shown in FIG. 11, the second gate electrode configuration portion SGc2 is placed on the substrate. The pad electrode Pc2 thus formed is added. The pad electrode Pc2 is connected to the second gate electrode Gc2, and is in a floating state like the second gate electrode Gc2. Using this pad electrode Pc2, it is possible to more precisely control the amount of charge injected into the gate electrode Gc of the short-circuit MOS transistor element RTr2. By injecting charges through the pad electrode Pc2, for example, the resistance value of the short-circuit MOS transistor element (high resistance element) RTr2 in the wafer state can be adjusted.

The hole injection into the gate electrode Gc of the short-circuit MOS transistor element RTr2 shown in FIG. 8 is not limited to the method shown in FIG. 11, but the gate electrode Gc is formed of silicon oxide (SiO ₂ ), for example. Alternatively, high energy radiation such as X-rays may be irradiated to trap holes in the oxide film.

  In each of the semiconductor devices 20, 21, 21 a, and 21 b described above, n short MOS transistor elements (high resistance elements) RTr 1 or RTr 2 are used for n MOS transistor elements Tr constituting the main line. A gate voltage dividing circuit line is configured. Each of the n short-circuit MOS transistor elements (high resistance elements) RTr1 or RTr2 constituting the gate voltage dividing circuit line may be divided into a plurality of parts.

  FIG. 13 is a schematic top view showing a configuration of a main part of the semiconductor device 22 as an example of the semiconductor device.

  In the semiconductor device 22 shown in FIG. 13, the short-circuit MOS transistor elements (high resistance elements) arranged in the field regions F1 to F6 constituting each stage of the gate voltage dividing circuit line are divided into three parts. ing. As a result, each of the divided elements RTr3a to RTr3c formed by dividing into three pieces is appropriately connected, so that a desired high resistance value of each stage of the short-circuit MOS transistor element (high resistance element) can be easily, precisely and widely used. It becomes possible to set to.

  As described above, each of the semiconductor devices 20, 21, 21a, 21b, and 22 is a semiconductor device in which n (n ≧ 2) MOS transistor elements that are insulated from each other are sequentially connected in series. An object of the present invention is to provide a semiconductor device that can secure a high breakdown voltage required as a whole, and is small in size and low in power consumption.

  Therefore, the semiconductor devices 20, 21, 21 a, 21 b, and 22 have levels in an inverter driving high voltage IC composed of, for example, a GND reference gate drive circuit, a floating reference gate drive circuit, a control circuit, and a level shift circuit. It is suitable for a semiconductor device used for a shift circuit. In particular, the high-voltage IC using the semiconductor devices 20, 21, 21a, 21b, and 22 can secure a high withstand voltage required as a whole, has low power consumption, is a small and inexpensive semiconductor device. Thus, a high voltage IC suitable for driving an inverter of an in-vehicle motor such as an HEV / EV / FC vehicle or an inverter of an in-vehicle air conditioner can be obtained. However, the application target of the semiconductor device of the present invention is not limited to this, and can also be applied to the field of consumer / industrial motor control.

FIG. 3 is a schematic top view showing a configuration of a main part of a semiconductor device 20 as an example of a semiconductor device which is not the present invention but is a reference . (A), (b) is typical sectional drawing of MOS transistor element Tr and short circuit MOS transistor element RTr1 in the semiconductor device 20, respectively. (A), (b) is a figure which shows the gate voltage-drain current (Vg-Id) characteristic regarding MOS transistor element Tr and short-circuit MOS transistor element RTr1, respectively. It is a figure which shows the gate voltage-drain current (Vg-Id) characteristic at the time of changing the threshold voltage of short circuit MOS transistor element RTr1 by changing ion implantation amount. FIG. 2 is a schematic cross-sectional view of a more preferable short-circuit MOS transistor element RTr1a that can be used in the configuration of the semiconductor device 20 of FIG. (A), (b) is typical sectional drawing of another MOS transistor element Trb and short circuit MOS transistor element RTr1b which can be applied to the structure of the semiconductor device 20 of FIG. 1, respectively. FIG. 2 is a schematic top view showing a configuration of a main part of a semiconductor device 21 as an example of a semiconductor device on which the present invention is based . 3 is a schematic cross-sectional view of a short-circuit MOS transistor element RTr2 in the semiconductor device 21. FIG. It is a figure which shows the gate voltage-drain current (Vg-Id) characteristic regarding short circuit MOS transistor element RTr2. FIG. 8 is a more preferable example of the semiconductor device 21 shown in FIG. 7, and is a schematic top view showing a main configuration of the semiconductor device 21 a. FIG. 11 is a schematic cross-sectional view of a short-circuit MOS transistor element RTr2 and a second gate electrode configuration unit SGc2 in the semiconductor device 21a. It is a typical top view which shows the principal part structure of the semiconductor device 21b which concerns on this invention . 3 is a schematic top view showing a main configuration of a semiconductor device 22. FIG. 1 is a basic equivalent circuit diagram of a semiconductor device 10 in a semiconductor device disclosed in Patent Document 2 used for a high voltage IC of an inverter drive circuit. 14 is a diagram showing in detail the level shift circuit unit and floating reference gate drive circuit unit of the high voltage IC disclosed in Patent Document 2, and is a basic equivalent circuit diagram of FIG. 14 applied to the level shift circuit of the high voltage IC 100. FIG. 2 is a diagram illustrating an arrangement of circuit elements of the semiconductor device 10 shown. It is sectional drawing in the dashed-dotted line AA of FIG. 15, and is a figure which shows the structure of each MOS transistor element. FIG. 16 is a schematic top view showing a main configuration of a semiconductor device 11 in which the semiconductor device 10 shown in FIGS. 14 and 15 is simplified.

Explanation of symbols

10, 11, 20, 21, 21, 21a, 21b, 22 Semiconductor device Tr, Trb, Tr _{1 to} Tr _n , Tr _n MOS transistor element RTr1, RTr1a, RTr1b, RTr2, RTr3a to RTr3c Short-circuit MOS transistor element R _out Output resistance 1 SOI substrate 1a SOI layer 2 support substrate 3 buried oxide film 4, Z1 insulation isolation trench Z2 second insulation isolation trench F1 to F6 field region S, Sa, Sb source D, Db drain G, Ga to Gc gate (electrode)
n1 Short-circuit channel (inversion layer channel)
h Charge (hole)

Claims (11)

N (n ≧ 2) MOS transistor elements that are isolated from each other are sequentially connected in series between a ground (GND) potential and a predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage. Connected,
The gate terminal in the first stage MOS transistor element is an input terminal,
The n short-circuit MOS transistor elements formed between the source potential and the drain in such a manner that there is no gate input can conduct the GND potential side at the first stage and the predetermined potential side between the GND potential and the predetermined potential. As the nth stage, they are sequentially connected in series,
The gate terminals of the MOS transistor elements of each stage excluding the first stage MOS transistor element are sequentially connected between the short-circuit MOS transistor elements of the respective stages connected in series,
A semiconductor device in which an output is taken out from a terminal on the predetermined potential side in the n-th stage MOS transistor element ,
The short-circuit MOS transistor element has a gate electrode in a floating state,
In a state where charges are injected into the gate electrode, the source and drain are formed to be conductive,
The gate electrode is connected to a second gate electrode in a floating state formed on the tunnel oxide film;
A semiconductor device, wherein the second gate electrode is connected to a pad electrode in a floating state formed on a substrate .   The semiconductor device according to claim 1, wherein the MOS transistor element and the short-circuit MOS transistor element have the same cross-sectional structure in the channel length direction.   The semiconductor device according to claim 1, wherein the MOS transistor element and the short-circuit MOS transistor element are of a lateral type.   The semiconductor device according to claim 1, wherein the MOS transistor element and the short-circuit MOS transistor element are of a vertical type. The MOS transistor element and the short-circuit MOS transistor element are formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film,
5. The semiconductor device according to claim 1, wherein the semiconductor devices are isolated from each other by an insulating isolation trench reaching the buried oxide film . 6. An n-fold insulating isolation trench reaching the buried oxide film is formed;
The n MOS transistor elements isolated from each other are sequentially arranged one by one in each region surrounded by the n-fold insulating isolation trench so as to include a high-stage MOS transistor element. 6. The semiconductor device according to claim 5, wherein: The n short-circuit MOS transistor elements that are isolated from each other are sequentially arranged one by one in each region surrounded by the n-layer insulation isolation trench so as to include a high-stage short-circuit MOS transistor element. The semiconductor device according to claim 6 . 8. The semiconductor device according to claim 7, wherein each of the n short-circuit MOS transistor elements is divided into a plurality of parts . The semiconductor device is
A GND reference gate drive circuit based on a GND potential, a floating reference gate drive circuit based on a floating potential, a control circuit for controlling the GND reference gate drive circuit and the floating reference gate drive circuit, and the control circuit; In a high voltage IC for driving an inverter, which is interposed between the floating reference gate driving circuit and configured by a level shift circuit for level shifting an input / output signal of the control circuit between a GND potential and a floating potential.
The predetermined potential as a floating potential,
9. The semiconductor device according to claim 1 , wherein the semiconductor device is applied to the level shift circuit . The semiconductor device according to claim 9 , wherein the high voltage IC is a high voltage IC for driving an inverter of a vehicle-mounted motor . The semiconductor device according to claim 9 , wherein the high voltage IC is a high voltage IC for driving an inverter of an in-vehicle air conditioner .

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