JP2001210685A5 - - Google Patents

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Publication number
JP2001210685A5
JP2001210685A5 JP2000264193A JP2000264193A JP2001210685A5 JP 2001210685 A5 JP2001210685 A5 JP 2001210685A5 JP 2000264193 A JP2000264193 A JP 2000264193A JP 2000264193 A JP2000264193 A JP 2000264193A JP 2001210685 A5 JP2001210685 A5 JP 2001210685A5
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JP
Japan
Prior art keywords
test
semiconductor chip
test circuit
semiconductor wafer
semiconductor
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Pending
Application number
JP2000264193A
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Japanese (ja)
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JP2001210685A (en
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Priority to JP2000264193A priority Critical patent/JP2001210685A/en
Priority claimed from JP2000264193A external-priority patent/JP2001210685A/en
Publication of JP2001210685A publication Critical patent/JP2001210685A/en
Publication of JP2001210685A5 publication Critical patent/JP2001210685A5/ja
Pending legal-status Critical Current

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Claims (7)

半導体ウエハに形成された半導体チップの電気的試験を行うテストシステムであって、
前記半導体チップにおける電極パッドの配置にあわせて導電性のニードルを配設し、テスト回路と接続するプローブカードと、
前記プローブカードに搭載され、プログラムに基づいて前記半導体チップのテストを行うテスト回路と、
前記テスト回路におけるプログラムの書き換え、ならびに前記テスト回路から出力されたテスト結果を格納する制御装置とよりなることを特徴とするテストシステム。A test system for conducting an electrical test of a semiconductor chip formed on a semiconductor wafer,
According to the arrangement of the electrode pads on the semiconductor chip, a conductive needle is arranged, and a probe card connected to a test circuit;
A test circuit mounted on the probe card for testing the semiconductor chip based on a program;
A test system comprising: a control device for rewriting a program in the test circuit and storing a test result output from the test circuit. 半導体ウエハに形成された半導体チップの電気的試験を行うテストシステムであって、前記半導体ウエハの任意の位置に形成された前記半導体チップをテストするテスト回路と、前記半導体チップと前記テスト回路とを接続するテスト用配線が形成されプロービングモジュールと、前記プロービングモジュールを介して前記半導体チップ、および前記テスト回路に電源を供給する電源供給装置とを備えたことを特徴とするテストシステム。A test system for conducting an electrical test of a semiconductor chip formed on a semiconductor wafer, comprising: a test circuit for testing the semiconductor chip formed at an arbitrary position of the semiconductor wafer; and the semiconductor chip and the test circuit. A test system comprising: a probing module in which test wiring to be connected is formed; and a power supply device that supplies power to the semiconductor chip and the test circuit via the probing module. 半導体ウエハに形成された半導体チップの電気的試験を行うテストシステムであって、前記半導体ウエハにおけるスクライブエリア、またはチップエリアに、前記半導体チップをテストするテスト回路を形成し、前記半導体ウエハのスクライブエリアまたはテスト用配線層に、前記テスト回路と半導体チップとを接続するテスト用配線を形成した構成よりなることを特徴とするテストシステム。A test system for performing an electrical test of a semiconductor chip formed on a semiconductor wafer, wherein a test circuit for testing the semiconductor chip is formed in a scribe area or chip area of the semiconductor wafer, and the scribe area of the semiconductor wafer is formed Alternatively, the test system includes a test wiring layer in which test wiring for connecting the test circuit and the semiconductor chip is formed. 請求項１〜３のいずれか１項に記載のテストシステムにおいて、前記テスト回路が、ＦＰＧＡまたはマイクロコンピュータデバイスを含むことを特徴とするテストシステム。The test system according to claim 1, wherein the test circuit includes an FPGA or a microcomputer device. 半導体ウエハに形成された半導体チップの電気的試験を行うテスタにおけるブロック毎の機能とテストされる前記半導体チップの機能とをハードウェア記述言語で記述し、前記ハードウェア記述とテストプログラムをハードウェアエミュレータに入力して、前記ハードウェアエミュレータによってシミュレーションを行ない、テストプログラムのデバッグを行うことを特徴とするテストプログラムの生成方法。A function for each block in a tester for performing an electrical test of a semiconductor chip formed on a semiconductor wafer and a function of the semiconductor chip to be tested are described in a hardware description language, and the hardware description and the test program are described in a hardware emulator. A test program generation method, wherein the test program is debugged by performing simulation with the hardware emulator. 請求項２あるいは請求項３に記載されたテストシステムにおいて、前記テスト回路は、半導体ウエハに形成された複数の半導体チップのテストを行なうことを特徴とするテストシステム。4. The test system according to claim 2, wherein the test circuit tests a plurality of semiconductor chips formed on a semiconductor wafer. 請求項６に記載のテストシステムにおいて、前記テスト回路が、ＦＰＧＡまたはマイクロコンピュータデバイスよりなることを特徴とするテストシステム。7. The test system according to claim 6, wherein the test circuit comprises an FPGA or a microcomputer device.
JP2000264193A 1999-11-19 2000-08-31 Test system and method of manufacturing semiconductor integrated circuit device Pending JP2001210685A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000264193A JP2001210685A (en) 1999-11-19 2000-08-31 Test system and method of manufacturing semiconductor integrated circuit device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP32928199 1999-11-19
JP11-329281 1999-11-19
JP2000264193A JP2001210685A (en) 1999-11-19 2000-08-31 Test system and method of manufacturing semiconductor integrated circuit device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2004053271A Division JP2004260188A (en) 2004-02-27 2004-02-27 Manufacturing method for semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JP2001210685A JP2001210685A (en) 2001-08-03
JP2001210685A5 true JP2001210685A5 (en) 2005-02-03

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JP2000264193A Pending JP2001210685A (en) 1999-11-19 2000-08-31 Test system and method of manufacturing semiconductor integrated circuit device

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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3934434B2 (en) 2002-02-19 2007-06-20 富士通株式会社 Circuit testing equipment
KR100465541B1 (en) * 2002-04-29 2005-01-13 주식회사 하이닉스반도체 Semiconductor test device with mulit probing pad
JP4800564B2 (en) * 2003-06-26 2011-10-26 株式会社日本マイクロニクス Probe card
US7307433B2 (en) * 2004-04-21 2007-12-11 Formfactor, Inc. Intelligent probe card architecture
US8581610B2 (en) * 2004-04-21 2013-11-12 Charles A Miller Method of designing an application specific probe card test system
TWI274166B (en) * 2004-06-18 2007-02-21 Unitest Inc Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices
US7245134B2 (en) * 2005-01-31 2007-07-17 Formfactor, Inc. Probe card assembly including a programmable device to selectively route signals from channels of a test system controller to probes
JP4322827B2 (en) 2005-02-09 2009-09-02 エルピーダメモリ株式会社 Semiconductor chip
JP2006349402A (en) * 2005-06-14 2006-12-28 Fukuoka Pref Gov Sangyo Kagaku Gijutsu Shinko Zaidan Probe, multilayer substrate and semiconductor device
TWI398640B (en) * 2005-09-19 2013-06-11 Gunsei Kimoto Contact assembly and its LSI wafer inspection device
KR100712561B1 (en) 2006-08-23 2007-05-02 삼성전자주식회사 Wafer type probe card and method for fabricating the same and semiconductor test apparatus having wafer type probe card
EP2259297A1 (en) * 2008-03-26 2010-12-08 Advantest Corporation Probe wafer, probe device, and testing system
WO2009139070A1 (en) * 2008-05-16 2009-11-19 株式会社アドバンテスト Manufacturing method and wafer unit for testing
JP5461394B2 (en) * 2008-05-21 2014-04-02 株式会社アドバンテスト Test wafer unit and test system
WO2009147723A1 (en) 2008-06-02 2009-12-10 株式会社アドバンテスト Test system and substrate unit to be used for testing
WO2010044143A1 (en) 2008-10-14 2010-04-22 株式会社アドバンテスト Test apparatus and manufacturing method
JP5617768B2 (en) * 2011-06-10 2014-11-05 株式会社デンソー Semiconductor device and measuring method of semiconductor device
JP2013088288A (en) * 2011-10-18 2013-05-13 Fujitsu Semiconductor Ltd Inspection device and inspection system
JP5731417B2 (en) * 2012-01-18 2015-06-10 東京エレクトロン株式会社 Semiconductor device inspection equipment
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JP2017129544A (en) * 2016-01-22 2017-07-27 東京エレクトロン株式会社 Substrate inspection device and program
KR102578644B1 (en) * 2017-08-30 2023-09-13 삼성전자주식회사 A apparatus for predicting a yield of a semiconductor integrated circuits, and a method for manufacturing a semiconductor device using the same
CN109994400A (en) * 2017-12-29 2019-07-09 江苏凯尔生物识别科技有限公司 Material collecting device for chip testing
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JP7058759B2 (en) * 2019-01-22 2022-04-22 株式会社アドバンテスト Automatic test equipment for testing one or more devices under test, methods for automatic testing of one or more devices under test, and computer programs for handling command errors.

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