JP5731417B2 - Semiconductor device inspection equipment - Google Patents

Description

  The present invention relates to a semiconductor device inspection apparatus.

  2. Description of the Related Art Conventionally, in a semiconductor device manufacturing process, a semiconductor device inspection apparatus (tester) for inspecting the state of a semiconductor wafer and the state of a packaged semiconductor device has been used. In such a semiconductor device inspection apparatus, a predetermined inspection signal is output to the semiconductor device to be inspected, and an output signal of the semiconductor device to be inspected is measured to inspect whether the predetermined signal is output from the semiconductor device to be inspected. (For example, refer to Patent Document 1).

JP 2011-53180 A

  A semiconductor device inspection apparatus requires different electronic circuits for inspection depending on the type of semiconductor device to be inspected. Conventionally, such an inspection electronic circuit has been a large one formed on a printed wiring board or the like. However, it is difficult to install such a large inspection electronic circuit in the vicinity of the semiconductor device to be inspected, and the electronic circuit for inspection is to be installed at a certain distance. For this reason, there is a problem that the transmission line between the electronic circuit for inspection and the semiconductor device to be inspected becomes long, making it difficult to perform high-speed inspection.

The following effects can be expected by downsizing the electronic circuit of the semiconductor device inspection apparatus into a single chip.
1: By integrating the driver circuit in the chip, relays and switches that originally required a large area on the substrate are not necessary, and the number of components can be reduced by integrating them.
2: By integrating the driver circuit in the chip, the temperature distribution in the chip and the process of executing the process by the process in which the inspection device electrically tests the function of the semiconductor device due to its own heat generation The variation in operation becomes uniform and it becomes easier to control.

  It should be noted that in the conventional method configured over a large area on the substrate, the variation of each part is not related to each other. Therefore, the process contents are changed by exchanging specific parts to correct the process contents. It is difficult to carry out management.

  The above-mentioned one-chip electronic circuit of a semiconductor device inspection apparatus can be expected to have an excellent effect, but conversely, in order to reduce the size, an electronic circuit is formed in a small area, and the occupied area is Therefore, it is necessary to reduce the area occupied by each electronic circuit unit to reduce the size.

  On the other hand, in order to cover a wide input voltage range, a function of processing a high voltage system (for example, 20 V system) signal is required. However, in this case, the size of the transistor element or the like becomes larger than that of the low voltage system (for example, 1.8 V system), and it becomes difficult to perform a high-speed (for example, 1 nanosecond) operation. There is a problem that the area occupied by this increases and it is difficult to reduce the size. Furthermore, as a high voltage signal processing, for example, a problem of the prior art will be described by taking a comparator that processes a 20V signal as an example. When a high voltage differential amplifier is used as a preceding stage in the comparator, the high voltage system signal processing is high. I can't get gain. Further, since the comparison accuracy in such a comparator is improved as the gain of the amplifier in the previous stage is higher, there is a problem that it is difficult to configure a high-accuracy comparator with a high-voltage amplifier.

  The present invention has been made in response to the above-described conventional circumstances, and can cover a wide input voltage range, and can downsize an electronic circuit for inspection into a single chip, and can perform high-speed processing. An object of the present invention is to provide a semiconductor device inspection apparatus capable of performing the above.

One aspect of a semiconductor device inspection apparatus according to the present invention is a semiconductor device inspection apparatus that performs electrical inspection of a semiconductor device to be measured. At least a digital / analog converter and a timing generator are provided in one semiconductor chip. A test signal supply circuit for supplying a test signal to the semiconductor device under test based on a test timing of the timing generator, and comparing the output signal from the semiconductor device under test with a reference value A semiconductor chip on which a comparison circuit for inspecting the state of a device, a DC circuit for applying a DC voltage or a DC current to the semiconductor device to be measured, and a power circuit for supplying power to the semiconductor device to be measured are formed. a, the comparator circuit, receiving the output signal of the first voltage system from the measured semiconductor devices A first differential amplifier, a level shifter for reducing an output signal from the first differential amplifier to a voltage level of a second voltage system lower than the first voltage system, and an output from the level shifter And a second differential amplifier for receiving the second voltage system.

  According to the present invention, there is provided a semiconductor device inspection apparatus capable of covering a wide input voltage range, reducing the size of an inspection electronic circuit to one chip, and performing high-speed processing. Can be provided.

The figure which shows schematic structure of the inspection apparatus of the semiconductor device of one Embodiment of this invention. The figure which shows the principal part schematic structure of the test | inspection apparatus of the semiconductor device of FIG. The figure which shows the operation timing of the comparator circuit of FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 schematically shows a schematic configuration of a semiconductor inspection apparatus according to an embodiment of the present invention. The semiconductor inspection apparatus 100 is configured by mounting a semiconductor chip 120 on a circuit board 110, and is connected to a semiconductor device under test (DUT (Device Under Test)) 200 via a transmission line 150 to perform the inspection. It is configured as follows.

  The semiconductor chip 120 includes a timing generator 121, a digital / analog converter (DAC) 122, a plurality of pin driver circuits 123, a comparator circuit (comparison circuit) 124, a DC circuit 125, a VC circuit 126, and a driver buffer circuit 127. Has been. In addition, on the circuit board 110 on which the semiconductor chip 120 is mounted, a resistance element 111 is disposed corresponding to each pin driver circuit 123. In FIG. 1, reference numerals 130 and 131 denote force lines, and reference numerals 140 and 141 denote sense lines.

  A plurality of pin driver circuits 123 apply a predetermined inspection signal to the semiconductor device 200 to be inspected via the resistance element 111 and the transmission line 150 based on the test timing of the timing generator 121. That is, the pin driver circuit 123 functions as an inspection signal supply circuit.

  Then, by comparing the output signal output from the semiconductor device 200 to be inspected with the reference value by the comparator circuit 124 based on the inspection signal supplied from the pin driver circuit 123, a normal signal is output from the semiconductor device 200 to be inspected. Inspect whether it is done. The DC circuit 125 formed on the semiconductor chip 120 is for applying a DC voltage or current to the semiconductor device 200 to be inspected, and the VC circuit 126 is for supplying power to the semiconductor device 200 to be inspected. .

  A predetermined inspection signal is applied from the plurality of pin driver circuits 123 to the semiconductor device 200 to be inspected via the resistance element 111 and the transmission line 150. At this time, for example, when the impedance of the transmission line 150 is 50Ω, impedance matching is performed so that the output impedance of the pin driver circuit 123 is 14Ω, the impedance of the resistance element 111 is 36Ω, and the total impedance is 50Ω. ing.

  As shown in FIG. 2, the comparator circuit 124 includes a front-stage differential amplifier 161, a level shifter 162, a rear-stage differential amplifier 163, and a latch circuit 164. The pre-stage differential amplifier 161 is of a high voltage system (20V system in this embodiment), and a reference signal (REF) is input through the switch S1, and a data signal (DATA) is input through the switch S2. It is designed to be entered. In the present embodiment, the front-stage differential amplifier 161 of the comparator circuit 124 is configured with a 20V system as described above, so that a wide input voltage range can be covered.

  On the other hand, the post-stage differential amplifier 163 is of a low voltage system (1.8 V system in the present embodiment), which makes it faster than the case where the post-stage differential amplifier 163 is of a high voltage system. Processing (for example, processing speed on the order of nanoseconds) and downsizing can be achieved.

  Also. A level shifter 162 is interposed between the front-stage differential amplifier 161 and the rear-stage differential amplifier 163. The output signal of the front-stage differential amplifier 161 is input to the level shifter 162 and is level-shifted to a low voltage system signal (1.8 V system in this embodiment). The level-shifted signal is input to the low-voltage system (1.8 V system) post-stage differential amplifier 163 via the capacitors C1 and C2. Since the front-stage differential amplifier 161 is a high-voltage amplifier, a high gain cannot be obtained. Since the comparison accuracy of the comparator improves as the gain of the amplifier increases, it is difficult to configure a high-accuracy comparator with a high-voltage amplifier. Therefore, the high gain is obtained by setting the low-voltage differential amplifier after the level shifter 162 in multiple stages without expecting a high gain in the pre-stage differential amplifier 161. A highly accurate comparator can be configured by the offset cancel circuit and this high gain.

  FIG. 3 shows the operation timing of the comparator circuit 124 configured as described above. In the comparator circuit 124 configured as described above, when φ1 is on (switches S3, S4, S5, and S6 are on) and φ2 is off (switches S1 and S2 are off), the front-stage differential amplifier 161 and the rear-stage differential amplifier 161 The offset voltage of the differential amplifier 163 is charged to the capacitor C1 and the capacitor C2 (t1: offset, REF voltage sampling phase shown in FIG. 3).

  When φ1 is off (switches S3, S4, S5, and S6 are off) and φ2 is on (switches S1 and S2 are on), the voltages of the reference signal (REF) and the data signal (DATA) Are compared and the obtained output voltage is latched by the latch circuit 164 at the fall of φ2 (t3 shown in FIG. 3: auto zero and comparison phase). In addition, t2 shown in FIG. 3 is a simultaneous ON prohibition section.

  As described above, in the semiconductor inspection apparatus 100 of the present embodiment, the timing generator 121, the digital / analog converter (DAC) 122, the plurality of pin driver circuits 123, the comparator circuit 124, the DC circuit 125, the VC circuit 126, and the driver buffer circuit. 127 or the like is formed in one semiconductor chip 120, and the inspection circuit can be downsized compared to the conventional one. As a result, the semiconductor inspection apparatus 100 can be arranged closer to the device under test (DUT) 200, the transmission line 150 can be shortened, and high-speed inspection can be performed. It becomes.

  As shown in FIG. 2, the comparator circuit 124 includes a front-stage differential amplifier 161, a level shifter 162, a rear-stage differential amplifier 163, and a latch circuit 164. 161 is a high voltage system (20V system in this embodiment), and the post-stage differential amplifier 163 is a low voltage system (1.8V system in this embodiment).

  As described above, since the front-stage differential amplifier 161 of the comparator circuit 124 is configured with a 20 V system, a wide input voltage range can be covered.

  Further, the rear stage differential amplifier 163 is of a low voltage system (1.8V system in this embodiment), and is level-shifted by the level shifter 162 to perform signal processing in the 1.8V system after the rear stage differential amplifier 163. It has become. As a result, it is possible to perform high-speed processing (for example, processing speed on the order of nanoseconds) and downsizing as compared with the case where the subsequent differential amplifier 163 and the subsequent 20V systems are used.

  When the area occupied on the semiconductor chip 120 is compared, the two stages of amplifiers composed of 20V elements and the four stages of amplifiers composed of 1.8V elements have substantially the same area.

  In addition, this invention is not limited to the said embodiment, Of course, a various deformation | transformation is possible.

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor inspection apparatus, 110 ... Circuit board, 111 ... Resistance element, 120 ... Semiconductor chip, 121 ... Timing generator, 122 ... Digital-analog converter (DAC), 123 ... Pin driver circuit, 124: Comparator circuit, 125: DC circuit, 126: VC circuit, 127: Driver buffer circuit, 130, 131: Force line, 140, 141 ... Sense line, 150 ... Transmission line, 200 ... Semiconductor device under test (DUT (Device Under Test)).

Claims (2)

A semiconductor device inspection apparatus for performing electrical inspection of a semiconductor device to be measured,
At least in one semiconductor chip,
A digital-to-analog converter,
A timing generator;
An inspection signal supply circuit for supplying an inspection signal to the semiconductor device to be measured based on a test timing of the timing generator;
A comparison circuit for inspecting the state of the semiconductor device under test by comparing an output signal from the semiconductor device under test with a reference value;
A DC circuit for applying a DC voltage or a DC current to the semiconductor device to be measured;
A power supply circuit for supplying power to the semiconductor device to be measured;
Having a semiconductor chip formed,
The comparison circuit is
A first differential amplifier for receiving an output signal of a first voltage system from the semiconductor device to be measured;
A level shifter for reducing an output signal from the first differential amplifier to a voltage level of a second voltage system lower than the first voltage system;
A second differential amplifier of the second voltage system for receiving an output from the level shifter;
An inspection apparatus for a semiconductor device, comprising: A semiconductor device inspection apparatus according to claim 1,
The semiconductor device inspection apparatus, wherein the first voltage system is a 20V system and the second voltage system is a 1.8V system.

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