JPH10288647A - Integrated circuit inspection device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inspect the internal circuit of an integrated circuit or the condition of an I/O pin with the minimum probe for inspection. SOLUTION: When a device is constituted to measure the condition of an integrated circuit 1 and an internal circuit 2 and the condition of I/O pins 31-33, an analog test bus 4 included in the integrated circuit 1 is provided. Further, switching means 51-56 are provided and the analog bus 4 is connected to the internal circuit 2 or the I/O pins 31-33 selectively. At the same time, a switch control means 7 is provided, thus controlling the connection of switch means 51-56 according to a control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit inspection apparatus and an inspection method.

[0002]

2. Description of the Related Art A circuit inspection method using a bed of nail (inspection probe), which is one of the inspection methods for printed circuit boards used in electronic equipment ("Integratin").
g design and Test: Using CAE Tools for ATE Programi
ng ", KPParker, IEEE ComputerSociety Press, Los Alam
Itos CA, 1987) is used as an effective inspection method by conducting inspection by contacting the inspection probe with the wiring and components of the printed circuit board on which the components are mounted, and by diagnosing efficient failure points. . In component inspection on a mounting board, for example, an analog IC has a relatively small number of pins, and a probe for inspection is brought into contact with a test point provided on a printed circuit board, and an output signal thereof is observed. The inspection was easily performed.

[0003]

However, with the recent miniaturization and high performance of electronic equipment, high integration of ICs and high-density mounting of printed circuit boards are rapidly progressing. Therefore, the circuit inspection method using the inspection probe has lost its usefulness. In addition to the high density of the mounting substrate, high integration, or the increase in the number of pins due to being integrated together with the digital IC makes it difficult to bring the inspection probe into contact, and it has become difficult to test the analog IC. .

The present invention relates to an internal circuit of an integrated circuit or an integrated circuit.
It is an object of the present invention to provide an integrated circuit inspection device and an inspection method for inspecting the state of the / O pin with a minimum inspection probe.

[0005]

In order to solve this problem, an apparatus of the present invention comprises an analog test bus included in an integrated circuit and an analog test bus connected to an internal circuit or I / O.
It is configured to have switch means for selectively connecting to pins and switch control means for controlling connection of the switch means in accordance with a control signal.

Accordingly, the apparatus of the present invention is connected to the analog test bus by selectively connecting the analog test bus to an internal circuit or an I / O pin when testing an integrated circuit device including the present invention. The condition of the internal circuit or the I / O pin can be easily inspected by the measuring device.

According to a first aspect of the present invention, there is provided an apparatus for measuring a state of an internal circuit of an integrated circuit and a state of an I / O pin, wherein the analog test bus included in the integrated circuit and the analog test bus are provided. Switch means for selectively connecting a test bus to the internal circuit or the I / O pin;
A testing device having the switch control means for controlling connection of the switch means in accordance with a control signal, the switch controlling the switch control means when testing an integrated circuit device including the present invention, and connecting the analog test bus to an internal circuit. Or I
By selectively connecting to the / O pin using switch means, it is easy to use a measuring device connected to the analog test bus, and to check the status of the internal circuit or I / O pins with a minimum number of test probes. It is possible to do.

According to a third aspect of the present invention, there is provided an apparatus for measuring a state of an internal circuit of an integrated circuit and a state of an I / O pin, wherein the analog test bus included in the integrated circuit, Buffer means for buffering a circuit or a signal of the I / O pin; switch means for selectively connecting the analog test bus to the internal circuit or the I / O pin directly or via the buffer circuit; And a switch control means for controlling connection of the switch means in accordance with the following. When testing an integrated circuit device including the present invention, the test apparatus controls the switch control means to connect an analog test bus to an internal circuit or I. A measuring device connected to an analog test bus by selectively connecting to the / O pin via a buffer circuit using switch means More easily, also it is possible to check the status of high-impedance and high-frequency portion of the internal circuit or I / O pins in the probe for minimal testing.

According to a fifth aspect of the present invention, there is provided an input signal switch for selectively connecting a reference voltage power supply and an input of the buffer means to the internal circuit or the I / O pin or to the reference power supply. 4. The test apparatus according to claim 3, further comprising: when testing the integrated circuit device including the present invention, connecting the analog test bus to the reference voltage power supply using the switch control means and the switch means directly or via the buffer means. The condition of the reference voltage power supply is measured by a measuring device connected to the analog test bus, and the analog test bus is directly connected to an internal circuit or an I / O pin using switch control means and switch means. Alternatively, the state of the internal circuit or the I / O pin is selectively connected via a buffer means and measured by a measuring device connected to the analog test bus. Measured, and status of the observed reference power supply, it is possible to make highly accurate inspection by comparing the status of internal circuitry or I / O pins.

According to a seventh aspect of the present invention, there is provided an apparatus for measuring a state of an internal circuit of an integrated circuit and a state of an I / O pin, wherein the analog test bus included in the integrated circuit, Frequency conversion means for converting the frequency of a circuit or the signal of the I / O pin in synchronization with a given frequency conversion pulse signal; and connecting the analog test bus directly to the internal circuit or the I / O pin or to the frequency What is claimed is: 1. An inspection apparatus comprising: a switch unit selectively connected via a conversion unit; and said switch control unit for controlling connection of said switch unit in accordance with a control signal. Occasionally, an analog test bus is selectively connected to an internal circuit or an I / O pin via a frequency conversion means using a switch control means and a switch means. By applying a frequency conversion pulse and converting the status of the internal circuit or I / O pin to a different frequency signal by the frequency conversion means, the internal circuit or I / O pin status can be obtained by a simple measurement device connected to the analog test bus. Can be measured.

According to a sixteenth aspect of the present invention, there is provided an apparatus for measuring a status of an internal circuit of an integrated circuit and a status of an I / O pin, comprising: a pair of analog test buses included in the integrated circuit; First signal sampling means for sampling the signal of the internal circuit or the I / O pin in synchronization with a given sampling pulse, a reference voltage, and the first signal sampling means in synchronization with the given sampling pulse; A second signal sampling unit for sampling a reference voltage and selecting the pair of analog test buses directly to the internal circuit or the I / O pin or via the first and second signal sampling units; Is a testing device having switch means for connecting the switches, and the switch control means for controlling the connection of the switch means in accordance with a control signal, wherein a reference voltage is applied when testing an integrated circuit device including the present invention. An analog test bus is selectively connected through the second signal sampling means using the switch control means and the switch means, a sampling pulse is applied, and a reference voltage is sampled on the second signal sampling means. The sampled state of the reference voltage power supply is measured by a measuring device connected to the test bus, and the analog test bus is connected to the internal circuit or the I / O pin using the switch control means and the switch means. , Selectively apply a sampling pulse, sample the state of the internal circuit or the I / O pin to the first sampling circuit, and use the measuring device connected to the analog test bus to connect the internal circuit or the I / O pin. The sampled state of the / O pin is measured, and the observed state of the reference power supply and the sampled internal circuit or I / O pin are measured.
By comparing the state of the pins, it is possible to perform a highly accurate inspection.

An invention according to claim 18 of the present invention is an apparatus for measuring a state of an internal circuit of an integrated circuit and a state of an I / O pin, wherein an analog test bus included in the integrated circuit and a voltage are measured. A voltage comparison means for comparing the variable reference voltage, the signal of the internal circuit or the I / O pin with the reference voltage in synchronization with a given trigger, and the analog test bus is connected to the internal circuit or the I / O pin. O
An inspection apparatus comprising: switch means for selectively connecting to a pin directly or via the voltage comparison means; and switch control means for controlling connection of the switch means in accordance with a control signal. An analog test bus is selectively connected to the O pin via a voltage comparison means using a switch control means and a switch means, and a trigger is given to the comparison means while changing a reference voltage, and a measurement connected to the analog test bus is provided. By measuring the comparison result from the comparison means by the device, it is possible to detect the voltage at the measurement point without being affected by noise or the like.

According to a twenty-first aspect of the present invention, there is provided an apparatus for measuring a state of an internal circuit of an integrated circuit and a state of an I / O pin, the first and second pairs being included in the integrated circuit. An analog test bus, switch means for selectively connecting the pair of analog test buses to the internal circuit or the I / O pin, and switch control means for controlling connection of the switch means according to a control signal. And a switch control means for controlling the switch control means when testing an integrated circuit device including the present invention, and selectively connecting a pair of analog test buses to an internal circuit or an I / O pin using the switch means. This makes it easier to use a measurement device connected to the analog test bus, and to detect the status of internal circuits or multiple I / O pin locations with a minimum number of test probes. It is possible to become.

According to a twenty-fourth aspect of the present invention, in addition to the inspection apparatus of the twenty-first aspect, an internal circuit disconnection controlled by the switch control means for controlling conduction between the I / O pin and an internal circuit. A switch is provided, and the internal circuit is disconnected by the switch control means and the switch is opened, so that a signal applied from the signal generation means via the analog test bus does not adversely affect the internal circuit, and the inspection can be executed safely.

According to a twenty-ninth aspect of the present invention, in addition to the inspection device of the eighth aspect, a transistor for forming a current source at a location to be measured is provided, and the internal circuit is separated by switch control means. The switch is opened, the analog test bus is connected to the I / O pin by the connecting means, and the transistor forming the current source is driven by the step wave to generate a step wave, and the transient response waveform is synchronized with the step wave to delay time Is detected by a signal sampling means that is provided with a sampling pulse by a sampling signal obtained by sweeping the signal, and is measured in a time domain by a measuring device connected to an analog test bus, so that a measured signal connected to an I / O pin is measured. It becomes possible to measure the impedance of the circuit.

According to a thirty-fifth aspect of the present invention, in addition to the inspection device of the twenty-first aspect, the switch control means connects the pair of analog buses to all of the internal circuits and the I / O bus.
It is characterized by having an operation mode in which the pair of analog buses is not connected to the / O pin, and by releasing the pair of analog buses from all internal circuits and I / O pins in this operation mode, the parasitic capacitance of the pair of analog buses is reduced. Measurement becomes possible.

According to a thirty-second aspect of the present invention, a dummy I / O pad not connected to another circuit is provided in addition to the inspection device according to the twenty-first aspect.
By connecting a pair of analog test buses to the / O pad using the switch means and the switch control means, the parasitic capacitance of the dummy I / O pad can be measured.

According to a thirty-fourth aspect of the present invention, in addition to the inspection apparatus of the twenty-first aspect, a plurality of analog test buses added to the pair of test buses and the plurality of analog test buses are connected to the internal device. And a switch means for selectively connecting to a circuit or the I / O pin. When testing an integrated circuit device including the present invention, the switch control means is controlled to connect a plurality of analog test buses to an internal circuit. Alternatively, by selectively connecting to the I / O pins using switch means, it is possible to easily inspect the status of the internal circuit or a plurality of locations of the I / O pins by the measuring device connected to the analog test bus. Becomes possible.

According to a thirty-fifth aspect of the present invention, in the inspection apparatus according to the twenty-first aspect, the switch unit is connected to a switch unit connected to an I / O pad.
The switches of the pair of analog test buses are connected to I / O pads via resistors, respectively, so that the effect of the resistance of the switches on the measurement system during measurement using the analog test bus is reduced.

According to a thirty-sixth aspect of the present invention, in the inspection apparatus according to the thirty-fifth aspect, the I / O pad is
The one connected to the conductor of the pair of analog test buses connected to the second analog test bus connecting the measuring device from the center of the pad via a resistor or a conductor, and is used for measurement using the analog test bus. This has the effect of further reducing the effect of the resistance of the switch on the measurement system.

According to a thirty-seventh aspect of the present invention, there is provided a storage means for storing information required for inspection such as a standard voltage, a standard impedance, a permissible error range, a parasitic capacitance and a parasitic resistance of each measuring point in an integrated circuit. An inspection apparatus having the above-mentioned configuration, and it is possible to determine whether the inspection is normal or not by comparing the information stored in the storage unit with the measurement result at the point to be measured.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 1, 1 is an integrated circuit, 2
Are internal circuits having the original functions of the integrated circuit, 31, 32, 3
Reference numeral 3 denotes an I / O pin of the integrated circuit 1. 4 is an analog test bus; 51, 52 and 53 are switch means for selectively connecting the internal circuit 2 and the analog test bus 4;
Switch means 5 and 56 for selectively connecting the I / O pins 31, 32 and 33 to the analog test bus 4, and 6
Is switch control means for controlling the opening and closing of the switch means 51-56. 7 is a switch control signal generator for generating a signal for controlling the switch control means 6,
Reference numeral 8 denotes a measuring device for observing the state of the analog test bus 4. The switch means 51 to 56 are opened and closed by controlling the switch control means 6 with a signal from the switch control signal generator 7. Since the switch control means 7 and the switch control signal generating device 8 can be easily configured by a known technique, various examples of a specific configuration and a control method are conceivable. It is assumed that all the switch means can be controlled by the control by. In the following description, the opening and closing of the switch means is controlled by a signal from the switch control signal
Is not specifically stated. In the figure, the I / O pins 31 to 33
Wiring from the switch control means 6 to the switch means 51
Wirings for controlling .about.56 are omitted.

When the integrated circuit 1 is in a normal circuit operation state, that is, when the internal circuit 2 is performing an original operation, the switch means 51 to 56 are all open. In this state, the analog test bus 4, the switch means 51 to 56, and the switch control means 6 do not affect the operation of the internal circuit 2.

At the time of testing the integrated circuit 1, a measuring device 8 required for testing is connected to the analog test bus 4. Next, by closing the switch means provided at the inspection target location, a signal at the inspection target location is sent to the measuring device 8 via the analog test bus 4. The inspection of the integrated circuit 1 can be performed by measuring the inspection target portion while opening and closing the switch means as needed. As a result, the inspection of the integrated circuit 1 can be executed only by accessing the switch control signal and the analog test bus. Can be minimized. For example, integrated circuit 1
Has 20 I / O pins, and if there are 10 measurement points required for inspection, it is necessary to contact at least 10 inspection probes with the mounting substrate in the related art. Was. According to the present invention, it is possible to measure 10 inspection objects of the integrated circuit 1 by using only two switch control signals and only three inspection probes to the analog test bus. By outputting these three wires to the edge of the mounting board such as a connector, a physical access point on the mounting board becomes unnecessary. Also, by installing the switch means at an internal node of the internal circuit 2 (a node where no signal is output to the I / O pin), the integrated circuit
Measurement of the internal nodes.

FIG. 2 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 2, 1 is an integrated circuit, 2
Are internal circuits having the original functions of the integrated circuit, 31, 32, 3
Reference numeral 3 denotes an I / O pin of the integrated circuit 1. 4 is an analog test bus, 51, 52, 53 are switch means for selectively connecting the output of the internal circuit 2 or the buffer means 9 and the analog test bus 4, and 54, 55, 56 are I / O pins 3.
Switch means for selectively connecting 1, 32, 33 and the analog test bus 4, and 6 is switch means 51 to 5
6 is switch control means for controlling the opening and closing of the switch 6. Reference numeral 7 denotes a switch control signal generator for generating a signal for controlling the switch controller 6, and reference numeral 8 denotes a measuring device for observing the state of the analog test bus. Reference numeral 9 denotes buffer means for buffering a signal from the internal circuit 2. The switch means 51 to 56 are opened and closed by controlling the switch control means 6 with a signal from the switch control signal generator 7. Here, the switch control means 7 and the switch control signal generator 8 are the same as those shown in FIG. In the following description, it is not particularly described that the opening and closing of the switch means is performed by controlling the switch control means 6 with a signal from the switch control signal generator 7. In the figure, the I / O pins 31, 32, 33
Wiring from the switch control means 6 to the switch means 51
Wirings for controlling .about.56 are omitted.

When the integrated circuit 1 is in a normal circuit operation state, that is, when the internal circuit 2 is performing an original operation, the switch means 51 to 56 are all open. In this state, the analog test bus 4, the switch means 51 to 56, the switch control means 6, and the buffer means 9 do not affect the operation of the internal circuit 2.

At the time of testing the integrated circuit 1, a measuring device 8 required for testing is connected to the analog test bus 4. Next, by closing the switch means provided at the inspection target location, a signal at the inspection target location is sent to the measuring device via the analog test bus 4. The buffered signal of the internal circuit (or I / O pin) can be measured at the node where the buffer means 9 is provided. The inspection of the integrated circuit 1 can be performed by measuring the inspection target portion while opening and closing the switch means as needed. As a result, the inspection of the integrated circuit 1 can be executed only by accessing the switch control signal and the analog test bus. Can be minimized. For example, if the integrated circuit 1 has 20 I / O pins and there are 10 measurement points required for the inspection, at least 10 inspection probes are conventionally contacted with the mounting substrate. Had to be done. According to the present invention, it is possible to measure 10 inspection objects of the integrated circuit 1 by using only two switch control signals and only three inspection probes to the analog test bus. By outputting these three wires to the edge of the mounting board such as a connector,
There is no need for a physical access point on the mounting board. The switch means is connected to an internal node (I /
By arranging it at a node where no signal is output from the O pin), it is possible to measure an internal node of the integrated circuit 1 which has been impossible in the past. Further, since the inspection is performed by using the buffer means 9 as necessary, a node having a high impedance or a high frequency can be measured by the analog test bus.

FIG. 3 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 3, 1 is an integrated circuit, 2
Are internal circuits having the original functions of the integrated circuit, 31, 32, 3
Reference numeral 3 denotes an I / O pin of the integrated circuit 1. 4 is an analog test bus, 51, 52, 53 are switch means for selectively connecting the output of the internal circuit 2 or the buffer means 9 and the analog test bus 4, and 54, 55, 56 are I / O pins 3.
Switch means for selectively connecting 1, 32, 33 to the analog test bus 4, and 6 are switch means 51, 5,
Switch control means for controlling opening and closing of 2, 53, 54, 55 and 56. Reference numeral 7 denotes a switch control signal generator for generating a signal for controlling the switch controller 6, and reference numeral 8 denotes a measuring device for observing the state of the analog test bus. 9 is the internal circuit 2 (or I / O pin)
Buffer means for buffering a signal from Reference numeral 10 denotes a reference voltage line, 11 denotes a reference voltage power supply, and 12 denotes an input signal changeover switch. The switch means 51 to 56 are opened and closed by controlling the switch control means 6 with a signal from the switch control signal generator 7. Here, the switch control means 7 and the switch control signal generator 8 are the same as those shown in FIG. In the following description, it is not particularly described that the opening and closing of the switch means is performed by controlling the switch control means 6 with a signal from the switch control signal generator 7. Note that in the figure, the I / O
Wiring to pins 31, 32, 33 and switch control means 6
Wiring and the like for controlling the switch means 51 to 56 are omitted.

When the integrated circuit 1 is in a normal circuit operation state, that is, when the internal circuit 2 is performing an original operation, the switch means 51 to 56 are all open. In this state, the analog test bus 4, the switch means 51 to 56, the switch control means 6, the buffer means 9, the reference voltage line 10, and the input signal changeover switch 12 do not affect the operation of the internal circuit 2.

At the time of testing the integrated circuit 1, a measuring device required for testing is connected to the analog test bus 4. Next, by closing the switch means provided at the inspection target location, a signal at the inspection target location is sent to the measuring device via the analog test bus 4. For the node provided with the buffer means, the buffered reference voltage is measured by first setting the input signal changeover switch 12 to the reference voltage line 10 side. Next, the buffered signal of the internal circuit (or I / O pin) is measured by setting the input signal switch 12 to the internal circuit (or I / O pin) side. The result of measuring the reference voltage is the reference voltage power supply 11
If the voltage is different from the voltage supplied from, it can be determined that there is an influence of noise or the like at the time of measurement, and the degree of the influence is subtracted from the result of measurement of the internal circuit (or I / O pin) to obtain a more accurate measurement The result can be obtained. In the same manner, the inspection of the integrated circuit 1 can be performed by measuring the inspection target portion while opening and closing the switch means as needed.
As a result, the inspection of the integrated circuit 1 can be executed only by accessing the switch control signal and the analog test bus. Can be minimized. For example, the integrated circuit 1 has 20 I / Os.
10 pins required for inspection
If so, at least ten inspection probes had to be brought into contact with the mounting board in the past.
According to the present invention, it is possible to measure 10 inspection targets of the integrated circuit 1 by using only two switch control signals, an analog test bus, and only four inspection probes to the reference voltage line. By outputting these four wires to the edge of the mounting board such as a connector, a physical access point on the mounting board becomes unnecessary. Further, the switch means is connected to an internal node of the internal circuit 2 (a node where no signal is output to the I / O pin).
, The measurement of the internal nodes of the integrated circuit 1, which has been impossible in the past, becomes possible. Further, since the inspection is performed by using the buffer means 9 as necessary, a node having a high impedance or a high frequency can be measured by the analog test bus. In addition, by using the result of measuring the reference voltage power supply 11, accurate measurement can be performed in consideration of the influence of noise and the like.

FIG. 4 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 4, 1 is an integrated circuit, 2
Are internal circuits having the original functions of the integrated circuit, 31, 32, 3
Reference numeral 3 denotes an I / O pin of the integrated circuit 1. 4 is an analog test bus, 51, 52, 53 are switch means for selectively connecting the output of the internal circuit 2 or the sampling means 13 and the analog test bus 4, and 54, 55, 56 are I / O pins 3
Switch means for selectively connecting 1, 32, 33 to the analog test bus 4, and 6 are switch means 51, 5,
Switch control means for controlling opening and closing of 2, 53, 54, 55 and 56. Reference numeral 7 denotes a switch control signal generator for generating a signal for controlling the switch controller 6, and reference numeral 8 denotes a measuring device for observing the state of the analog test bus. Reference numeral 13 denotes a sampling unit that samples a signal from the internal circuit 2 (or the I / O pin), and 14 denotes a sampling pulse generator that supplies a sampling pulse to the sampling unit 13. As an example, the sampling unit 13 includes a capacitance element, a switch that applies a voltage to the capacitance element in synchronization with the sampling pulse, and shuts off the voltage, and a buffer for buffering the voltage of the capacitance element. A buffer may not be necessary depending on the node to be used and the frequency of the sampling pulse. Switch means 51, 52, 53, 54, 55, 5
The switch 6 is opened and closed by controlling the switch control means 6 with a signal from the switch control signal generator 7. Here, the switch control means 7 and the switch control signal generator 8 are the same as those shown in FIG. In the following description, it is not particularly described that the opening and closing of the switch means is performed by controlling the switch control means 6 with a signal from the switch control signal generator 7. In the figure, wiring from the internal circuit 2 to the I / O pins 31 to 33, wiring for controlling the switch means 51 to 56 from the switch control means 6, and the like are omitted.

When the integrated circuit 1 is in a normal circuit operation state, that is, when the internal circuit 2 is performing an original operation, the switch means 51 to 56 are all open. In this state, the analog test bus 4, the switch means 51, 52, 53, 5
4, 55, 56, the switch control means 6, and the sampling means 9 do not affect the operation of the internal circuit 2.

At the time of testing the integrated circuit 1, a measuring device 8 required for testing is connected to the analog test bus 4. Next, by closing the switch means provided at the inspection target location, a signal at the inspection target location is sent to the measuring device via the analog test bus 4. For the node provided with the sampling means, the sampled signal from the internal circuit (or I / O pin) can be measured by the sampling signal from the sampling pulse generator 14.

As a first example of the test, a case where the signal to be measured is a high-frequency periodic signal will be described. If the frequency of the signal under measurement is 1 GHz, it is usually difficult to observe this signal with the measuring device 8 via the analog test bus 4. A measuring device for measuring a frequency of 1 GHz is expensive,
Further, since the analog test bus has a wiring capacity, the measurement environment becomes worse as the frequency of the signal under measurement is higher.
When a signal to be measured of 1 GHz is sampled and measured with a sampling pulse of 1 MHz which is generally a fraction of an integer, for example, one thousandth, the measured signal is the signal to be measured. Frequency components of 1 GHz, 1 GHz + 1 MHz, 1 GHz-1 MHz, and 1 MHz are included. It is an inexpensive measuring device by measuring the lowest 1MHz component of this frequency component using a low-pass filter, and the signal to be measured is converted to a low frequency, so the influence of the wiring capacity of the analog test bus is small. It can be measured in the state.

As a second example of the inspection, a case will be described in which, at the time of sampling, sampling is performed by giving a sampling signal having a delay time set in synchronization with the system clock of the integrated circuit 1.
Since the operation of the internal circuit 2 changes in synchronization with the system clock, the signal under measurement is a periodic signal synchronized with the system clock. A signal sampled from the signal under measurement is measured using a sampling pulse whose phase is shifted from the system clock by Δt. By sampling the signal to be measured synchronized with the system clock with a shift of Δt from the system clock, a certain point of the signal to be measured is sampled. It will be converted to a level. Next, when the sampling pulse is sampled with a shift of Δt + α, another constant point of the signal under measurement is sampled, and a signal converted to a DC level can be measured. Similarly, the original waveform can be reproduced by shifting the phase by the required number of times and plotting the measured DC level signal in accordance with the shifted phase. When the internal circuit is not operating normally, the sampled signal has a frequency component according to the error, so that an abnormality of the internal circuit can be detected.

As described above, when the present invention is used, a high-speed waveform can be converted into a low-frequency waveform at the time of inspection, so that measurement can be performed with a low-speed and inexpensive measuring device. Since the high-speed waveform is converted into a low-frequency waveform, the influence of the wiring capacity of the analog test bus on the measurement can be reduced. In addition, since the inspection of the integrated circuit 1 can be performed only by accessing the switch control signal, the sampling pulse signal, and the analog test bus, the inspection is physically performed for all the inspection target portions, which has been conventionally required. The number of test probes can be minimized. For example, integrated circuit 1
Has 20 I / O pins, and if there are 10 measurement points required for inspection, it is necessary to contact at least 10 inspection probes with the mounting substrate in the related art. Was. According to the present invention, the test object 10 of the integrated circuit 1 is tested by using only two test signals for the switch control signal, the analog test bus, and the sampling pulse input.
It is possible to measure the location. By outputting these four wires to the edge of the mounting board such as a connector, a physical access point on the mounting board becomes unnecessary. By installing the switch means at an internal node of the internal circuit 2 (a node at which no signal is output from the I / O pin), it becomes possible to measure the internal nodes of the integrated circuit 1 which were not possible in the past. In addition, since the signal of the high-frequency node is converted to the low-frequency signal by performing the inspection using the sampling unit 13 as necessary, the measurement of the high-frequency node can be performed with a low-speed and inexpensive measuring device. Becomes possible. If necessary, the analog test bus can be connected to an internal local power supply or ground line to observe the sampled signal to monitor the internal power supply and ground noise.

Here, an example in which the sampling means 13 is used as an example of the frequency conversion means has been described. However, for example, it is also possible to use a multiplier as the frequency conversion means and amplitude-modulate the signal under measurement to perform measurement. is there.

FIG. 5 shows an example of the sampling means 13 of the present invention. In FIG. 5, reference numeral 131 denotes an input terminal of the sampling means 13. 132 is a first capacitive element, 133 is a first sampling switch that shuts off after supplying an input voltage to the capacitive element 132 in synchronization with a sampling pulse, and 134 is a capacitive element 1
It is a first buffer means for buffering 32 voltages.
135 is a second capacitive element, 136 is a second sampling switch that applies a voltage to the capacitive element 135 and then shuts off.
Is a second buffer means for buffering the voltage of the capacitor 135. 138 is an output terminal of the sampling means 13.
139 is a sampling pulse input terminal, and 140 is a logic inverter for supplying complementary pulses to the sampling switches 133 and 136, respectively.

The sampling pulse is input to the sampling pulse input terminal 139.
, The first sampling switch 133 is closed at the rising edge of the sampling pulse, and the first capacitive element 1
32, the voltage of the input terminal 131 is applied to the first capacitive element 13
2 after the charge is sufficiently accumulated in the first sampling switch 13
3 opens. At the falling edge of the sampling pulse, the second sampling switch 136 is closed this time, and the second capacitive element 13
5 is supplied with the voltage of the first capacitive element buffered by the first buffer means 134, and the second sampling switch 136 is opened after the electric charge is sufficiently accumulated in the second capacitive element 135. This prevents a signal from being output to the output terminal of the sampling unit while the electric charge is stored in the first capacitance element, as compared with the case where the signal is sampled by a single sampling unit. I can do it. That is, there is no tracking unit for the waveform input to the sampling means, and a completely sampled waveform can be obtained in all periods. Therefore, when a signal sampled by the measuring device 8 is measured, if the measurement timing is later than the sampling pulse in the case of a single sampling unit, the tracking part of the waveform is measured, causing an error. And a more accurate measurement becomes possible.

FIG. 6 shows an embodiment of the sampling means of the present invention. In FIG. 6, 1 is an integrated circuit, and 4 is an analog test bus. 13 is a sampling means, 141 is an inverting amplifier, 142 is a feedback capacitance, 143 is a feedback capacitance 14
The switch means 144 for discharging 2 models the wiring capacity of the analog test bus 4. 5
1 is a switch means, 8 is a measuring device, and 14 is a sampling pulse generator.

When inspecting the integrated circuit 1, the switching means 1
43 is closed and the feedback capacitor 142 is discharged. The measuring device 8 is connected to the output of the inverting amplifier 141. Switch means 5
1 is closed, and the sampling means 13 at the location to be measured is connected to the analog test bus 4. The sampling pulse is generated by the sampling pulse generator 14 so that the sampling means 13 samples the signal at the measured position, and the sampled signal is input to the inverting amplifier 141 via the analog test bus 4. . The inverting amplifier 141 operates according to the signal input to the inverting amplifier 141, and the electric charge output from the sampling unit 13 is transferred to the feedback capacitor 142. Since the positive input is grounded, the wiring capacitance 144 of the analog test bus 4 exists at the virtual ground point. Since there is no potential difference between the positive input and the negative input, no charge moves to the wiring capacitance 144. Assuming that the capacitance of the capacitive element included in the sampling means 13 is C1, the capacitance of the feedback capacitor 142 is C2, the charge stored in the sampling means 13 is Q1, and the voltage output from the sampling means 13 is V1, The voltage Vo appearing at the output terminal of the type amplifier is Vo = Q1 / C2 = -V1 * C1 / C2, and if C1 = C2, Vo = -V1. By measuring Vo with the measuring device 8, the voltage sampled by the sampling means 13 can be measured. As a result, it is possible to execute an accurate test with the influence of the wiring capacity of the analog test bus minimized. Since it is not necessary to provide buffer means for each sampling means, the ratio of the inspection circuit in the integrated circuit can be reduced.

FIG. 7 shows an embodiment of the sampling means of the present invention. In FIG. 7, 1 is an integrated circuit, and 4 is an analog test bus. 13 is a sampling means, and MO
It comprises an S-transistor 145 and a switch 146 for supplying an input voltage to the MOS transistor 145 by a sampling pulse and then cutting off the input voltage. 8 is a measuring device,
Reference numeral 14 denotes a sampling pulse generator.

When the sampling pulse is supplied from the sampling pulse generator 14, the sampling means 13 switches the switch 146.
Is closed, and the input voltage is applied to the gate of the MOS transistor 145. Since the MOS transistor 145 has a gate capacitance between the drain and the source, the input voltage is
The data is held in the transistor 145. At the time of inspection, the switch means 51 is closed, and the voltage held in the MOS transistor 145 is measured by the measuring device 8 connected to the analog test bus 4 to obtain a sampled signal of the internal circuit (or I / O pin). Can be measured.

FIG. 8 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 8, reference numeral 1 denotes an integrated circuit. 41 is a first analog test bus, 42 is a second analog test bus, 51 and 52 are internal circuits or I / Os.
Output from O pin (not shown) and analog test bus 4
The switch means 53 and 54 selectively connect the internal circuit or the sampling means 13 and 15 and the analog test bus 42.
Reference numerals 8 and 16 denote measuring devices for observing the state of the analog test bus. Reference numeral 10 denotes a reference voltage line, reference numeral 11 denotes a reference voltage power supply, and reference numerals 13 and 15 denote sampling means for sampling the state of an internal circuit or I / O pins. In the following description, it is not particularly described that the opening and closing of the switch means is performed by controlling the switch control means (not shown) with a signal from a switch control signal generator (not shown). The switch means is open unless otherwise specified. In the drawings, wirings that are not relevant to the description are omitted.

At the time of testing the integrated circuit 1, measuring devices required for testing are connected to the analog test buses 41 and 42. By closing the switch means 51 (when the node to be measured is an internal circuit or a node where the signal of the I / O pin can be directly observed), the internal circuit or the I / O pin is connected to the analog test bus 41.
The signal at the / O pin is output. At this time, by simultaneously closing the switch means 53, a signal from the reference voltage 11 is output to the analog test bus 42 via the reference voltage line 10. If the result measured by the measuring device 16 is different from the voltage of the reference voltage power supply 11, it can be determined that there is an influence of noise or the like at the time of the measurement, and the degree of the influence is measured by an internal circuit (or I / O pin). By subtracting from the result, a more accurate measurement result can be obtained.

By closing the switch means 52 (when the measured node is a node provided with the sampling means),
The signal of the internal circuit or the I / O pin is sampled by the sampling means 13 and output to the analog test bus 41. At this time, by simultaneously closing the switch means 54, the signal from the reference voltage 11 is sampled by the sampling means 15 via the reference voltage line 10 and output to the analog test bus 42. If the result measured by the measuring device 16 is different from the voltage of the reference voltage power supply 11, it can be determined that there is an influence of noise or the like at the time of the measurement, and the degree of the influence is measured by an internal circuit (or I / O pin). By subtracting from the result, a more accurate measurement result can be obtained. In particular, an offset voltage tends to easily appear in the sampling means, and there may be several tens of mV in some cases. However, the present invention enables accurate measurement in such a case.

In the same manner, the measurement of the inspection target portion is performed while opening and closing the switch means as necessary, thereby obtaining the integrated circuit 1.
Inspection can be performed. As a result, the inspection of the integrated circuit 1 can be executed only by accessing the switch control signal and the analog test bus. Can be minimized. For example, if the integrated circuit 1 has 20 I / O pins and there are 10 measurement points required for the inspection, at least 10 inspection probes are conventionally contacted with the mounting substrate. Had to be done. According to the present invention, the test object 10 of the integrated circuit 1 is controlled by two switch control signals, a pair of analog test buses, and a total of five test probes to a reference voltage line.
It is possible to measure the location. By outputting these five wires to the edge of the mounting board such as a connector, a physical access point on the mounting board becomes unnecessary. By installing the switch means at an internal node of the internal circuit (a node where no signal is output to the I / O pin), it becomes possible to measure the internal node of the integrated circuit 1 which has been impossible in the past. In addition, since the inspection is performed by using the sampling means as needed, a node having a high frequency can be measured by the analog test bus. In addition, by using the result of measuring the reference voltage power supply, accurate measurement can be performed in consideration of the influence of noise and the like.

FIG. 9 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 9, 1 is an integrated circuit, and 4 is an analog test bus. Reference numeral 51 denotes switch means for selectively connecting an output from an internal circuit or an I / O pin (not shown) to a first input 171 of the voltage comparison means 17, and 52 denotes a voltage of the reference voltage source 19 to a reference voltage line. 18
Are connected to the second input 172 of the voltage comparison means 17 through the switching means.
It is assumed that 52 switch control inputs are common. Reference numeral 8 denotes a measuring device for observing the signal of the comparison result output 174 of the voltage comparing means 17 via the analog test bus 4. 1
Reference numeral 4 denotes a sampling pulse generator which sends a signal to the operation pulse input 173 of the voltage comparison means 13 to generate a signal for operating the voltage comparison means 17. In the following description, it is not particularly described that the opening and closing of the switch means is performed by controlling the switch control means (not shown) with a signal from a switch control signal generator (not shown). The switch means is open unless otherwise specified. In the drawings, wirings that are not relevant to the description are omitted.

When the integrated circuit 1 is inspected, a measuring device required for the inspection is connected to the analog test bus 4. By closing the switch means 51, 52 (when the node to be measured is an internal circuit or a node where the signal of the I / O pin can be directly observed), the internal circuit or the I / O pin is input to the first input 171 of the voltage comparison means 17. As for the signal of the pin, the voltage of the reference voltage source 19 is input to the second input 172 of the voltage comparing means 17.
By sending a signal for operating the voltage comparing means 17 from the sampling pulse generator 14, the voltage comparing means 17 is operated, and the result of comparing the voltages of the first input 171 and the second input 171 is a comparison result output. 174. The voltage comparison means 13 shown in FIG. 9 outputs the comparison result output if the power supply voltage (high potential) of the integrated circuit 1 is low when the voltage of the first input 171 is higher than the second input 172, and outputs the reference voltage (low potential) if the voltage is low. (Potential) is output. When the high potential is measured by the measuring device 8 as a result of operating the voltage comparing means 17 by the sampling pulse, the reference voltage source 19
Can be determined to be lower than the voltage of the internal circuit (or I / O pin). In this case, the reference voltage is set high and the measurement is performed again. When the reference voltage is higher than the voltage of the internal circuit (or the I / O pin), a low potential is observed in the measuring device 8. In this case, the reference voltage is set low and the measurement is performed again. By measuring the voltage of the comparison result output 174 with the measuring device 8 while changing the reference voltage according to the measurement result, the voltage of the internal circuit (or I / O pin) can be finally measured.

As a method for generating the reference voltage, more efficient measurement can be performed by using a binary search method in which the potential difference between the power supply voltage of the integrated circuit 1 and the reference voltage is set as a range. As an example, when the power supply voltage is 3V and the voltage of the internal circuit is 2V, 1) the reference voltage is measured at 0V → the comparison result output is high potential 2) the reference voltage is measured at 3V → the comparison result output is low Potential 3) The reference voltage is measured at 1.5 V between 0 V and 3 V. → The comparison result output is a high potential. Since the comparison result output changes from a low potential to a high potential in the process of 2) to 3), the measured voltage is measured. 4) The reference voltage is measured at 2.25 V between 1.5 V and 3 V, and the comparison result output is a low potential 3) to 4). Since the output of the comparison result changes from the high potential to the low potential, it can be seen that the potential at the location to be measured is not less than 1.5 V and not more than 2.25 V. 5) The reference voltages are 1.5 V and 2.25 V. Intermediate 1.87
Measured at 5V → Comparative result output is high potential Since the comparison result output changes from low potential to high potential in the process from 4) to 5), the potential at the point to be measured is 1.875 or more and 2.25V or less. 6) The reference voltage is set at 2.0 between 1.875 and 2.25 V.
Measured at 625V → Comparative result output is low potential In the process from 5) to 6), the comparison result output changes from high potential to low potential, so the potential at the point to be measured is 1.875 or more and 2.0625V or less. You can see that. Similarly, if the comparison result output changes from high potential to low potential, correct the lower limit of the voltage, then measure at the middle potential in the range, and if the comparison result output changes from low potential to high potential, increase the upper limit of voltage. The voltage at the point to be measured can be finally obtained by correcting the voltage and then measuring the voltage at an intermediate potential in the range.

As described above, the inspection of the integrated circuit 1 can be executed by measuring the inspection target portion by using the voltage comparison means 17. As a result, the inspection of the integrated circuit 1 can be executed only by accessing the switch control signal and the analog test bus. Can be minimized. For example, if the integrated circuit 1 has 20 I / O pins and there are 10 measurement points required for the inspection, at least 1
It was necessary to bring zero test probes into contact with the mounting board. According to the present invention, it is possible to measure 10 inspection targets of the integrated circuit 1 by using a total of six inspection probes for two switch control signals, a pair of analog test buses, a reference voltage line, and a sampling pulse input. . By outputting these six wires to the edge of the mounting board such as a connector, a physical access point on the mounting board becomes unnecessary.
By installing the switch means at an internal node of the internal circuit (a node where no signal is output to the I / O pin), it becomes possible to measure the internal node of the integrated circuit 1 which has been impossible in the past.
The inspection circuit can be simplified by performing the inspection using the voltage comparison means 17 as necessary. In addition, since the comparison output result is measured, it is possible to perform measurement in consideration of the influence of noise and the like.

FIG. 10 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 10, 1 is an integrated circuit, 2 is an internal circuit having an intrinsic function of the integrated circuit, 31, 3
Reference numerals 2 and 33 are I / O pins of the integrated circuit 1. 41 is the first
An analog test bus, 42 is a second analog test bus, 51, 52, 53 are switch means for selectively connecting the internal circuit 2 and the analog test buses 41, 42,
Reference numerals 4 and 55 denote switch means for selectively connecting the I / O pins 31 and 32 and the analog test buses 41 and 42, and reference numeral 57 selectively connects the internal circuit 2 or the I / O pin 33 and the analog test buses 41 and 42. Or internal circuit 2
Switch means for separating the I / O pin 33 from the I / O pin 33. 6 is switch means 51, 52, 53, 54, 55,
Switch control means for controlling the opening and closing of the switch 57. 7 is a switch control signal generator for generating a signal for controlling the switch control means 6, 8 is a measuring device for observing the state of the analog test bus 41, and 81 is an observing state of the analog test bus 42. , Or a signal source for supplying a signal from the analog test bus 42. Reference numeral 9 denotes buffer means for buffering signals of the internal circuit, and reference numeral 13 denotes sampling means for sampling the signals of the internal circuit. Reference numerals 91 and 92 denote external components connected to the integrated circuit 1, where 91 is a resistor and 92 is a capacitor. Switch means 51, 52, 53, 54, 55,
The switch 57 is selectively opened and closed by controlling the switch control means 6 with a signal from the switch control signal generator 7. Since the switch control means 7 and the switch control signal generating device 8 can be easily configured by a known technique, various examples of a specific configuration and a control method are conceivable. It is assumed that all switch means can be controlled by the control based on the kinds of signals. In the following description, it is not particularly described that the opening and closing of the switch means is performed by controlling the switch control means 6 with a signal from the switch control signal generator 7. In the figure,
The wiring from the internal circuit 2 to the I / O pins 31 to 33 and the wiring for controlling the switch means 51 to 55 and 57 from the switch control means 6 are omitted.

When the integrated circuit 1 is in a normal circuit operation state, that is, when the internal circuit 2 is performing an original operation, the switch means 51 to 55, 57 are all open. In this state, the analog test buses 41 and 42 and the switch means 51 to 51
55, 57, the switch control means 6, the buffer means 9, and the sampling means 13 do not affect the operation of the internal circuit 2.

At the time of testing the integrated circuit 1, measuring devices necessary for testing are connected to the analog test buses 41 and 42. Next, by closing the switch means provided at the inspection target location, the signals at the inspection target location are converted to the analog test buses 41 and 4.
2 to the measuring device. The inspection of the integrated circuit 1 can be performed by measuring the inspection target portion while opening and closing the switch means as needed. Since a plurality of nodes can be measured simultaneously using two analog test buses, the test can be executed more efficiently than the configuration shown in FIG.

When the internal circuit 2 is inspected, the measuring device 8 is connected to the analog test bus 41 and the analog test bus 42
Is connected to a signal source 81. For example, the signal input to the internal circuit 2 via the switch means 53 is
If it has a configuration that is amplified and output via
The analog test bus 41 is connected to the output of the internal circuit 2 using the switch means 57. The analog test bus 42 is connected to the input of the internal circuit 2 using the switch means 53. In this state, the analog test bus 42
A signal is sent to the internal circuit 2 via the internal circuit 2, and the input signal amplified by the operation of the internal circuit 2 is measured by the measuring device 8 via the analog test bus 41, so that the internal circuit 2 can be inspected. By supplying a signal from one of the analog test buses, it becomes possible to inspect the internal circuit.

As a result, the inspection of the integrated circuit 1 can be performed only by accessing the switch control signal and the analog test bus. The number of test probes can be minimized. For example, if the integrated circuit 1 is 2
Assuming that there are 0 I / O pins and there are 10 measurement points required for inspection, conventionally, at least 10 inspection probes had to be brought into contact with the mounting board. . According to the present invention, it is possible to measure 10 test objects of the integrated circuit 1 by using only four test probes for two switch control signals and two analog test buses. By outputting these four wires to the edge of the mounting board such as a connector, a physical access point on the mounting board becomes unnecessary. Also, by installing the switch means at an internal node of the internal circuit 2 (a node where no signal is output to the I / O pin), the integrated circuit
Measurement of the internal nodes. Further, the buffer means 9 and the sampling means 13 can be used for measurement as required. This makes it possible to inspect high impedance nodes and high frequency nodes.

External components 91 and 92 connected to the integrated circuit
At the time of inspection, the measuring device 8 is connected to the analog test bus 41.
Is connected to a signal source 81 to the analog test bus 42.
The switch means 57 is set so that the I / O pin 33 and the internal circuit 2 are open and the I / O pin 33 and the analog test buses 41 and 42 are connected. A step wave is generated from the signal source 81, and the analog test bus 42, I
The signal is sent to external components 91 and 92 via the / O pin 33, and its transient response waveform is measured by the measuring device 8 via the analog test bus 41. In this example, the external component 91 is a resistor, 92 is a capacitive element, and the external components 91 and 92 are connected in series. The transient response characteristic of a resistor is represented by Vr = RI, where Vr is a voltage, R is a resistance value, and I is a current. The transient response characteristics of the capacitor
If c, capacity is C, and current is I, Vc = 1 / C (１ ／ Idt). Since the resistance and the capacitance element have different transient response characteristics, the transient response waveform can be measured while applying a step wave, and the impedance of the external components 91 and 92 can be measured from the measured voltage waveform. For example, when the resistor 91 and the capacitor 92 are connected as shown in the drawing,
Since the transient response characteristic is represented by Vo = (1−exp (−t / RC)), the impedance of the resistor 91 and the capacitance element 92 can be calculated by comparing the characteristic graph obtained in advance with the measurement result. You can check for correctness. The switch means 57 connects the internal circuit 2 to the I / O
Since it is separated from the pin 33, it is possible to eliminate the adverse effect of the signal from the signal source 81 on the internal circuit 2. With this, the impedance of the external component is conventionally measured by the inspection probe. However, the present invention allows the external component to be inspected by accessing two analog test buses and the switch control means. Access points can be reduced. Also, the measurement can be performed by using a sampling means provided on the I / O pin as required.

FIG. 11 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 11, reference numeral 1 denotes an integrated circuit, reference numeral 2 denotes an internal circuit having an intrinsic function of the integrated circuit, and reference numeral 31 denotes an I / O pin of the integrated circuit 1. 4 is an analog test bus, 51 is a switch for connecting the sampling means 13 and the analog test bus 4, and 52 is a switch for disconnecting the I / O pin 31. 6 is switch means 5
1, 52, switch control means for controlling the opening and closing of the current source switch transistor 62. Reference numeral 7 denotes a switch control signal generator for generating a signal for controlling the switch controller 6, and reference numeral 8 denotes a measuring device for observing the state of the analog test bus 4. 61 is a current source transistor, 6
2 is a current source switch transistor, 63 is an equalize switch transistor, 64 is a current value setting line, 65 is a current source pulse line, and 91 is a resistor. In the drawings, wires and the like that are not relevant to the description are omitted.

When the integrated circuit 1 is in a normal circuit operation state, that is, when the internal circuit 2 is performing an original operation, the switch means 51 and 52 and the current source switch transistor 62 are all open. In this state, the analog test bus 4
1, 42, switch means 51, 52, switch control means 6, sampling means 13, current source transistor 61, current source switch transistor 62, and equalize switch transistor 63 do not affect the operation of internal circuit 2.

When testing the resistor 91, the necessary measuring device 8 is connected to the analog test bus 4. Switch means 52
To disconnect the I / O pin 31 from the internal circuit 2.
The switch means 51 is closed and the sampling means 13 and the analog test bus 4 are connected. The resistance 9 is set by the current value setting line 64.
An appropriate current value of the current source transistor 61 for measuring the impedance of 1 is set. A pulse is applied from the current source pulse line 65 to operate the current source transistor 61,
A pulse current is applied to the resistor 91, the transient response characteristic is sampled by the sampling means 13, and measured by the measuring device 8, so that the impedance of the resistor 91 can be inspected. As a result, the impedance of the external component is conventionally measured by the inspection probe, but according to the present invention, the external component is accessed by accessing one analog test bus, the current value setting line, the current source pulse line, and the switch control means. Inspection of parts becomes possible, and physical access points can be reduced.

FIG. 12 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 12, 1 is an integrated circuit, 2 is an internal circuit having an original function of the integrated circuit, and 34 is an I / O circuit.
/ O pad, 35 is a dummy I / O not connected to the internal circuit.
O pad. 41 and 42 are analog test buses, 4
Reference numerals 3 and 44 denote wiring capacities of the analog test buses 41 and 42, respectively, and reference numerals 45 and 46 denote I / O pads 34 and 3 respectively.
5 is a model of the capacitance component of FIG. 57 and 58 are switch means, 8 is a measuring device, and 81 is a measuring device or a signal source. In the drawings, wires and the like that are not relevant to the description are omitted.

When the integrated circuit 1 is in a normal circuit operation state, that is, when the internal circuit 2 is performing an original operation, the switch means 51 and 52 are all open. In this state, the analog test buses 41 and 42 and the switch means 51 and 52 do not affect the operation of the internal circuit 2.

Prior to the inspection of the integrated circuit 1, the switch means 57 and 58 are controlled to disconnect the analog test bus 41 and the analog test bus 42 from all internal circuits and I / O pins. In this state, the wiring capacitances 43 and 44 of the analog test buses 41 and 42 are measured using, for example, a capacitance meter.
Next, the switch means 58 is switched to connect the dummy I / O pad 35 and the analog test bus 41, and the dummy I / O pad 35 is connected to the dummy I / O pad 35.
The capacitance of the / O pad 35 is measured. By measuring the capacitance of the analog test bus and the I / O pad prior to the inspection, errors due to those capacitances can be corrected at the time of inspection, and more accurate inspection can be performed.

FIG. 13 shows a part of an integrated circuit to which one embodiment of the present invention is applied. In FIG. 13, reference numeral 2 denotes an internal circuit having an original function of the integrated circuit, 21 denotes a model of the wiring resistance, 22, 23, and 24 denote protection resistors, and 34,
35 is an I / O pad, and 36 and 37 are protection transistors. 41 and 42 are analog test buses, and 57 and 59 are switch means. In the drawings, wires and the like that are not relevant to the description are omitted.

In manufacturing an integrated circuit, for example, when the physical distance between the switch means 57 and the I / O pad 43 is long, the wiring resistance 21 may be generated between the switch means 57 and the I / O pad 43. is there. When the potential outside the I / O pad 34 is measured using the analog test bus 41 due to the resistance component of the wiring resistance 21, a measurement error occurs when the wiring resistance is not sufficiently smaller than the external load resistance. Therefore, as between the switch means 59 and the I / O pad 35, the protection resistor 2 is connected between the I / O pad and each analog test bus or the wiring to the internal circuit.
2, 23 and 24 are provided. Thus, for example, when measuring the potential of the I / O pad 35 with the analog test bus 41, the internal resistance of the voltmeter is usually several megaohms or more,
Even if the protection resistor 22 is 1 kohm, the error is about 1%. By intentionally providing a protection resistor as shown in the figure, errors during measurement can be practically eliminated, and the inspection circuit itself such as an analog test bus and switch means can be protected from an external surge voltage or the like. .

FIG. 14 shows an I / O pad to which an embodiment of the present invention is applied. In FIG. 14 (a), 22,
23 and 24 are protection resistors, 25 is a model of a resistance component of the I / O pad, and 35 is an I / O pad. In FIGS. 14B and 14C, reference numeral 22 denotes a protection resistor;
Is the first aluminum wiring, 202 is the second aluminum wiring, 20
3 is a silicon dioxide layer, and 204 is a silicon substrate. FIG.
In (c), 205 is a diffusion layer, 206 is a third aluminum wiring, and 207 is a wiring to an analog test bus. In the drawings, wires and the like that are not relevant to the description are omitted.

FIGS. 14A and 14B show the I / O pad 3 of FIG.
5 shows an enlarged view near 5 and a physical sectional view thereof. Although the advantage of providing the protection resistor around the I / O pad 35 has been described with reference to FIG. 13, microscopically, the wiring between the bonding portion at the center of the I / O pad and the analog test bus or the internal circuit is performed. Since there is a slight resistance component 25 of the aluminum wiring, the resistance of this portion may give an error during measurement in some cases.

FIG. 14 (c) shows an improved portion in the vicinity of the I / O pad of FIG. 14 (b). A hole is made in the silicon dioxide layer 203 immediately below the bonding part and in the wiring to the analog test bus or internal circuit, and a diffusion layer is formed in the silicon substrate 204. Aluminum wiring is performed on the holes formed in the analog test bus or the wiring to the internal circuit, and wiring to the analog test bus or the internal circuit is performed. Thus, the voltage measurement by the analog test bus can be performed more accurately than the center of the bonding of the I / O pad. Further, since the diffusion layer 205 has a resistance component,
It is not necessary to provide the protective resistors 22, 23, and 24, which are conventionally intentionally provided.

FIG. 15 shows an integrated circuit to which one embodiment of the present invention is applied. In FIG. 15, 1 is an integrated circuit, 2 is an internal circuit having an intrinsic function of the integrated circuit, 31, 3
Reference numerals 2 and 33 are I / O pins of the integrated circuit 1. 4 is an analog test bus; 51, 52 and 53 are switch means for selectively connecting the internal circuit 2 and the analog test bus 4;
4, 55, 56 are switch means for selectively connecting the I / O pins 31, 32, 33 and the analog test bus 4, 6
Is a storage means, 8 is a measuring device for observing the state of the analog test bus, and 27 is a computer for reading data from the storage means 26. The storage means 26 stores in advance data useful for testing the integrated circuit 1, that is, standard voltage, standard impedance, allowable error range, parasitic capacitance, parasitic resistance, and the like at each measurement point. In the drawings, wires and the like that are not relevant to the description are omitted.

When testing the integrated circuit 1, a measuring device 8 required for testing is connected to the analog test bus 4. Next, by closing the switch means provided at the inspection target location, a signal at the inspection target location is sent to the measuring device via the analog test bus 4. The inspection target is measured while opening and closing the switch means as needed. After the inspection or before the inspection, the inspection data stored in the storage device 26 is read using the computer 27, and the data in the storage unit 26 is compared with the measurement result, or the measurement result is corrected using the data in the storage unit 26. By doing so, the inspection of the integrated circuit 1 can be executed. This eliminates the need to measure in advance the analog test bus, the parasitic capacitance of the I / O pad, the parasitic resistance, and the like, so that the inspection can be performed efficiently. In addition, when an inspection is performed by a field service or the like, the inspection can be performed without carrying an inspection specification or the like of each integrated circuit.

Although the main embodiment of the present invention has been described above, it goes without saying that various applications can be made by combining the individual claims recited in the present invention.

[0073]

As described above, according to the present invention, when inspecting an integrated circuit, the condition of the internal circuit or I / O pins of the integrated circuit can be inspected with a minimum number of inspection probes. Is obtained.

[Brief description of the drawings]

FIG. 1 is a structural diagram of an integrated circuit according to an embodiment of the present invention;

FIG. 2 is a structural diagram of an integrated circuit according to one embodiment of the present invention;

FIG. 3 is a structural view of an integrated circuit according to one embodiment of the present invention;

FIG. 4 is a structural diagram of an integrated circuit according to one embodiment of the present invention;

FIG. 5 is a structural diagram of a sampling unit according to an embodiment of the present invention.

FIG. 6 is a structural diagram of an integrated circuit in one embodiment of the present invention.

FIG. 7 is a structural diagram of a sampling unit according to an embodiment of the present invention.

FIG. 8 is a structural diagram of an integrated circuit according to one embodiment of the present invention;

FIG. 9 is a structural diagram of a voltage comparison unit according to an embodiment of the present invention.

FIG. 10 is a structural diagram of an integrated circuit in one embodiment of the present invention;

FIG. 11 is a structural diagram of an integrated circuit in one embodiment of the present invention;

FIG. 12 is a structural diagram of an integrated circuit in one embodiment of the present invention;

FIG. 13 is a structural diagram of an integrated circuit in one embodiment of the present invention;

FIG. 14 is a structural diagram of an I / O pad according to an embodiment of the present invention.

FIG. 15 is a structural diagram of an integrated circuit in one embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Integrated circuit 2 Internal circuit 4 Analog test bus 6 Switch control means 7 Switch control signal generator 8 Measuring device 31 I / O pin 32 I / O pin 33 I / O pin 51 Switching means 52 Switching means 53 Switching means 54 Switching means 55 switch means 56 switch means

Claims (38)

[Claims] 1. An apparatus for measuring a state of an internal circuit and a state of an I / O pin of an integrated circuit, wherein the analog test bus included in the integrated circuit is connected to the internal circuit or the I / O pin.
An inspection apparatus comprising: switch means for selectively connecting to the / O pin; and switch control means for controlling connection of the switch means according to a control signal. 2. An inspection apparatus according to claim 1, wherein said analog test bus is selectively connected to said internal circuit or said I / O pin using said switch control means and said switch means. An inspection method for measuring the status of the internal circuit or the I / O pins by a measurement device connected to a test bus. 3. An apparatus for measuring a state of an internal circuit of an integrated circuit and a state of an I / O pin, comprising: an analog test bus included in the integrated circuit; and a signal of the internal circuit or the I / O pin. Buffer means for buffering the analog test bus to the internal circuit or the I
An inspection apparatus comprising: switch means for selectively connecting to the / O pin directly or via the buffer circuit; and switch control means for controlling connection of the switch means according to a control signal. 4. The inspection apparatus according to claim 3, wherein the analog test bus is directly connected to the internal circuit or the I / O pin by using the switch control means and the switch means or via the buffer means. A test method for selectively connecting and measuring the status of the internal circuit or the I / O pin by a measuring device connected to the analog test bus. 5. The circuit according to claim 1, further comprising: a reference voltage power supply;
The inspection apparatus according to claim 3, further comprising an input signal changeover switch selectively connected to the / O pin or the reference power supply. 6. An inspection apparatus according to claim 5, wherein said analog test bus is selectively connected to said reference voltage power supply directly or via said buffer means using said switch control means and said switch means. Measuring the state of the reference voltage power supply by a measuring device connected to the analog test bus, and connecting the internal circuit or the I / O pin to
The analog test bus is selectively connected directly or via the buffer means using the switch control means and the switch means, and the internal circuit or the I / O pin is measured by a measuring device connected to the analog test bus. Inspection method characterized by measuring the situation of. 7. An apparatus for measuring a status of an internal circuit of an integrated circuit and a status of an I / O pin, comprising: an analog test bus included in the integrated circuit; and a signal of the internal circuit or the I / O pin. Frequency conversion means for converting a frequency in synchronization with a given frequency conversion pulse signal; and connecting the analog test bus to the internal circuit or the I
An inspection apparatus comprising: switch means for selectively connecting to the / O pin or directly via the frequency conversion means; and switch control means for controlling connection of the switch means according to a control signal. 8. An inspection apparatus according to claim 7, wherein said frequency conversion means is constituted by sampling means. 9. The inspection apparatus according to claim 8, wherein the analog test bus is connected to the internal circuit or the I / O pin by using the switch control means and the switch means via the signal sampling means. Selective connection, applying a sampling pulse, sampling the state of the internal circuit or the I / O pin to the signal sampling circuit, and measuring the internal circuit or the I / O pin by a measuring device connected to the analog test bus. An inspection method for measuring the sampled status of the / O pin. 10. The inspection method according to claim 9, wherein said sampling pulse is synchronized with a system clock for synchronizing an internal circuit of said integrated circuit, and a delay time is made variable. 11. The inspection apparatus according to claim 8, wherein said sampling means comprises a capacitance element and a switch for applying an input voltage to said capacitance element in synchronization with a sampling pulse and then shutting off. 12. The signal sampling means includes: a capacitance element; a switch for supplying an input voltage to the capacitance element in synchronization with a sampling pulse and then shutting off; and a voltage buffer means for buffering a voltage of the capacitance element. The inspection device according to claim 8, comprising: 13. The signal sampling means includes: a first capacitance element; a first switch for shutting off a supply of an input voltage to the first capacitance element in synchronization with a sampling pulse; A first voltage buffer means for buffering the voltage of the first capacitive element, and a second voltage buffer means for applying an input voltage to the second capacitive element in synchronization with an inversion pulse of the second capacitive element and the sampling pulse and then cutting off the input voltage. 2 switches, and second voltage buffer means for buffering the voltage of the second capacitor.
The inspection device according to claim 8. 14. The sampling means comprises a capacitance element and a switch for supplying an input voltage to the capacitance element in synchronization with a sampling pulse and then shutting off the input voltage. 9. The inspection apparatus according to claim 8, further comprising a feedback capacitor between an input and an output of the amplifier, transferring a charge of the capacitive element to the feedback capacitor, and using an output voltage of the inverting amplifier as an output signal. . 15. The sampling means includes a source grounded M
9. The system according to claim 8, further comprising: an OS transistor; and a switch that applies an input voltage to a gate of the MOS transistor in synchronization with a sampling pulse and then shuts off, and uses a drain current of the MOS transistor as an output signal. Inspection equipment. 16. The status and I / O of an internal circuit of an integrated circuit.
An apparatus for measuring a state of a pin, wherein a pair of analog test buses included in the integrated circuit and a signal of the internal circuit or the I / O pin are sampled in synchronization with a given sampling pulse. A first signal sampling means, a reference voltage, a second signal sampling means for sampling the reference voltage in synchronization with a given sampling pulse, and the pair of analog test buses connected to the internal circuit or Switch means for selectively connecting to the I / O pin directly or via the first and second signal sampling means; and switch control means for controlling connection of the switch means according to a control signal. Inspection equipment to have. 17. The inspection apparatus according to claim 16, wherein
The analog test bus is selectively connected to the reference voltage via the second signal sampling means using the switch control means and the switch means, and a sampling pulse is applied to change the reference voltage to the reference voltage. 2, the sampled state of the reference voltage power supply is measured by a measuring device connected to the analog test bus, and the switch control means is connected to the internal circuit or the I / O pin. The analog test bus is selectively connected to the analog test bus via the first sampling means using the switch means and a sampling pulse is applied to change the state of the internal circuit or the I / O pin to the first sampling signal. A test method of sampling the sampling circuit and measuring the sampled state of the internal circuit or the I / O pin by a measuring device connected to the analog test bus. 18. The status and I / O of an internal circuit of an integrated circuit.
An apparatus for measuring a status of a pin, comprising: an analog test bus included in the integrated circuit; a reference voltage capable of changing a voltage; and a signal of the internal circuit or the I / O pin synchronized with a given trigger. Voltage comparing means for comparing the analog test bus with the internal circuit or the I
An inspection device comprising: switch means for selectively connecting to the / O pin directly or via the voltage comparison means; and switch control means for controlling connection of the switch means in accordance with a control signal. 19. An inspection apparatus according to claim 18, wherein said analog test bus is selectively connected to said internal circuit or said I / O pin using said switch control means and said switch means via said voltage comparison means. And a trigger is provided to the comparing means while changing the reference voltage, and a measuring device connected to the analog test bus measures a comparison result from the comparing means. 20. The inspection method according to claim 19, wherein voltage control means for sequentially generating a voltage using a binary search method according to an output of said voltage comparison means is used as said reference voltage. 21. Status and I / O of an internal circuit of an integrated circuit
An apparatus for measuring a status of a pin, wherein a first and a second pair of analog test buses included in the integrated circuit are selectively connected to the internal circuit or the I / O pin. An inspection apparatus comprising: switch means for connecting; and switch control means for controlling connection of the switch means according to a control signal. 22. The inspection apparatus according to claim 21, wherein
The pair of analog test buses are selectively connected to the internal circuit or the two points of the I / O pin using the switch control means and the switch means, respectively, and are respectively connected to the pair of analog test buses. An inspection method for measuring two different states of the internal circuit or the I / O pins by a measuring device. 23. The inspection apparatus according to claim 21, wherein
The input of the internal circuit is connected to the first analog test bus using the switch control means and the switch means, and the output of the internal circuit is connected to the second analog test bus using the switch control means and the switch means. The first analog test bus is connected to a signal generator, and a signal is sent to an input of the internal circuit so that the internal circuit is in an operation state. An inspection method for measuring the state of the internal circuit by a measurement device connected to a bus. 24. The inspection apparatus according to claim 21, further comprising an internal circuit disconnecting switch controlled by said switch control means for controlling conduction between said I / O pin and an internal circuit. 25. An inspection apparatus according to claim 24, wherein said internal circuit disconnecting switch is opened by said switch control means, and said first analog test bus is connected to said I / O pin by said connection means. The second analog test bus is connected to the / O pin by the connection means, and a step wave is applied from the signal generation means connected to the first analog test bus, and the transient response waveform is converted to the second analog test bus. An inspection method for measuring an impedance of a circuit under test connected to the I / O pin by measuring in a time domain by a measuring device connected to a bus. 26. A buffer means for buffering a signal of the internal circuit or the I / O pin, and selectively connecting the pair of analog test buses to the internal circuit or the I / O pin directly or via the buffer means. 22. The inspection apparatus according to claim 21, further comprising: switch means connected to the inspection apparatus. 27. A signal sampling means for sampling a signal of said internal circuit or said I / O pin in synchronization with a given sampling pulse, and said pair of analog test buses being connected to said internal circuit or said I / O pin. 22. Switch means selectively connected to the / O pin directly or via said signal sampling means.
Inspection device as described. 28. The test apparatus according to claim 27, wherein said internal circuit disconnection switch is opened by said switch control means, and said first analog test bus is connected to said I / O pin by said connection means. The second analog test bus is connected to the / O pin by the connecting means, and a step wave is given by the signal generating means connected to the first analog test bus, and the transient response waveform is synchronized with the step wave. The delay time is detected by a signal sampling means that is provided with a sampling pulse by a sampling signal obtained by sweeping the delay time, and is measured in a time domain by a measuring device connected to the second second analog test bus. I / O
An inspection method for measuring the impedance of a circuit under test connected to a pin. 29. The inspection apparatus according to claim 8, further comprising a transistor forming a current source at a location to be measured. 30. An inspection apparatus according to claim 21, wherein said switch control means has an operation mode in which said pair of analog buses are not connected to all said internal circuits and I / O pins. 31. An inspection apparatus according to claim 30, wherein said pair of analog buses are connected to all said internal circuits and said I bus.
An inspection method that releases the / O pin and measures the parasitic capacitance of the pair of analog buses. 32. The inspection apparatus according to claim 21, further comprising a dummy I / O pad that is not connected to another circuit. 33. The inspection apparatus according to claim 32, wherein the pair of analog test buses are connected to the dummy I / O pad using the switch means and the switch control means. An inspection method for measuring a parasitic capacitance of an I / O pad. 34. A system according to claim 21, further comprising a plurality of analog test buses in addition to said pair of test buses, and switch means for selectively connecting said plurality of analog test buses to said internal circuit or said I / O pins. Inspection device as described. 35. The inspection apparatus according to claim 21, wherein the switch means connected to the I / O pad connects switches of the pair of analog test buses to the I / O pad via respective resistors. 36. The I / O pad is connected from a center of the pad via a resistor or a conductor to a conductor of the pair of analog test buses connected to a second analog test bus connecting a measuring device. Item 35. The inspection device according to Item 35. 37. An inspection apparatus having storage means for storing information required for inspection such as a standard voltage, a standard impedance, an allowable error range, a parasitic capacitance and a parasitic resistance of each measurement point in an integrated circuit. 38. The inspection apparatus according to claim 37, wherein the determination as to whether the inspection is normal or not is made by comparing the information stored in the storage means with the measurement result at the point to be measured. Inspection method.