JP2003185711A - Inspection device - Google Patents

Inspection device

Info

Publication number
JP2003185711A
JP2003185711A JP2002290931A JP2002290931A JP2003185711A JP 2003185711 A JP2003185711 A JP 2003185711A JP 2002290931 A JP2002290931 A JP 2002290931A JP 2002290931 A JP2002290931 A JP 2002290931A JP 2003185711 A JP2003185711 A JP 2003185711A
Authority
JP
Japan
Prior art keywords
pad
switch means
analog test
pair
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002290931A
Other languages
Japanese (ja)
Inventor
Akira Matsuzawa
昭 松澤
Atsushi Kukutsu
厚士 九々津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002290931A priority Critical patent/JP2003185711A/en
Publication of JP2003185711A publication Critical patent/JP2003185711A/en
Pending legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To inspect an internal circuit of an integrated circuit or a condition of an I/O pin thereof, using the minimum of inspection probes. <P>SOLUTION: In this device, switch means 57, 59 are provided to connect analog test buses 41, 42 included in the integrated circuit selectively to the internal circuit 2 or the I/O pin, the connection of the switch means is controlled in response to a control signal, and switches for a pair of analog test buses are connected to an I/O pad 43 via resistances 22-24 respectively, in the switch means connected to the I/O pad 43. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体集積回路の
検査装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit inspection device.

【0002】[0002]

【従来の技術】従来の回路検査方法は、部品が実装され
たプリント回路基板の配線や部品に対して検査プローブ
を接触させることで検査を行い、効率的な故障箇所の診
断により有効な検査方法として利用されている。実装基
板上での部品検査においては、例えばアナログICは比
較的ピン数も少なく、プリント回路基板上に設けられた
テストポイントに検査用プローブを接触させ、その出力
信号を観測することで比較的容易に検査が実行できてい
た。
2. Description of the Related Art A conventional circuit inspection method is an effective inspection method for efficiently diagnosing a fault location by inspecting a wiring or a component of a printed circuit board on which a component is mounted by contacting an inspection probe. Is used as. For component inspection on a mounting board, for example, an analog IC has a relatively small number of pins, and it is comparatively easy to bring an inspection probe into contact with a test point provided on a printed circuit board and observe its output signal. I was able to carry out the inspection.

【0003】[0003]

【非特許文献1】“Integrating design and Test :Usi
ng CAE Tools for ATE Programing”,K.P.Parker,IEEE
Computer Society Press, Los Alamitos CA, 1987
[Non-Patent Document 1] "Integrating design and Test: Usi
ng CAE Tools for ATE Programming ”, KPParker, IEEE
Computer Society Press, Los Alamitos CA, 1987

【0004】[0004]

【発明が解決しようとする課題】しかしながら、近年の
電子機器の小型化、高機能化に伴い、ICの高集積化、
プリント回路基板の高密度実装化が急速に進んでいる。
このため検査用のプローブを使用した回路検査方法はそ
の有用性を失ってきている。実装基板の高密度化に加え
て高集積化、或いはディジタルICと混在して集積され
ることによる多ピン化により検査プローブを接触させる
ことも困難になり、アナログICの検査は困難になって
きた。
However, with the recent miniaturization and higher functionality of electronic equipment, higher integration of ICs,
High-density mounting of printed circuit boards is rapidly advancing.
For this reason, the circuit inspection method using the inspection probe has lost its usefulness. In addition to the high density of the mounting board, high integration, or the increased number of pins due to mixed integration with a digital IC makes it difficult to bring the inspection probe into contact, and inspection of the analog IC has become difficult. .

【0005】本発明は、集積回路の内部回路もしくはI
/Oピンの状況を最小限の検査用プローブで検査する集
積回路の検査装置を提供することを目的とする。
The present invention relates to an internal circuit of an integrated circuit or I
An object of the present invention is to provide an inspection device for an integrated circuit that inspects the status of the / O pin with a minimum inspection probe.

【0006】[0006]

【課題を解決するための手段】この課題を解決するため
に本発明は、集積回路に含まれる第1、第2の一対のア
ナログテストバスと、前記一対のアナログテストバスを
内部回路もしくはI/Oピンに選択的に接続するスイッ
チ手段と、制御信号に応じて前記スイッチ手段の接続を
制御するスイッチ制御手段とを有し、前記スイッチ手段
において、I/Oパッドに接続されるスイッチ手段は前
記一対のアナログテストバスのスイッチをそれぞれ抵抗
を介してI/Oパッドに接続したことを特徴とする。
In order to solve this problem, the present invention provides a pair of first and second analog test buses included in an integrated circuit and an internal circuit or an I / O circuit for the pair of analog test buses. The switch means has a switch means selectively connected to the O pin and a switch control means for controlling connection of the switch means according to a control signal. In the switch means, the switch means connected to the I / O pad is the above-mentioned. The switch of the pair of analog test buses is connected to the I / O pad via a resistor, respectively.

【0007】[0007]

【発明の実施の形態】図1は本発明の一実施の形態を適
用した集積回路の一部を示している。図1において、2
は集積回路本来の機能を持つ内部回路、21は配線抵抗
をモデル化したもの、22、23、24は保護抵抗、3
4,35はI/Oパッド、36、37は保護トランジス
タである。41,42はアナログテストバス、57,5
9はスイッチ手段である。尚図中では説明に関係のない
配線等は省略されている。
FIG. 1 shows a part of an integrated circuit to which an embodiment of the present invention is applied. In FIG. 1, 2
Is an internal circuit having the original function of the integrated circuit, 21 is a model of wiring resistance, 22, 23 and 24 are protective resistances, 3
Reference numerals 4 and 35 are I / O pads, and 36 and 37 are protection transistors. 41 and 42 are analog test buses and 57 and 5
9 is a switch means. It should be noted that wiring and the like not related to the description are omitted in the drawing.

【0008】集積回路を製造する際に、一例としてスイ
ッチ手段57とI/Oパッド43の物理的距離が長かっ
た場合に、スイッチ手段57とI/Oパッド43間に配
線抵抗21が生じる場合がある。配線抵抗21の抵抗成
分により、アナログテストバス41を使ってI/Oパッ
ド34の外部に電位を測定する場合に、配線抵抗が外部
の負荷抵抗より十分小さくない場合に測定誤差を生じ
る。そこでスイッチ手段59とI/Oパッド35間のよ
うに、I/Oパッドからそれぞれのアナログテストバ
ス、或いは内部回路への配線の間にそれぞれ保護抵抗2
2,23,24を設ける。
In manufacturing an integrated circuit, as an example, when the physical distance between the switch means 57 and the I / O pad 43 is long, a wiring resistance 21 may occur between the switch means 57 and the I / O pad 43. is there. Due to the resistance component of the wiring resistance 21, when measuring the potential outside the I / O pad 34 using the analog test bus 41, a measurement error occurs if the wiring resistance is not sufficiently smaller than the external load resistance. Therefore, a protective resistor 2 is provided between the I / O pad and each analog test bus or the wiring to the internal circuit, such as between the switch means 59 and the I / O pad 35.
2, 23, 24 are provided.

【0009】これにより例えばアナログテストバス41
でI/Oパッド35の電位を測定する場合、電圧計の内
部抵抗は通常数メガオーム以上であり、仮に保護抵抗2
2が1キロオームであったとしても誤差は1%程度であ
る。保護抵抗を図に示すように意図的に設けることによ
り測定時の誤差を実用上なくすことができ、またアナロ
グテストバス、スイッチ手段等の検査回路自身を外部の
サージ電圧等から保護することができる。
Thus, for example, the analog test bus 41
When measuring the potential of the I / O pad 35 with, the internal resistance of the voltmeter is usually several megohms or more.
Even if 2 is 1 kilohm, the error is about 1%. By intentionally providing a protective resistor as shown in the figure, errors during measurement can be practically eliminated, and the test circuit itself such as the analog test bus and switch means can be protected from external surge voltage, etc. .

【0010】図2は本発明の一実施の形態を適用したI
/Oパッドを示している。図2(a)において22,2
3,24は保護抵抗、25はI/Oパッドの抵抗成分を
モデル化したものであり、35はI/Oパッドである。
図2(b)、(c)において、22は保護抵抗、201は第
1のアルミ配線、202は第2のアルミ配線、203は
二酸化珪素層、204は珪素の基板である。
FIG. 2 shows an I to which an embodiment of the present invention is applied.
/ O pad is shown. 2 and 2 in FIG.
3 and 24 are protection resistors, 25 is a model of the resistance component of the I / O pad, and 35 is an I / O pad.
In FIGS. 2B and 2C, 22 is a protective resistor, 201 is a first aluminum wiring, 202 is a second aluminum wiring, 203 is a silicon dioxide layer, and 204 is a silicon substrate.

【0011】図2(c)において205は拡散層、206
は第3のアルミ配線、207はアナログテストバスへの
配線である。尚図中では説明に関係のない配線等は省略
されている。
In FIG. 2C, 205 is a diffusion layer and 206
Is a third aluminum wiring, and 207 is a wiring to the analog test bus. It should be noted that wiring and the like not related to the description are omitted in the drawing.

【0012】図2(a) 、(b)は図1のI/Oパッド3
5近傍の拡大図とその物理的断面図を示している。図1
でI/Oパッド35周辺のように保護抵抗を設けること
の利点を説明したが、ミクロ的にはI/Oパッドの中心
のボンディング部分からアナログテストバス、或いは内
部回路への配線の間にアルミ配線の抵抗成分25が僅か
に存在するため、場合によってはこの部分の抵抗が測定
時に誤差を与える。
2 (a) and 2 (b) show the I / O pad 3 of FIG.
5 shows an enlarged view of the vicinity of No. 5 and its physical sectional view. Figure 1
Although the advantage of providing the protective resistance around the I / O pad 35 has been described above, in a microscopic sense, aluminum is provided between the bonding portion at the center of the I / O pad and the analog test bus or the wiring to the internal circuit. Since there is a slight resistance component 25 of the wiring, the resistance of this portion may cause an error during measurement in some cases.

【0013】図2(c)は図2(b)のI/Oパッドの近傍
部分に対して改良を加えたものである。ボンディング部
分の直下及びアナログテストバス、或いは内部回路への
配線部分に二酸化珪素層203に穴を開け、珪素基板2
04に拡散層を生成する。アナログテストバス、或いは
内部回路への配線部分に開けた穴の部分にアルミ配線を
行い、アナログテストバス、或いは内部回路への配線を
行う。
FIG. 2C is an improvement of the portion near the I / O pad of FIG. 2B. A hole is formed in the silicon dioxide layer 203 immediately below the bonding portion and in the wiring portion to the analog test bus or the internal circuit, and the silicon substrate 2 is formed.
A diffusion layer is generated at 04. Aluminum wiring is provided in a hole formed in a wiring portion to the analog test bus or the internal circuit, and wiring to the analog test bus or the internal circuit is performed.

【0014】このことで、アナログテストバスによる電
圧の測定が、I/Oパッドのボンディングの中心よりよ
り正確に行える。また拡散層205が抵抗成分を持つた
め、従来意図的に設けていた保護抵抗22,23,24
を設ける必要がなくなる。
Thus, the voltage measurement by the analog test bus can be performed more accurately than the center of I / O pad bonding. Further, since the diffusion layer 205 has a resistance component, the protection resistors 22, 23, and 24 which are conventionally intentionally provided are provided.
It becomes unnecessary to provide.

【0015】[0015]

【発明の効果】以上のように本発明によれば、アナログ
テストバスを使った測定の際にスイッチの抵抗が測定系
に与える影響を少なくすることができる。
As described above, according to the present invention, it is possible to reduce the influence of the resistance of the switch on the measurement system during measurement using the analog test bus.

【0016】さらに、I/Oパッドは、パッドの中心よ
り抵抗もしくは導体を介して一対のアナログテストバス
のうち測定装置を接続する第2のアナログテストバスに
接続される導体へ接続したことにより、アナログテスト
バスを使った測定の際にスイッチの抵抗が測定系に与え
る影響をさらに少なくすることができる。
Further, the I / O pad is connected from the center of the pad to the conductor connected to the second analog test bus for connecting the measuring device of the pair of analog test buses via the resistor or the conductor, The effect of the switch resistance on the measurement system during measurement using the analog test bus can be further reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施の形態における集積回路の構造
FIG. 1 is a structural diagram of an integrated circuit according to an embodiment of the present invention.

【図2】本発明の一実施の形態におけるI/Oパッドの
構造図
FIG. 2 is a structural diagram of an I / O pad according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

2 内部回路 22,23,24 保護抵抗 34,35 I/Oパッド 41,42 アナログテストバス 57,59 スイッチ手段 2 Internal circuit 22,23,24 Protective resistance 34,35 I / O pad 41,42 Analog test bus 57,59 switch means

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】集積回路の内部回路の状況およびI/Oピ
ンの状況を測定する装置であって、前記集積回路に含ま
れる第1、第2の一対のアナログテストバスと、前記一
対のアナログテストバスを前記内部回路もしくは前記I
/Oピンに選択的に接続するスイッチ手段と、制御信号
に応じて前記スイッチ手段の接続を制御するスイッチ制
御手段とを有し、前記スイッチ手段において、I/Oパ
ッドに接続されるスイッチ手段は前記一対のアナログテ
ストバスのスイッチをそれぞれ抵抗を介してI/Oパッ
ドに接続した検査装置。
1. An apparatus for measuring a status of an internal circuit and an status of an I / O pin of an integrated circuit, comprising first and second pair of analog test buses included in the integrated circuit, and the pair of analogs. The test bus is connected to the internal circuit or the I
A switch means selectively connected to the / O pin and a switch control means for controlling the connection of the switch means in response to a control signal. In the switch means, the switch means connected to the I / O pad is An inspection apparatus in which switches of the pair of analog test buses are connected to I / O pads via resistors, respectively.
【請求項2】前記I/Oパッドは、パッドの中心より抵
抗もしくは導体を介して前記一対のアナログテストバス
のうちの測定装置を接続する第2のアナログテストバス
に接続される導体へ接続した請求項1記載の検査装置。
2. The I / O pad is connected from the center of the pad to a conductor connected to a second analog test bus connecting a measuring device of the pair of analog test buses via a resistor or a conductor. The inspection apparatus according to claim 1.
JP2002290931A 2002-10-03 2002-10-03 Inspection device Pending JP2003185711A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002290931A JP2003185711A (en) 2002-10-03 2002-10-03 Inspection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002290931A JP2003185711A (en) 2002-10-03 2002-10-03 Inspection device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP09702797A Division JP3508460B2 (en) 1997-04-15 1997-04-15 Inspection apparatus and inspection method for integrated circuit

Publications (1)

Publication Number Publication Date
JP2003185711A true JP2003185711A (en) 2003-07-03

Family

ID=27606668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002290931A Pending JP2003185711A (en) 2002-10-03 2002-10-03 Inspection device

Country Status (1)

Country Link
JP (1) JP2003185711A (en)

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