JP2001196522A - Printed wiring board and multichip module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct electrical connection to the embedded bare chip of a semiconductor element without through a bonding process which requires an exclusive facility such as for wire bonding and flip chip bonding, and to arrange a conductive layer and a electronic circuit on an insulating layer covering the buried bear chip to cover the bare chip. SOLUTION: The bare chip 20 of the semiconductor element, which has plural connection electrode 21 and 22, is embedded in a printed wiring board 10. The insulating layer 16 of the printed wiring board 10, which covers the bare chip 20, has plural via holes 19a and 19b, to which the connection electrodes 21 and 22 of the bare chip 20 are exposed. The connection electrodes 21 and 22 of the bare chip 20 are electrically connected to the corresponding part of the conductive layer 17 of the printed wiring board 10, which is formed on the insulating layer 16, via the via holes 19a and 19b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and a multi-chip module, and more particularly, to a printed wiring board in which a bare chip of a semiconductor element is embedded and a plurality of printed circuit boards mounted on the printed wiring board. The present invention relates to a multi-chip module having a semiconductor element chip mounted thereon.

[0002]

2. Description of the Related Art When mounting a bare chip of a semiconductor element such as a semiconductor integrated circuit on a printed wiring board, a wire bonding method for connecting using conductive wires or a flip chip for connecting using conductive bumps is used. Generally, the connection electrodes of the bare chip are electrically connected to the wiring on the printed wiring board by using a bonding method. However, to perform these bonding methods, expensive dedicated equipment is required, and after the bonding is completed, there is a problem that a work of sealing a bare chip mounted on a printed wiring board with a resin is required. . In addition, since the sealing resin covers a wider area than the mounted bare chip, other electronic components cannot be mounted not only on the area where the bare chip is mounted but also on the area covered with the sealing resin. There is also a problem that there is a problem in improving the quality. Therefore, in order to solve or suppress these problems, various improvement plans have been conventionally developed and proposed.

Japanese Unexamined Patent Application Publication No. 9-8213 discloses a technique in which a two-stage recess or hole is provided inside a multilayer wiring board, and a bare chip of a semiconductor element is mounted in the recess or hole. ing. The bare chip of the semiconductor element is buried in the lower part of the recess or the hole. The bonding wire for electrically connecting the bare chip to the wiring of the multilayer wiring board is buried in the upper part (wider than the lower part) of the recess or hole. The sealing resin is filled in the entire recess or hole by screen printing so as not to protrude from the recess or hole. For this reason, in this conventional technique, the area covered by the sealing resin is the same as the size of the concave portion or the hole, and as a result, the area required for resin sealing can be reduced. That is, it is possible to solve the above-mentioned problem related to the improvement of the mounting density.

[0004] Although a bare chip of a semiconductor element is not buried, the prior art related to the present invention is disclosed in Japanese Patent Laid-Open No. 5-3 / 1993.
No. 27228 and JP-A-9-270367.

Japanese Patent Application Laid-Open No. 5-327228 discloses a multilayer printed wiring board having an adhesive layer covering an inner-layer conductor circuit, wherein electronic circuit components are mounted on the inner-layer conductor circuit, and the inner-layer conductor circuit and an upper or lower part are mounted. There is disclosed a technique for making an electrical connection with a conductive circuit layer through a through hole or a via hole formed in the multilayer printed wiring board. According to this conventional technique, since the electronic circuit component is mounted together with the inner layer circuit (not the outer layer circuit) of the multilayer printed wiring board, a sealing resin for covering the electronic circuit component is not required, and the adhesive layer is not required. Another electronic circuit component can be mounted so as to overlap the electronic circuit component embedded above. Therefore, the above-described problems relating to the resin sealing and the improvement of the mounting density can be solved.

In Japanese Patent Application Laid-Open No. 9-270367, a first circuit element such as an inductance, a conductive path, and a capacitance is embedded and formed in an insulating substrate, and a similar second circuit element is formed on the insulating substrate. The first and second
Through the electrical connection between the circuit elements
A technique performed via the formed via-hole conductor is disclosed. These via-hole conductors are used as terminal electrodes of the first circuit element. According to this conventional technique, a via-hole conductor for electrically connecting the first and second circuit elements is used as a terminal electrode, so that the composite electronic component or the circuit module can be reduced in size and thickness. Become.

[0007]

However, the above-mentioned prior art has the following problems.

In the prior art disclosed in Japanese Patent Application Laid-Open No. 9-8213, connection between a wiring layer of a printed wiring board and an electrode of a bare chip of a buried semiconductor element is performed by wire bonding. For this reason, dedicated equipment for wire bonding is required. In addition, since the sealing resin that covers the bare chip is exposed on the surface of the concave portion or the hole portion of the printed wiring board, an electronic component smaller than the conductive layer for wiring or the bare chip is disposed on the sealing resin. Can not.

In the prior art disclosed in Japanese Patent Application Laid-Open No. Hei 5-327228, an electronic circuit component embedded in the inner-layer conductor circuit is electrically connected to the inner-layer conductor circuit by soldering. As in the case of the prior art disclosed in Japanese Patent No. 8213, a soldering step is required. Further, what is buried in the inner conductor circuit is limited to electronic circuit components, and there is no mention of burying a bare chip of a semiconductor element. Further, it is difficult to apply this conventional technique to a bare chip of a semiconductor element.

[0010] In the prior art disclosed in Japanese Patent Application Laid-Open No. 9-270367, what is buried in the insulating substrate is limited to a circuit element such as an inductance, and a case where a bare chip of a semiconductor element is buried is mentioned. Absent.
Further, it is impossible to apply this conventional technique to a bare chip of a semiconductor element for the following reasons.

That is, in this prior art, a via-hole conductor penetrated and formed in an insulating substrate is used for electrical connection. Therefore, when the first circuit element embedded in the insulating substrate is a bare chip of a semiconductor element, It is necessary to penetrate and form the same number of via-hole conductors as the number of connection electrodes of the bare chip on the insulating substrate at a small pitch. However, such a task is extremely difficult or impossible.

An object of the present invention is to provide a printed wiring board and a printed wiring board capable of electrically connecting a buried semiconductor element to a bare chip without going through a bonding step such as wire bonding or flip chip bonding which requires dedicated equipment. To provide a multi-chip module.

Another object of the present invention is to dispose a conductive layer or mount another electronic circuit component on an insulating layer covering a bare chip of a buried semiconductor element so as to overlap the bare chip. It is to provide a printed wiring board and a multi-chip module.

Still another object of the present invention is to provide a printed wiring board and a multi-chip module capable of simplifying a bonding step of a buried semiconductor element to a bare chip and improving the mounting density of electronic circuit components. It is in.

[0015]

(1) A printed wiring board according to the present invention comprises: a first bare chip of a semiconductor element having a plurality of connection electrodes; a first insulating layer covering the first bare chip; A first conductive layer formed on an insulating layer, wherein the first insulating layer has a first group of via holes exposing a connection electrode of the first bare chip, and the connection electrode Are electrically connected to corresponding portions of the first conductive layer through the first group of via holes.

(2) In the printed wiring board of the present invention, a first group of via holes for exposing a plurality of connection electrodes of the first bare chip is formed in the first insulating layer covering the first bare chip of the semiconductor element. I have. The connection electrodes are electrically connected to corresponding portions of the first conductive layer formed on the first insulating layer via the via holes. Therefore, when the first conductive layer is formed by a plating method or the like, the corresponding portion of the first conductive layer can be brought into contact with the plurality of connection electrodes of the first bare chip via the via hole. Therefore, the electrical connection between the connection electrode of the buried first bare chip and the first conductive layer can be performed without going through a bonding step requiring expensive dedicated equipment such as wire bonding or flip chip bonding. It is possible. This leads to simplification of the bonding process of the embedded semiconductor element to the bare chip.

Further, since the first bare chip of the semiconductor element is covered not by the sealing resin but by the first insulating layer constituting the printed wiring board, another first insulating chip is provided on the first insulating layer. A conductive layer can be arranged and other electronic circuit components can be mounted. That is, it is possible to arrange another conductive layer or mount another electronic circuit component so as to overlap the buried bare chip. this is,
This leads to an improvement in the mounting density of electronic circuit components. (3) In a preferred example of the printed wiring board of the present invention, a second bare chip of the semiconductor element having a plurality of connection electrodes is further provided on the same side of the printed wiring board as the first bare chip. The first insulating layer covers the second bare chip and has a second group of via holes exposing connection electrodes of the second bare chip.
And the connection electrode of the second bare chip is the second electrode.
The first conductive layer is electrically connected to a corresponding portion through the group of via holes. In this example, the advantage that a small multi-chip module can be easily obtained is further obtained.

In this example, it is preferable that the first and second bare chips are electrically connected to each other via the first conductive layer. There is further obtained an advantage that electrical connection between the first and second bare chips can be easily performed.

In another preferred embodiment of the printed wiring board of the present invention, a second bare chip of the semiconductor element having a plurality of connection electrodes is further provided on the printed wiring board on the side opposite to the first bare chip. The second bare chip is a second bare chip.
A second conductive layer is formed on the second insulating layer while being covered by the insulating layer. Then, the second insulating layer is a second insulating layer that exposes a connection electrode of the second bare chip.
A group of via holes, and the connection electrodes of the second bare chip are connected to the second bare chip via the second group of via holes.
It is electrically connected to a corresponding part of the conductive layer. In this example, the advantage that a small multi-chip module can be easily obtained is further obtained.

In this example, it is preferable that the first and second bare chips are electrically connected to each other via a through hole penetrating the printed wiring board. There is further obtained an advantage that electrical connection between the first and second bare chips can be easily performed.

(4) A multi-chip module according to the present invention includes a printed wiring board, and a first bare chip of a semiconductor device having a plurality of connection electrodes embedded in the printed wiring board. The first insulating layer of the printed wiring board covering one bare chip has a first group of via holes exposing the connecting electrode of the first bare chip, and the connecting electrode of the first bare chip is The printed wiring board formed on the first insulating layer is electrically connected to a corresponding portion of a first conductive layer via a first group of via holes.

(5) In the multi-chip module of the present invention, for the same reason as described for the printed wiring board of the present invention, the multi-chip module is embedded without passing through a bonding step such as wire bonding or flip chip bonding. It is possible to electrically connect the semiconductor element to the first bare chip, and it is also possible to arrange another conductive layer or mount other electronic circuit components so as to overlap the buried bare chip It is. Therefore, it is possible to simplify the bonding process of the embedded semiconductor element to the bare chip and to improve the mounting density of electronic circuit components.

(6) In a preferred example of the multichip module of the present invention, the multichip module further includes a packaged chip of a semiconductor element having a plurality of connection leads mounted outside the printed wiring board. The connection leads of the packaged chip are electrically connected to corresponding portions of the first conductive layer. In this example, the connection lead of the packaged chip can be provided at a position overlapping the first bare chip, and therefore, the advantage that the degree of freedom in the layout of the packaged chip is further increased is obtained.

In another preferred embodiment of the multichip module of the present invention, a second bare chip of the semiconductor element having a plurality of connection electrodes is further provided on the same side of the printed wiring board as the first bare chip. The first insulating layer covers the second bare chip and the second insulating chip.
It has a second group of via holes exposing the bare chip connection electrodes. The connection electrodes of the second bare chip are electrically connected to corresponding portions of the first conductive layer via the second group of via holes. In this example,
This has the further advantage that small multichip modules can be easily obtained.

In this example, it is preferable that the first and second bare chips are electrically connected to each other via the first conductive layer. There is further obtained an advantage that electrical connection between the first and second bare chips can be easily performed.

In still another preferred embodiment of the multichip module of the present invention, a second bare chip of the semiconductor element having a plurality of connection electrodes is further provided on the printed wiring board on the side opposite to the first bare chip. The second
The bare chip is covered with a second insulating layer of the printed wiring board, and a second conductive layer of the printed wiring board is formed on the second insulating layer. The second insulating layer has a second group of via holes exposing the connection electrodes of the second bare chip, and the connection electrodes of the second bare chip are connected via the second group of via holes. It is electrically connected to a corresponding portion of the second conductive layer. In this example, the advantage that a small multi-chip module can be easily obtained is further obtained.

In this example, it is preferable that the first and second bare chips are electrically connected to each other via a through hole penetrating the printed wiring board. There is further obtained an advantage that electrical connection between the first and second bare chips can be easily performed.

Preferably, the first and second bare chips are arranged so as to be back to back.

[0029]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 shows a multichip module according to a first embodiment of the present invention.

As is apparent from FIG. 1, the multi-chip module of the first embodiment has a printed wiring board 10 in which a bare chip 20 of a semiconductor element is embedded.
And a packaged chip 30 of a semiconductor element mounted on one side of the printed wiring board 10. The bare chip 20 has connection electrodes 21 and 22 arranged on its surface. Unlike the bare chip 20, the packaged chip 30 has a package of plastic, ceramic, or the like, and a plurality of connection leads 31 are formed on both sides of the package.

The printed wiring board 10 includes a glass or ceramic plate core 11, and the surface thereof is covered with an insulating layer 12. A conductive layer 13 having a predetermined pattern and a bare chip 20 of a semiconductor element are arranged on the insulating layer 12. The connection electrodes 21 and 22 formed on one surface of the bare chip 20 are located on the opposite side (that is, outside) of the core 11.

An insulating layer 14 covering the conductive layer 13 is further formed on the insulating layer 12, and the bare chip 20 is exposed from the insulating layer 14. A conductive layer 15 having a predetermined pattern is formed on the insulating layer 14, and an insulating layer 16 covering the conductive layer 15 is further formed on the insulating layer 14.
Are formed. The insulating layer 16 also covers the bare chip 20. Thus, the bare chip 20 is embedded inside the printed wiring board 10. The conductive layers 13 and 15
Each forms a predetermined inner layer circuit.

The insulating layer 16 covering the bare chip 20 has via holes 19a and 19b at locations corresponding to the connecting electrodes 21 and 22 of the bare chip 20, respectively. Electrode 2
Each of 1 is exposed from corresponding via hole 19a, and each of electrodes 22 is exposed from corresponding via hole 19b. The insulating layer 16 covering the bare chip 20 further has a via hole 19c, and a part of the conductive layer 15 below the insulating layer 16 is exposed from the via hole 19c.

An outermost conductive layer 17 having a predetermined pattern is formed on the insulating layer 16. The conductive layer 17
A predetermined outer layer circuit is formed, but via holes 19a and 19b are formed in electrodes 21 and 22 of bare chip 20 buried below.
Is in contact through. Thus, the conductive layer 17 is electrically connected to the electrodes 21 and 22 at the corresponding locations. The conductive layer 17 is also in contact with the underlying conductive layer 15 via the via hole 19c, so that the conductive layer 17 is also electrically connected to the conductive layer 15.

An outermost insulating layer 18 covering the conductive layer 15 is further formed on the insulating layer 16. Conductive layer 15
Are exposed from the insulating layer 18 except for a portion necessary for connection of the packaged chip 30 of the semiconductor element and other electronic components (not shown). Chip 30 with package
The connection lead 31 is connected to the conductive layer 1 by soldering or the like.
7 is electrically connected to a predetermined circuit of the printed wiring board 10 by being fixed to the exposed portion.

Next, a method of manufacturing the multichip module according to the first embodiment having the above configuration will be described with reference to FIG.

First, as shown in FIG.
An insulating layer 12 on the surface of the conductive layer 13 having a predetermined pattern,
An insulating layer 14 and a conductive layer 15 having a predetermined pattern are sequentially formed. Thereafter, a hole is formed in a predetermined portion of the insulating layer 14, and the bare chip 20 of the semiconductor element is placed on the lower insulating layer 12 through the hole. At this time, the electrode 21 of the bare chip 20 is directed upward, that is, the side opposite to the core 11. The state at this time is shown in FIG.

Subsequently, as shown in FIG. 2B, an insulating layer 16 is formed so as to cover the entire printed wiring board 10 including the conductive layer 15 and the bare chip 20. Then, via holes 19a, 19b,
19c is formed, and the electrodes 21 and 22 of the bare chip 20 are exposed from the via holes 19a and 19b, respectively, and a predetermined portion of the conductive layer 15 is exposed from the via hole 19c. The insulating layer 16 may be formed by applying an appropriate insulating material, or may be formed by attaching a film of the insulating material. The state at this time is shown in FIG.

Next, the via holes 19a, 19b, 19c
A conductive layer 17 having a predetermined pattern is selectively formed on the insulating layer 16 on which is formed by plating. Then
The conductive layer 17 contacts the electrodes 21 and 22 of the bare chip 20 via the via holes 19a and 19b.
The conductive layer 17 is electrically connected to each of the corresponding electrodes 21 and 22 at a predetermined location. At the same time, the conductive layer 17
Is in contact with a predetermined portion of conductive layer 15 below via hole 19c, and as a result, conductive layer 17 is electrically connected to a predetermined portion of conductive layer 15.

Next, the outermost insulating layer 1 is formed on the insulating layer 16.
8 is formed to cover the conductive layer 17. The insulating layer 18 has a predetermined pattern so as to expose a predetermined portion of the conductive layer 17 used for mounting the packaged chip 30 of the semiconductor element. The state at this time is shown in FIG.

Finally, as shown in FIG. 1, the connection leads 31 of the packaged chip 30 are fixed to predetermined exposed portions of the conductive layer 17 by soldering or the like, so that the chip 30 is placed on the printed wiring board 10. Mount. The chip 30 is located at a position overlapping the bare chip 20 embedded inside the printed wiring board 10. Thus, the multichip module shown in FIG. 1 is completed.

Although not shown, if necessary,
It goes without saying that another electronic circuit component such as a capacitor or another chip with a package may be fixed on the conductive layer 17.

As described above, in the multichip module according to the first embodiment of the present invention, the plurality of connection electrodes 21 and 22 of the bare chip 20 are exposed on the insulating layer 16 covering the bare chip 20 of the semiconductor element. A plurality of via holes 19a and 19b are formed. The connection electrodes 21 and 22 are electrically connected to corresponding portions of the conductive layer 17 formed on the insulating layer 16 via the via holes 19a and 19b. Therefore, when the conductive layer 17 is formed by plating or the like, the corresponding portion of the conductive layer 17 can be brought into contact with the plurality of connection electrodes 21 and 22 of the bare chip 20 via the via holes 19a and 19b, respectively. . Therefore, the embedded bare chip 20 can be embedded without going through a bonding step requiring expensive dedicated equipment such as wire bonding or flip chip bonding.
It is possible to make an electrical connection between the connection electrodes 21 and 22 and the conductive layer 17. That is, the bonding process of the embedded semiconductor element to the bare chip 20 can be simplified.

The bare chip 20 is covered by
Since it is not the sealing resin but the insulating layer 16 constituting the printed wiring board 10, another conductive layer is arranged on the insulating layer 16 so as to overlap the bare chip 20, and other electronic circuit components are mounted thereon. Or you can. Further, by mounting the packaged chip 30 thereon so as to overlap, it is also possible to three-dimensionally mount semiconductor elements and electronic circuit components on the printed wiring board 10,
The mounting density can be further improved.

Although the printed wiring board 10 has the core 11 in the multichip module according to the first embodiment, it is needless to say that the printed wiring board 10 may not have the core.

(Second Embodiment) FIG. 3 shows a multichip module according to a second embodiment of the present invention. This multi-chip module includes a printed wiring board 40 having no core.
Inside two semiconductor element bare chips 20a and 20b
Are buried adjacent to each other.

As shown in FIG. 3, the printed wiring board 40 also includes an insulating layer 41, a conductive layer 42 having a predetermined pattern, an insulating layer 43, a conductive layer 44 having a predetermined pattern, and an insulating layer 4
5, a conductive layer 46 having a predetermined pattern, an insulating layer 47, a conductive layer 48 having a predetermined pattern, and an insulating layer 49 are laminated in this order. The bare chips 20a and 20b of the semiconductor device are mounted on the insulating layer 43, and the insulating layers 45 and 47
Its side and top are covered by.

Insulating layer 4 covering bare chips 20a and 20b
7 has a plurality of via holes 50a, 50b at locations corresponding to the plurality of electrodes 21a, 22a of the bare chip 20a, and has a plurality of via holes 50c, 50d at locations corresponding to the plurality of electrodes 21b, 22b of the bare chip 20b. ing. Each of the electrodes 21a of the bare chip 20a is exposed from the corresponding via hole 50a, and each of the electrodes 22a is
It is exposed from the corresponding via hole 50b. Each of the electrodes 21b of the bare chip 20b has a corresponding via hole 50.
c, and each of the electrodes 22b is exposed from the corresponding via hole 50d.

Insulating layer 4 covering bare chips 20a and 20b
An outermost conductive layer 48 having a predetermined pattern is formed on 7. This conductive layer 48 has a via hole 50a.
And the electrodes 21a and 22 of the bare chip 20a via 50b
a, and as a result, the conductive layer 48 is electrically connected to the electrodes 21a and 22a at predetermined positions. Further, the conductive layer 48 is formed in the via hole 5.
The electrodes 21b of the bare chip 20b via 0c and 50d,
22b, so that the conductive layer 48
Is electrically connected to the electrodes 21b and 22b at predetermined locations.

The printed wiring board 40 includes the bare chip 20a.
And 20b, there are a plurality of through holes 51a and 51b penetrating the printed wiring board 40. Conductive layers 52a and 52b are formed on the inner walls of through holes 51a and 51b, respectively.
Thereby, the outermost conductive layer 48 is electrically connected to the outermost conductive layer 42 on the opposite side. As a result, the electrode 21a of the bare chip 20a and the electrode 2 of the bare chip 20b
2b are electrically connected to each other. The electrode 21b of the bare chip 20a and the electrode 22 of the bare chip 20b
a is electrically connected by the conductive layer 48.

As described above, also in the multichip module according to the second embodiment of the present invention, the connection electrodes 21a and 22a of the bare chip 20a are exposed on the insulating layer 47 covering the bare chips 20a and 20b of the semiconductor element. A plurality of via holes 50a, 50b and a plurality of via holes 50c, 50d for exposing the connection electrodes 21b, 22b of the bare chip 20b are formed.
1a, 22a, 21b, and 22b are the via holes 50
It is electrically connected to a conductive layer 48 formed on the insulating layer 47 via a, 50b, 50c, and 50d. For this reason, as in the first embodiment, the connection electrodes 21a and 22a for the buried bare chips 20a and 20b are bypassed through a bonding step requiring expensive dedicated equipment such as wire bonding or flip chip bonding. ,
It is possible to make electrical connection between the conductive layers 48 and 21b and 22b. That is, the bonding process of the buried semiconductor element to the bare chips 20a and 20b can be simplified.

Since the bare chips 20a and 20b are covered with the insulating layer 16 constituting the printed wiring board 10, another conductive layer may be arranged on the insulating layer 16 so as to overlap the bare chip 20, or other conductive layers may be provided. Electronic circuit components can be mounted. Further, by mounting the packaged chip 30 thereon so as to overlap, it is also possible to three-dimensionally mount semiconductor elements and electronic circuit components on the printed wiring board 10, thereby further improving the mounting density. It becomes possible.

(Third Embodiment) FIG. 4 shows a multichip module according to a third embodiment of the present invention. This multi-chip module includes a printed wiring board 60 having no core.
Inside two semiconductor element bare chips 20a and 20b
Buried back to back.

As shown in FIG. 4, the printed wiring board 60
Are an insulating layer 61, a conductive layer 62 having a predetermined pattern, an insulating layer 63, a conductive layer 64 having a predetermined pattern, an insulating layer 65,
A conductive layer 66 having a predetermined pattern, an insulating layer 67, a conductive layer 68 having a predetermined pattern, an insulating layer 69, a conductive layer 70 having a predetermined pattern, and an insulating layer 71 are laminated in this order. The bare chips 20a and 20b of the semiconductor element are arranged back to back with the insulating layer 67 interposed therebetween.
3, 65, 67 and 69 cover the periphery.

The insulating layer 63 covering the bare chip 20b has a plurality of via holes 72c and 72d at locations corresponding to the plurality of electrodes 21b and 22b of the bare chip 20b.
Electrodes 21b and 22b are connected to via holes 72c and 7c, respectively.
It is exposed from 2d. The conductive layer 62 formed on the lower surface of the insulating layer 63 is in contact with the electrodes 21b and 22b of the bare chip 20b via the via holes 72c and 72d, respectively. Is electrically connected to

Similarly, insulating layer 6 covering bare chip 20a
9 has via holes 72a and 72b at locations corresponding to the plurality of electrodes 21a and 22a of the bare chip 20a. Electrodes 21a and 22a are connected to via holes 72a, respectively.
And 72b. The conductive layer 70 formed on the upper surface of the insulating layer 69 is in contact with the electrodes 21a and 22a of the bare chip 20a via the via holes 72a and 72b, and as a result, the conductive layer 70 has the electrodes 21a and 22a at predetermined positions. Is electrically connected to

The printed wiring board 60 has through holes 73a and 73b penetrating therethrough, and bare chips 20a and 20b.
Around. Conductive layers 74a and 74b are formed on the inner walls of the through holes 51a and 51b, respectively. The two outermost conductive layers 62 and 70 are electrically connected to each other by the conductive layers 74a and 74b.
Thus, the electrode 21a of the bare chip 20a and the electrode 21b of the bare chip 20b are electrically connected to each other.

As described above, also in the multi-chip module according to the third embodiment of the present invention, the bare chip 20 is formed on the insulating layer 69 covering the bare chip 20a of the semiconductor element.
A plurality of via holes 72a and 72b exposing the connection electrodes 21a and 22a are formed on the insulating layer 63 covering the bare chip 20b.
via holes 72c and 72 exposing b and 22b
d is formed. The electrodes 21a and 22a of the bare chip 20a are electrically connected to the conductive layer 70 via the via holes 72a and 72b, and the electrodes 21b and 22b of the bare chip 20b are electrically connected to the conductive layer 62 via the via holes 72c and 72d. Have been. As a result, the same effects as in the above-described second embodiment can be obtained.

Further, since the bare chips 20a and 20b of the semiconductor element are buried in the printed wiring board 60 with their backs facing each other, there is an advantage that further miniaturization can be achieved as compared with the case of the second embodiment.

The internal structure of the printed wiring boards 10, 40, 60 according to the first to third embodiments is merely an example, and it is sufficient that the bare chip of at least one semiconductor element is embedded. For example, their layer structures can be arbitrarily changed. In the second and third embodiments, it goes without saying that a chip with a package of a semiconductor element and other electronic circuit components may be mounted as in the first embodiment.

[0062]

As described above, according to the printed wiring board and the multi-chip module of the present invention, the printed wiring board and the multi-chip module are buried without passing through a bonding step requiring special equipment such as wire bonding and flip chip bonding. Electrical connection of the semiconductor element to the bare chip can be made. Therefore, the bonding process of the embedded semiconductor element to the bare chip can be simplified.

Further, a conductive layer may be disposed on the insulating layer covering the bare chip of the buried semiconductor element so as to overlap the bare chip, or another electronic circuit component may be mounted. Therefore, the mounting density of electronic circuit components can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part showing a configuration of a multichip module according to a first embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view showing the method for manufacturing the multichip module of the first embodiment of the present invention.

FIG. 3 is a sectional view of a main part showing a configuration of a multichip module according to a second embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view showing a configuration of a multichip module according to a third embodiment of the present invention.

[Explanation of symbols]

10, 40, 60 printed wiring board 11 core of printed wiring board 12, 14, 16, 18, 41, 43, 45, 47, 4,
9, 61, 63, 65, 67, 69, 71 Insulating layers 13, 15, 17, 42, 44, 46, 48, 52a,
52b, 62, 64, 66, 68, 70, 74a, 74
b conductive layer 19a, 19b, 19c, 50a, 50b, 50c, 5
0d, 72a, 72b, 72c, 72d Via hole 20, 20a, 20b Bare chip of semiconductor element 21, 21a, 21b, 22, 22a, 22b Electrode for connection of bare chip 30 Chip with package of semiconductor element 31 Lead for connection of chip with package 51a, 51b, 73a, 73b Through hole

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 1/18 3/46

Claims (10)

[Claims] A first bare chip of a semiconductor device having a plurality of connection electrodes, a first insulating layer covering the first bare chip, and a first conductive layer formed on the first insulating layer; The first insulating layer has a first group of via holes exposing the connection electrodes of the first bare chip, and
The printed wiring board, wherein the connection electrode is electrically connected to a corresponding portion of the first conductive layer via the first group of via holes. 2. A second bare chip of a semiconductor element having a plurality of connection electrodes is provided on the same side of the printed wiring board as the first bare chip, and the first insulating layer covers the second bare chip. And a second group of via holes for exposing the connection electrode of the second bare chip, and the connection electrode of the second bare chip is
The printed wiring board according to claim 1, wherein the printed wiring board is electrically connected to a corresponding portion of the first conductive layer via a group of via holes. 3. A second bare chip of a semiconductor element having a plurality of connection electrodes is provided on a side of the printed wiring board opposite to the first bare chip, and the second bare chip is covered by a second insulating layer. In addition, a second conductive layer is formed on the second insulating layer, and the second insulating layer has a second group of via holes exposing the connection electrodes of the second bare chip. hand,
The printed wiring board according to claim 1, wherein the connection electrodes of the second bare chip are electrically connected to corresponding portions of the second conductive layer through the second group of via holes. 4. A printed wiring board, comprising: a first bare chip of a semiconductor element having a plurality of connection electrodes embedded in the printed wiring board; and a first bare chip of the printed wiring board covering the first bare chip. The first insulating layer has a first group of via holes exposing the connection electrodes of the first bare chip, and the connection electrodes of the first bare chip include the first group of via holes.
A multi-chip circuit, wherein the plurality of via holes are electrically connected to corresponding portions of a first conductive layer of the printed wiring board formed on the first insulating layer.
module. 5. The semiconductor device according to claim 1, further comprising a packaged chip of a semiconductor element having a plurality of connection leads mounted outside the printed wiring board, wherein the connection lead of the packaged chip is the first lead.
The multi-chip module according to claim 4, wherein the multi-chip module is electrically connected to a corresponding portion of the conductive layer. 6. A second bare chip of a semiconductor element having a plurality of connection electrodes, further provided on the same side of the printed wiring board as the first bare chip, wherein the first insulating layer is provided on the second bare chip. And a second group of via holes for exposing the connection electrodes of the second bare chip, and wherein the connection electrodes of the second bare chip are connected to the first group of via electrodes via the second group of via holes. The multichip module according to claim 4, wherein the multichip module is electrically connected to a corresponding portion of the conductive layer. 7. The multichip module according to claim 6, wherein said first and second bare chips are electrically connected to each other via said first conductive layer. 8. A second bare chip of the semiconductor element having a plurality of connection electrodes is further provided on a side of the printed wiring board opposite to the first bare chip, and the second bare chip is provided on the printed wiring board. A second conductive layer of the printed wiring board is formed on the second insulating layer while being covered by the second insulating layer, and the second insulating layer exposes a connection electrode of the second bare chip. Having a second group of via holes to be
The multichip module according to claim 4, wherein the connection electrodes of the bare chip are electrically connected to corresponding portions of the second conductive layer via the second group of via holes. 9. The multichip module according to claim 8, wherein said first and second bare chips are electrically connected to each other via a through hole penetrating said printed wiring board. 10. The first and second bare chips,
9. The arrangement of claim 8, wherein the arrangement is such that they are back to back.
Or a multichip module according to 9.