JP2001184211A - 処理システムにおいてスタックのポップおよびプッシュ動作を行なうための装置および方法 - Google Patents

処理システムにおいてスタックのポップおよびプッシュ動作を行なうための装置および方法

Info

Publication number
JP2001184211A
JP2001184211A JP2000338990A JP2000338990A JP2001184211A JP 2001184211 A JP2001184211 A JP 2001184211A JP 2000338990 A JP2000338990 A JP 2000338990A JP 2000338990 A JP2000338990 A JP 2000338990A JP 2001184211 A JP2001184211 A JP 2001184211A
Authority
JP
Japan
Prior art keywords
stack pointer
stack
pointer
updated
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000338990A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001184211A5 (enExample
Inventor
Farbliss Aidan
アイダン・ファブリス
Yoramm Salant
サラント・ヨーラム
Marc Erlneckaff
エルネケイブ・マーク
Leonido Tsukaaman
ツカーマン・レオニド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JP2001184211A publication Critical patent/JP2001184211A/ja
Publication of JP2001184211A5 publication Critical patent/JP2001184211A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30163—Decoding the operand specifier, e.g. specifier format with implied specifier, e.g. top of stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
JP2000338990A 1999-11-09 2000-11-07 処理システムにおいてスタックのポップおよびプッシュ動作を行なうための装置および方法 Pending JP2001184211A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/436891 1999-11-09
US09/436,891 US6654871B1 (en) 1999-11-09 1999-11-09 Device and a method for performing stack operations in a processing system

Publications (2)

Publication Number Publication Date
JP2001184211A true JP2001184211A (ja) 2001-07-06
JP2001184211A5 JP2001184211A5 (enExample) 2007-12-27

Family

ID=23734241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000338990A Pending JP2001184211A (ja) 1999-11-09 2000-11-07 処理システムにおいてスタックのポップおよびプッシュ動作を行なうための装置および方法

Country Status (5)

Country Link
US (1) US6654871B1 (enExample)
JP (1) JP2001184211A (enExample)
KR (1) KR100875377B1 (enExample)
CN (1) CN1230739C (enExample)
TW (1) TW535089B (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
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DE10121745A1 (de) * 2001-05-04 2002-11-14 Systemonic Ag Verfahren und Anordnung zu einem Stack mit einem, in Datengruppen mit mehreren Elementen aufgeteilten Speicher
IL152006A0 (en) * 2002-09-30 2003-07-31 Rabintex Ind Ltd Shell for ballistic helmet
CN100353335C (zh) * 2003-03-28 2007-12-05 联发科技股份有限公司 增加处理器中存储器的方法
US7111149B2 (en) * 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
WO2005096136A1 (en) * 2004-03-31 2005-10-13 Intel Corporation Stack caching using code sharing
US7290153B2 (en) 2004-11-08 2007-10-30 Via Technologies, Inc. System, method, and apparatus for reducing power consumption in a microprocessor
JP2006309508A (ja) * 2005-04-28 2006-11-09 Oki Electric Ind Co Ltd スタック制御装置およびその方法
US7769983B2 (en) * 2005-05-18 2010-08-03 Qualcomm Incorporated Caching instructions for a multiple-state processor
US7454572B2 (en) * 2005-11-08 2008-11-18 Mediatek Inc. Stack caching systems and methods with an active swapping mechanism
US7647482B2 (en) * 2006-03-31 2010-01-12 Intel Corporation Methods and apparatus for dynamic register scratching
US7711927B2 (en) * 2007-03-14 2010-05-04 Qualcomm Incorporated System, method and software to preload instructions from an instruction set other than one currently executing
EP2150889A1 (en) * 2007-04-10 2010-02-10 Cambridge Consultants Limited Data processing apparatus
US8055886B2 (en) 2007-07-12 2011-11-08 Texas Instruments Incorporated Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction
JP5044387B2 (ja) * 2007-12-26 2012-10-10 ルネサスエレクトロニクス株式会社 情報処理装置及びそのスタックポインタ更新方法
US9645949B2 (en) 2008-07-10 2017-05-09 Cambridge Consultants Ltd. Data processing apparatus using privileged and non-privileged modes with multiple stacks
US9588881B2 (en) * 2011-05-16 2017-03-07 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses
US9910823B2 (en) 2011-05-16 2018-03-06 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) having an instruction set optimized to minimize memory fetch
US8934279B2 (en) * 2011-05-16 2015-01-13 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space
US9697002B2 (en) * 2011-10-03 2017-07-04 International Business Machines Corporation Computer instructions for activating and deactivating operands
CN112486897B (zh) * 2019-09-11 2024-07-09 中国科学院微电子研究所 一种高速缓存系统及单周期多数据的入栈、出栈操作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58221446A (ja) * 1982-06-18 1983-12-23 Hitachi Ltd スタツクアドレス選択方式
JPS62128337A (ja) * 1985-11-30 1987-06-10 Nec Corp スタツク制御方式

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142635A (en) 1989-04-07 1992-08-25 Intel Corporation Method and circuitry for performing multiple stack operations in succession in a pipelined digital computer
JPH0752576B2 (ja) 1990-07-19 1995-06-05 株式会社東芝 スタックメモリ
US5381360A (en) * 1993-09-27 1995-01-10 Hitachi America, Ltd. Modulo arithmetic addressing circuit
US5706491A (en) 1994-10-18 1998-01-06 Cyrix Corporation Branch processing unit with a return stack including repair using pointers from different pipe stages
WO1996037828A1 (en) * 1995-05-26 1996-11-28 National Semiconductor Corporation Apparatus and method for executing pop instructions
US5687336A (en) 1996-01-11 1997-11-11 Exponential Technology, Inc. Stack push/pop tracking and pairing in a pipelined processor
KR100246465B1 (ko) * 1996-11-06 2000-03-15 김영환 마이크로프로세서 스택 명령어의 수행사이클을 줄이기 위한 장치 및 그 방법
US5958039A (en) * 1997-10-28 1999-09-28 Microchip Technology Incorporated Master-slave latches and post increment/decrement operations

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58221446A (ja) * 1982-06-18 1983-12-23 Hitachi Ltd スタツクアドレス選択方式
JPS62128337A (ja) * 1985-11-30 1987-06-10 Nec Corp スタツク制御方式

Also Published As

Publication number Publication date
KR20010051522A (ko) 2001-06-25
KR100875377B1 (ko) 2008-12-23
TW535089B (en) 2003-06-01
CN1295279A (zh) 2001-05-16
CN1230739C (zh) 2005-12-07
US6654871B1 (en) 2003-11-25

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