JP2001177110A - Lateral junction field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lateral JFET which can be easily manufactured as a high power semiconductor switching device that is high in breakdown voltage and capable of operating at a high speed. SOLUTION: A lateral junction field-effect transistor is equipped with a P-type SiC film 2 formed on an SiC substrate 1, a low concentration N-type SiC film 7 formed thereon, an N-type SiC film 3 formed thereon, a channel region 11 formed by thinning the N-type SiC film 3, a source region 22 and a drain region 23 formed on the sides of the channel region 11, and a gate electrode 14 where the low concentration N-type SiC film 7 is lower in N-type impurity concentration than the channel region 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral junction field effect transistor, and more particularly to a lateral junction field effect transistor using SiC as a semiconductor.

[0002]

2. Description of the Related Art A junction type field effect transistor (JFET: Jun)
ction Field Effect Transistor) is to apply a reverse bias voltage from a gate electrode to a pn junction provided on the side of a channel region through which carriers pass, thereby expanding a depletion layer from the pn junction to the channel region, And conducts operations such as switching. Among them, the “lateral” junction field effect transistor refers to a transistor in which carriers move parallel to the element surface in a channel region. Channel carriers are electrons (n
Type) or hole (p-type), but SiC, which is the object of the present invention, has a higher electron mobility than holes.
Usually, the channel region is an n-type impurity region. Therefore,
In the following description, for the sake of convenience, the carrier of the channel will be electrons, and the channel region will be described as an n-type impurity region. However, it goes without saying that the channel region may be a p-type impurity region.

In recent years, JF using silicon carbide (SiC)
ET is attracting attention. SiC has carrier mobility of S
Since it is as large as i, the saturation drift velocity of electrons is as large as GaAs, and the withstand voltage is large, studies on high-speed switching elements and high power elements are being studied. S
The crystal structure of iC includes a hexagonal close-packed structure and a cubic close-packed structure. In the hexagonal close-packed structure, there are many structures having different repetition periods of the layers. Type) is known. Representative polytypes include 3C, 4H, 6H, and the like. C is cubic,
H means hexagonal, and the number before it indicates the repetition period. The cubic form is only 3C, which is
C and others are collectively read as α-SiC. In the following description, only 6H or 4H of α-SiC is used.

FIG. 6 is a sectional view showing the structure of a JFET using SiC (PA Ivanov et al: 4H-SiC field-effect t).
ransistor hetero-epitaxially grown on 6H-SiC subst
rateby sublimation, p757 Silicon Carbide and Relat
ed Materials 1995 Conf., Kyoto Japan). In FIG. 6, a buffer layer 109 is formed by heteroepitaxially growing a 4H-SiC film 109 containing Sn on a 6H-SiC substrate 101 by a vacuum evaporation method. Buffer layer 10
9, an SiC film 1 containing Al which is a p + -type impurity
The n-type SiC film 103 having a source region 117 and a drain region 118 is formed on both sides thereof. The source electrode 112 and the drain electrode 113 are provided above the left and right of the channel region, and the gate electrode 114 is formed below the source and drain electrodes with a groove 115 therebetween. As the electrodes 114, a Ni film of the base film 120 and an Al film of the upper film 121 are formed. By using this lateral JFET, a JFET having a high electron drift mobility and an extremely high electron mobility can be formed.

[0005]

However, this J
The FET has the following problems. (A) It is insufficient in that it has both high breakdown voltage and low on-resistance.

The breakdown voltage of a JFET is determined by the breakdown voltage of a pn junction formed by an n-type impurity region of a channel and a p-type impurity region in contact with the region. Therefore, JFET
In order to improve the breakdown voltage performance, the breakdown voltage of the pn junction may be improved. In order to improve the breakdown voltage of the pn junction, the concentration of the n-type impurity, which is a channel impurity, may be reduced. As a result, the channel current decreases, and the on-resistance (the resistance in a state where carriers flow through the channel region) increases. ) Increases. As a result, power is consumed and the element temperature rises. Since the lateral JFET has a negative temperature coefficient in the range where the drain current is large, negative feedback is applied to the temperature rise, but no negative feedback is applied in the range where the drain current is small. Further, regardless of the magnitude of the drain current, power consumption in the element is not preferable. Another reason why the on-resistance of the JFET cannot be reduced is the contact resistance at the electrodes. In the configuration shown in FIG. 6, when each electrode is formed of Ni, the impurity concentration is too low, so that Schottky contact tends to remain, and ohmic contact cannot be obtained. (B) The switching speed is insufficient.

[0007] The switching speed is determined by the charge / discharge time of the depletion layer of the pn junction. Assuming that the depletion layer capacitance is C and the gate resistance is Rg, the charge / discharge time is determined by CRg. Therefore, if the gate resistance Rg can be reduced, the switching time can be shortened, but the conventional J shown in FIG.
In the FET, a groove is formed in the second conductivity type region, and the gate resistance cannot be sufficiently reduced. Note that the gate resistance Rg can be changed from the gate electrode 114 to the channel 111 if importance is placed on grasping intuitively while sacrificing some accuracy.
The resistance of the path leading to the pn junction interface at the center of the pn junction. (C) The manufacturing process is complicated and requires high precision and strict control.

When the JFET shown in FIG. 6 is manufactured, it is manufactured by the following method. The buffer layer 109 is formed on the SiC substrate 101, and then the p + type SiC film 10
2 is formed. Next, as shown in FIG. 7, an n-type SiC film is formed, and a portion where a channel, a source, and a drain region are to be formed is patterned using RIE (Reactive Ion Etching). Next, as shown in FIG. 8, a Ni film is formed as the lower layer 120 of the electrode. On this Ni film,
As shown in FIG. 9, an Al film for forming the upper layer 121 of the electrode is formed. At this time, the Al film cannot be positioned just above the Ni film to form a film, which often causes misalignment. If Al adheres to the side wall or the like, it acts as a floating electrode and makes the device operation unstable. Thereafter, as shown in FIG. 10, a channel region 111 is formed by RIE by using the source electrode 112 and the drain electrode 113 as a mask and etching the space therebetween. At this time, the p + type SiC film 1
02 is also etched to form a groove 115 together with the channel region. At the time of this etching, Al or the like adhered due to the above-described positional shift is also desired. The electrode is N
The reason for forming the two-layer film of the i film and the Al film is to form an ohmic contact. Due to the groove 115, the resistance Rg of the path from the gate electrode to the pn junction interface at the center of the channel region increases, and when used for a switching element, the rise (fall) time becomes long. In addition, an extra man-hour is required for forming the groove, which causes an increase in cost. (D) The operation becomes unstable due to the surface charge, and the surface leakage current is large.

A malfunction occurs due to the surface charge and the surface leakage current, and the yield is reduced. Therefore, the present invention
It is an object of the present invention to provide a lateral JFET that is easy to manufacture as a high-power semiconductor switching element having high withstand voltage and high speed.

[0010]

According to a first aspect of the present invention, there is provided a lateral JFET having a SiC substrate and a second JFET formed on the substrate.
A conductive type SiC film; and a low-concentration first conductive type SiC film formed on the second conductive type SiC film. A first conductivity type SiC film formed on the low-concentration first conductivity type SiC film; a channel region having a reduced thickness in the first conductivity type SiC film; Type S
A film made of a first conductivity type SiC formed on an iC film, and formed in a source region and a drain region separately formed on both sides of a channel region and a second conductivity type SiC region. A gate electrode.
The low-concentration first-conductivity-type SiC film contains the first-conductivity-type impurity at a lower concentration than the impurity concentration of the channel region.

With this configuration, the breakdown voltage can be improved without affecting the current in the channel region. For this reason, even if a high current flows, power consumption is small and a high breakdown voltage can be achieved without increasing the temperature. As a result,
It can be used for a high voltage, high power switching element. The first conductivity type may be p-type or n-type,
The second conductivity type may be either n-type or p-type.

In the lateral JFET according to the second aspect, in the lateral JFET according to the first aspect, the second conductive type SiC film has a surface having no groove, and the gate electrode is a second conductive type SiC region which is a second conductive type SiC region. It is composed of two gate electrodes formed on the flat surface of the type SiC film.

With this configuration, since no groove or the like is provided between the source / drain and the gate, the gate resistance can be reduced, and as a result, the switching response speed can be increased. In addition, in the manufacturing process, there is no problem with slight displacement of the formation of the gate electrode, so that a decrease in yield can be prevented.

According to a third aspect of the invention, in the lateral JFET of the first aspect, the SiC substrate is a second conductivity type SiC substrate containing a second conductivity type impurity, and the gate electrode is a second conductivity type SiC region. The back gate structure is provided over the back surface of a certain second conductivity type SiC substrate.

With this configuration, the gate electrode is provided on the entire back surface of the second conductivity type SiC substrate, so that the gate resistance is reduced. As a result, the response speed of the switching is improved, and the switching element can be used as a high-speed switching element. Further, formation of the gate electrode is also facilitated.

In the lateral JFET according to the fourth aspect,
In any one of the lateral JFETs of No. 3, the channel region contains a first-conductivity-type impurity whose concentration is higher than that of the first-conductivity-type SiC film on both sides thereof.

With this configuration, the on-resistance can be reduced without significantly lowering the breakdown voltage of the lateral JFET. As a result, it can be used as a switching element for high voltage and high power.

In the lateral JFET according to claim 5, claims 1 to
In any one of the lateral JFETs of No. 4, the source region and the drain region contain the first conductivity type impurity at a higher concentration than the impurity concentration of the region on both sides of the channel region.

According to this configuration, the ON resistance can be reduced without lowering the breakdown voltage. The electrodes are Ni and A
Ohmic contact can be formed without using a two-layer structure using 1 or the like. For this reason, in the manufacturing process,
As a result, no groove or the like is formed, the gate resistance can be kept low, and the rise (fall) time of switching can be reduced.

In the lateral JFET according to the sixth aspect,
5, the second conductivity type SiFET
The impurity concentration of the C film is higher than 10 ¹⁹ cm ⁻³ .

According to this configuration, ohmic contact is established at the gate electrode and the gate resistance is reduced. For this reason, the rise time and the fall time at the time of switching can be shortened, and a high-speed response can be achieved.

In the lateral JFET according to the seventh aspect,
6, the source electrode formed on the source region, the drain electrode formed on the drain region, and the gate electrode formed on the region of the second conductivity type SiC have the respective electrodes: It is made of a metal that makes ohmic contact with SiC containing impurities that come into contact therewith.

With this configuration, the electrodes can be formed by simple steps, and it is not necessary to form the electrode plate in a two-layer structure. For this reason, in the manufacturing process, a groove or the like for increasing the gate resistance is not formed as a result, and the rise (fall) time of switching can be shortened. Note that a metal that makes ohmic contact with the second conductivity type and the first conductivity type SiC film containing impurities at a high concentration includes Ni and the like.

In the lateral JFET of claim 8, claims 1 to
7, the surface excluding the source electrode, the drain electrode, and the gate electrode is covered with an insulating film.

When the element surface is exposed, operation instability occurs due to surface leakage current and surface charge formation. By the coating with the insulating film, such troubles can be prevented and the switching operation can be performed stably.

According to the ninth aspect of the invention, there is provided a lateral JFET.
8, the SiC substrate is 6
An H-SiC substrate, a second conductivity type SiC film and a first conductive type SiC film;
Each of the conductive SiC films is 6H-SiC.

According to the above configuration, thin films having good crystallinity are stacked, and there is no case where the yield is reduced due to malfunction or the like due to poor crystallinity.

In the lateral JFET according to the tenth aspect, the first aspect has the following features.
In any one of the lateral JFETs Nos. 1 to 8,
Both the iC film and the first conductivity type SiC film are 4H-S
The second conductivity type SiC film made of iC and made of 4H-SiC is formed on a 6H-SiC substrate via a 4H-SiC buffer layer.

4H-S with good crystallinity due to buffer layer
Since an iC film can be obtained, and 4H-SiC has a higher electron mobility than that of 6H-SiC or the like,
It can be suitable for a high-speed switching element or the like.

In the lateral JFET according to the eleventh aspect, the first aspect has the following features.
In any of the lateral JFETs Nos. 1 to 8, the SiC substrate is a 4H-SiC substrate, and the second conductivity type SiC film and the first conductivity type SiC film are both 4H-SiC.

According to the above configuration, thin films having good crystallinity are stacked, and there is no case where the yield decreases due to malfunction or the like due to poor crystallinity. Moreover, 4H-SiC
Is suitable for a high-speed switching element or the like because the mobility of electrons is superior to that of 6H-SiC or the like.

In the lateral JFET according to the twelfth aspect, the first aspect has the following features.
In any one of the lateral JFETs Nos. 1 to 8,
Both the iC film and the first conductivity type SiC film are 6H-S
The second conductivity type SiC film made of iC and made of 6H-SiC is formed on a 4H-SiC substrate via a 6H-SiC buffer layer.

6H-S with good crystallinity due to buffer layer
An iC film can be obtained, and there is no case where the yield decreases due to malfunction or the like due to poor crystallinity. Further, SiC having an appropriate crystal can be provided depending on the application.

[0034]

Next, an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a cross-sectional view of a lateral JFET according to a first embodiment. In FIG. 1, 6
On a H-SiC substrate 1, a 6H-p + type SiC film 2 is formed. Hereinafter, the SiC film formed on these will be
Since all are 6H-SiC films, "6H-" is omitted. On the p + -type SiC film 2, a low-concentration layer 7 containing an n-type impurity at a lower concentration than the channel region is formed by forming an n-type SiC film 3 and a p-type
The + type SiC film 2 is interposed between the two so that there is no place in contact with them. The channel region 11 is formed on the low concentration layer 7 at the center. The source electrode 12 and the drain electrode 13 are formed in the source region and the drain region, which are the n + SiC films 4 located above both sides of the channel when viewed from the channel region. Also, p +
The end of the type SiC film 2 is not covered with the upper n-type Si film 3, and the source electrode 12 formed above the center on one relatively wide uncoated surface.
Two gate electrodes 14 are formed so as to sandwich the gate electrode and the drain electrode 13. That is, the conductive path between the source / drain region and the gate electrode has a wide cross section without any narrow part constricted by a groove or the like in the middle.
It is desirable that the impurity concentration of each region is, for example, as follows. Channel region 11: n-type impurity 2 × 10 ¹⁷ cm ⁻³ source / drain region (n + -type SiC film) 4: n-type impurity> 1 × 10 ¹⁹ cm ⁻³ Low concentration layer 7: n-type impurity <2 × 10 ¹⁷ cm ⁻³ p + -type SiC film 2: p-type impurity> 1 × 10 ¹⁹ cm ^{−3 In} addition, the channel region has a thickness a, a length l, and a width w in the direction perpendicular to the paper surface according to the size of the element. You can decide.
Except for the electrodes 12, 13, and 14, the surface is S
It is covered with a protective film 5 made of iO ₂ . The source electrode 12 and the source region 22, the drain electrode 13 and the drain region 23, and the gate electrode 14 and the p + -type SiC film 2 as the gate region all have an impurity concentration of 1 × 10
^Since the region with a high concentration of more than ¹⁹ cm ^-3 is connected to the metal film, an ohmic contact can be formed by using, for example, Ni as the metal film and performing heat treatment.

In FIG. 1, in the ON state, a forward bias voltage is applied to the gate electrode, and no depletion layer is formed in the channel region 11. For this reason, carriers flow along a path from the source region to the drain region via the channel region. In this route, there is nothing to increase the on-resistance, and no power is consumed. When a reverse bias voltage is applied to the gate electrode 14, a depletion layer extends from the pn junction below the channel region to the channel region, and eventually turns off when the channel portion is completely closed. In the case where no groove is formed in the p-type SiC film 2 as in the present invention, the gate resistance is small, so that the repetition of ON and OFF reduces the rise (fall) time.

By using the configuration of the lateral JFET of FIG. 1, it is possible to improve the breakdown voltage without increasing the on-resistance, shorten the switching response time, and provide a JFET with stable performance. This JFET has a simple and easy manufacturing process and rarely causes troubles such as a decrease in yield, so that it can be manufactured at a low cost after all.

(Embodiment 2) FIG. 2 is a sectional view of a lateral JFET according to Embodiment 5. FIG. 2 is characterized in that the gate electrode is formed over the back surface of the p-type SiC substrate. According to the configuration of FIG. 2, the gate resistance Rg can be reduced, and as a result, the rise (fall) time of switching can be shortened. Further, the manufacturing method is simplified and facilitated, and the yield is improved.

[0039]

(Example 1) A lateral JFET using the structure shown in FIG. 1 was manufactured. The configuration of each region except for the channel region 11 and the low concentration layer 7 is as described above. In the channel region 11, the channel length 1 is 10 μm,
The channel thickness was 300 nm (0.3 μm), and the channel width w perpendicular to the paper was 700 μm. The impurity concentration of the low concentration layer (n− impurity layer) was 1 × 10 ¹⁵ cm ⁻³ , and the film thickness was 0.1 μm. FIGS. 3 to 5 show a method of manufacturing a lateral JFET of the present invention corresponding to FIGS. 7 to 10 for explaining a method of manufacturing a conventional lateral JFET. First, the p-type SiC substrate 1
A p + -type SiC film 2 is formed, and then a low-concentration n-type Si
A C film 7 is formed, and an n-type SiC film 3 is formed thereon.
Further, after forming an n + -type SiC 4 film thereon, RIE is performed.
Is performed to pattern the region including the source and drain regions (FIG. 3). Next, etching is performed by RIE in the center of the portion including the source and drain regions to form a groove, thereby forming a structure in which the source region 22 and the drain region 23 are separated (FIG. 4). Then, a gate electrode is formed on the p + SiC film 2 and n +
Source region 22 and drain region 2 which are impurity regions
3 are provided with a source electrode 12 and a drain electrode 13, respectively (FIG. 5). Thereafter, an etching step for forming a groove in p + SiC film 2 is not performed. For comparison, a lateral JFET having the structure shown in FIG. 6 was also manufactured. In the lateral JFET of the comparative example, the impurity concentration of both the source region and the drain region was not particularly increased, and the concentration of the n-type SiC film 3 was 2 × 1.
0 ¹⁷ cm ^-3 was left. Table 1 shows the measurement results of the breakdown voltage and the on-resistance of these two lateral JFETs.

[0040]

[Table 1]

As shown in Table 1, the on-resistance was increased from 10 mΩ · cm ² to 8.7 mΩ · c while the breakdown voltage was as high as 250 V.
m ² .

(Embodiment 2) Using the configuration of the lateral JFET of the present invention of Embodiment 1 above, changing only the p-type impurity concentration of the p-type SiC film and applying a voltage as an index of the response speed of the switching element. The rise (fall) time at the time was measured. Note that a Ni film is used for the electrode, and an ohmic contact is formed between the p-type impurity region and the ohmic contact. Table 2 shows the measurement results.

[0043]

[Table 2]

As shown in Table 2, the p-type impurity concentration is inversely proportional to the rise time, and the rise (fall) time tends to be shortened as the p-type impurity concentration increases.

While the embodiments and examples of the present invention have been described above, the embodiments and examples of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these. The invention is not limited to the embodiments and examples. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

[0046]

According to the present invention, it is possible to provide a lateral JFET suitable for a high-power semiconductor switching element having high withstand voltage and high speed. Since this lateral JFET can be manufactured by a simple and stable manufacturing process, it can be manufactured with a high yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a lateral JFET according to a first embodiment.

FIG. 2 is a cross-sectional view of a lateral JFET according to a second embodiment.

FIG. 3 is a cross-sectional view of a stage in which an n + SiC film is formed and patterned by RIE in an intermediate fabrication stage of the lateral JFET of FIG. 1;

FIG. 4 is a cross-sectional view of a stage where a channel region is formed by RIE after the stage of FIG. 3;

FIG. 5 is a cross-sectional view of a stage where an electrode is formed by forming a Ni film after the stage of FIG. 4;

FIG. 6 is a configuration sectional view of a conventional lateral JFET.

FIG. 7 is a cross-sectional view of a stage in which an n-channel layer is formed in an intermediate fabrication stage of the lateral JFET of FIG. 6;

FIG. 8 shows the first layer N of the two-layer electrode after the step of FIG. 7;
It is sectional drawing in the stage which formed the i film.

FIG. 9 shows the second layer A of the two-layer electrode after the stage of FIG. 8;
FIG. 4 is a cross-sectional view at the stage when an l film is formed.

FIG. 10 is a cross-sectional view of a stage where a groove is provided between the gate region and the center after the stage of FIG. 9;

[Explanation of symbols]

1 p-type SiC substrate, 2 p-type SiC film, 3 n-type Si
C film, 4 n + type SiC film (source and drain regions),
5 insulating film, 7 low concentration layer (n-type SiC film), 11
Channel region, 12 source electrode, 13 drain electrode, 14 gate electrode, 22 source region, 23 drain region, 114 gate electrode, 120Ni layer, 121
Al layer, 1 channel length, a channel thickness, w
Channel width.

Claims (12)

[Claims] An SiC substrate, a second conductivity type SiC film formed on the substrate, a low concentration first conductivity type SiC film formed on the second conductivity type SiC film, A first conductivity type SiC film formed on the first conductivity type SiC film, a channel region formed by reducing the thickness of the first conductivity type SiC film, and the first conductivity type SiC film The first conductivity type S formed on the film
a film made of iC, comprising: a source region and a drain region separately formed on both sides of a channel region; and a gate electrode formed in a second conductivity type SiC region. A lateral junction field effect transistor, wherein the SiC film includes a first conductivity type impurity having a lower concentration than an impurity concentration of the channel region. 2. The second conductivity type SiC film has a groove-free surface, and the gate electrode is formed on a flat surface of the second conductivity type SiC film which is a region of the second conductivity type SiC. 2. The lateral junction field-effect transistor according to claim 1, comprising two gate electrodes. 3. The SiC substrate is a second conductivity type SiC substrate containing a second conductivity type impurity, and the gate electrode is a back surface of the second conductivity type SiC substrate which is a region of the second conductivity type SiC. 2. The lateral junction field-effect transistor according to claim 1, wherein the lateral junction field-effect transistor is constituted by a back gate structure provided over the entire surface. 4. The lateral junction according to claim 1, wherein said channel region includes a first conductivity type impurity whose concentration is higher than that of a portion of said first conductivity type SiC film on both sides thereof. Type field effect transistor. 5. The semiconductor device according to claim 1, wherein the source region and the drain region are:
5. The lateral junction field-effect transistor according to claim 1, wherein the lateral junction field-effect transistor includes a first conductivity type impurity whose concentration is higher than an impurity concentration of a region on both sides of the channel region. 6. The lateral junction field effect transistor according to claim 1, wherein the impurity concentration of the second conductivity type SiC film exceeds 10 ¹⁹ cm ⁻³ . 7. A source electrode formed on the source region, a drain electrode formed on the drain region, and a gate electrode formed on the region of the second conductivity type SiC, Containing impurities in contact with
7. The lateral junction field-effect transistor according to claim 1, wherein the lateral junction field-effect transistor is made of a metal that makes ohmic contact with iC. 8. The lateral junction field effect transistor according to claim 1, wherein a surface excluding the source electrode, the drain electrode, and the gate electrode is covered with an insulating film. 9. The SiC substrate is a 6H—SiC substrate, and the second conductive SiC film and the first conductive Si
9. The lateral junction field effect transistor according to claim 1, wherein each of the C films is 6H-SiC. 10. The SiC film of the second conductivity type and the SiC film of the first conductivity type are both 4H-SiC.
The second conductivity type SiC film made of H-SiC is 6H-Si.
9. The lateral junction field effect transistor according to claim 1, wherein the lateral junction field effect transistor is formed on a C substrate via a 4H-SiC buffer layer. 11. The SiC substrate is a 4H—SiC substrate, and the second conductive type SiC film and the first conductive type S
9. The iC film is made of 4H-SiC.
The lateral junction field-effect transistor according to any one of the above. 12. The second conductivity type SiC film and the first conductivity type SiC film are both 6H-SiC,
The second conductivity type SiC film made of H-SiC is 4H-Si.
9. The lateral junction field effect transistor according to claim 1, wherein the transistor is formed on a C substrate via a 6H-SiC buffer layer.