JP2009295651A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents characteristics, such as impurity concentration of a channel layer and impurity concentration, from varying, when forming a semiconductor layer of a conductive type which is opposite to that of the channel layer as a junction FET, and has a junction field effect transistor that can be manufactured easily. <P>SOLUTION: A pair of p<SP>+</SP>-type contact layers 4 is provided on the channel layer 3 at both the sides of a p-type channel region 3a, and an n<SP>+</SP>-type contact layer 4 is provided at a lower side of the channel layer 3. Then, a source-drain electrode 5 is provided to the pair of p<SP>+</SP>-type contact layers 4 in ohmic contact, and a gate electrode 6 is provided on the exposure surface of an n<SP>+</SP>-type contact layer 2, provided on the lower side of the channel layer 3 in ohmic contact, thus forming the junction FET. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a junction field effect transistor (hereinafter also simply referred to as FET). More specifically, the present invention relates to a semiconductor device having a junction type FET having a structure in which a conductive type layer different from the channel layer of the junction type FET can be formed without a complicated process such as selective epitaxial growth or selective diffusion.

A conventional FET has a structure in which a gate electrode is provided between a source electrode and a drain electrode, and the current between the source and the drain is controlled by the gate. In such an FET, in order to widen the operation range in the gate forward direction, a structure in which an electrode having a high Schottky barrier height is provided at the gate (MESFET), or a pn junction type using a semiconductor layer having a conductivity type different from that of the channel layer It is known to use the FET structure. When a normally-off type FET is formed of MESFETs, the gate voltage is applied from 0 V in the forward direction of the gate to operate. However, in the MESFET structure, the gate forward current flows due to the metal-semiconductor Schottky junction, and therefore the gate operating voltage must be equal to or lower than the voltage Vf at which a certain gate forward current is obtained. Here, Vf is a voltage corresponding to a barrier height (potential barrier) φ _B determined by the materials of the metal and the semiconductor. Thus, in order to widen the gate operating voltage range, an electrode material having a high Schottky barrier height is required for the gate. However, when the semiconductor material is p-type GaAs, there is no material having a high barrier height.

Therefore, when a high Vf is required, a pn junction type FET structure is used. In this junction type p-channel FET, for example, as shown in FIG. 7A, an n ⁺ -type GaAs layer 54 is selectively epitaxially grown on the channel region of a p-type channel layer 52 made of GaAs, A p ⁺ type contact layer 53 made of GaAs epitaxially grown on the p type channel layer 52 is provided, and ohmic contacts are made on the p ⁺ type contact layer 53 and the n ⁺ type GaAs layer 54 on both sides thereof. The source / drain electrode 55 and the gate electrode 56 are provided. Reference numeral 51 denotes a semi-insulating substrate made of, for example, GaAs.

FIG. 7B shows another example of such a junction FET, and without selectively growing the n ⁺ -type GaAs layer 54, an n-type impurity is formed on the surface of the p-type channel layer 52 in that portion. Is selectively diffused, except that the n ⁺ -type diffusion region 58 is formed, and the other configuration is the same as that shown in FIG. 7A. Although not described, the FET has the same characteristics as the FET shown in FIG.

As described above, the junction FET is effective for increasing the range of the gate operating voltage. However, in order to form the junction FET, a pn junction is formed between the gate electrode and the channel layer. For example, the n ⁺ type semiconductor layer 54 must be selectively epitaxially grown on the p type channel layer 52 or the n ⁺ type diffusion region 58 must be selectively diffused to form a high impurity concentration layer. However, particularly in the case of a compound semiconductor such as GaAs, the temperature of the epitaxial growth is about 600 ° C., and the temperature of the selective growth or selective diffusion is not lower than this growth temperature, and the semiconductor layer that has already been epitaxially grown. There is a problem that the impurity concentration and the thickness of the impurity layer fluctuate and the characteristics deteriorate, and it is necessary to perform selective growth and diffusion at a low temperature. Therefore, when a very advanced technology is required and mass production is taken into consideration, there is a problem that the manufacturing process becomes very complicated and expensive, and the yield is lowered due to lack of reproducibility and stability. .

  The present invention has been made to solve such a problem. When a semiconductor layer having a conductivity type opposite to that of the channel layer is formed, characteristics such as impurity concentration of the channel layer can be obtained by selective epitaxial growth or selective diffusion. It is an object of the present invention to provide a semiconductor device having a junction field effect transistor having a structure that can be easily manufactured without causing fluctuations.

  A semiconductor device according to the present invention includes a channel layer having at least a first conductivity type channel region, and a pair of first conductivity type contacts provided on both sides of the channel region or on the channel layer on both sides of the channel region. A layer, a second conductivity type contact layer provided below the channel layer, a source electrode and a drain electrode in ohmic contact with the pair of first conductivity type contact layers, and an ohmic contact with the second conductivity type contact layer And a junction field effect transistor having a gate electrode.

Since the undoped layer is interposed between the second conductivity type contact layer and the first conductivity type channel layer, the reverse breakdown voltage of the pn junction and the gate-source capacitance C _GS can be easily controlled. preferable.

  Further, when each semiconductor layer constituting the junction field effect transistor is made of a compound semiconductor, the MESFET is particularly effective because it is difficult to increase the operating voltage range of the gate.

  According to the present invention, a normally-off type FET is realized by a junction FET, and therefore can be manufactured without being restricted by a semiconductor material or electrode metal. In addition, since the second conductivity type contact layer different from the conductivity type of the first conductivity type channel layer of the junction FET is formed under the first conductivity type channel layer, the first conductivity type channel layer is formed. In addition, it is not necessary to form the second conductivity type contact layer after forming the first conductivity type contact layer, the characteristics of the first conductivity type channel layer and the like are not changed, and the manufacturing process is very simple. become. For example, a semiconductor stacked portion including a first conductive type channel layer and a first conductive type contact layer is formed on the second conductive type contact layer, and a part of the semiconductor stacked portion is removed by etching to form the second conductive type. By exposing the type contact layer and forming the gate electrode on the exposed portion, a pn junction can be formed between the gate electrode and the first conductivity type channel layer, and the first contact type channel layer is formed on the first conductivity type channel layer. A junction FET can be formed very easily without selective epitaxial growth or selective impurity diffusion.

  Further, even if a stacked structure by such epitaxial growth is not used, for example, the second conductivity type contact layer is epitaxially grown, and a part of the first conductivity type contact layer (region) and the first conductivity layer therebetween are selectively diffused. Similarly, by forming a conductivity type channel layer (region) and forming a gate electrode on the exposed portion of the second conductivity type contact layer, the second conductivity different from the channel layer is formed below the channel layer (region). A type contact layer can be formed, and a junction type FET can be easily formed. That is, even if the first conductivity type contact region and the first conductivity type channel region are formed by selective diffusion, it is not necessary to form the second conductivity type contact layer after that, so that the impurity concentration of the first conductivity type channel region is reduced. And its depth will not fluctuate thereafter.

Next, the semiconductor device of the present invention will be described with reference to the drawings. The semiconductor device according to the present invention has a channel region of the first conductivity type (in this example, p-type, hereinafter referred to as p-type or p ⁺ -type), as shown in FIG. A pair of p ⁺ -type contact layers 4 are provided on the channel layer 3 on both sides of 3a, and the second conductivity type (in this example, n-type, hereinafter referred to as n-type or n ⁺ -type) is provided below the channel layer 3. ) N ⁺ -type contact layer 2 is provided. A source / drain electrode 5 is provided so as to make ohmic contact on the pair of p ⁺ type contact layers 4, and ohmic contact is made on the exposed surface of the n ⁺ type contact layer 2 provided below the channel layer 3. The junction type FET is formed by providing the gate electrode 6 on the substrate.

  Although the substrate 1 is not particularly limited, for example, when used for a microwave device or the like, since the electron mobility is high, the series resistance is low, and since the electron saturation speed is high, the cutoff frequency is also high. A compound semiconductor such as GaAs is preferably used as the operating layer, and the substrate 1 is also preferably a semi-insulating GaAs substrate.

The n ⁺ -type contact layer 2 is a layer for forming a pn junction with the channel layer 3. For example, silicon is doped so as to have an impurity concentration of about 5 × 10 ¹⁸ cm ⁻³ and has a thickness of about 20 to 100 nm. As will be described later, a part of the semiconductor laminated portion 7 laminated thereon is removed by etching so that the surface of the partial region 2a is exposed.

In this example, the p-type channel layer 3 is formed to have an impurity concentration and a thickness such that the gate voltage is 0 and the p-channel is closed in order to make the p-channel junction FET operate normally. It is formed to a thickness of about 20 to 100 nm with an impurity concentration of about × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ (for example, about 5 × 10 ¹⁷ cm ⁻³ ).

The p ⁺ -type contact layer 4 is a layer for making ohmic contact with a source / drain electrode 5 to be described later and the p-type channel layer 3, and has a sufficiently high impurity concentration, for example, about 1 × 10 ¹⁹ cm ⁻³ or more. Further, for example, carbon is doped to form a thickness of 30 nm or more. This p ⁺ -type contact layer 4 is a pair of p-type contact layers 4 spaced apart on both sides of the channel region 3a by removing a portion of the GaAs layer epitaxially grown on the surface of the p-type channel layer 3 as an operation region by etching. It is provided with the structure.

A source / drain electrode 5 is formed on the pair of p ⁺ -type contact layers 4 by a laminated structure of a metal such as Ti / Pt / Au or Pt / Ti / Pt / Au that is in ohmic contact. The gate electrode 6 is formed on the exposed portion of the partial region 2a of the n ⁺ -type contact layer 2 by a metal such as an ohmic contact, for example, a stacked structure of AuGe / Ni / Au, whereby the n ⁺ -type contact layer 2 And a p-type channel layer 3 form a junction FET in which a pn junction is formed.

Next, a method for manufacturing this junction FET will be described with reference to the process diagram of FIG. First, as shown in FIG. 2A, an n ⁺ -type contact layer 2 made of GaAs, a p-type channel layer 3 made of GaAs, and a p ⁺ -type contact layer 4 on a substrate 1 made of semi-insulating GaAs. Are epitaxially grown continuously at the aforementioned impurity concentration and thickness, respectively. A semiconductor layer on the n ⁺ -type contact layer 2, in this example, the p-type channel layer 3 and the p ⁺ -type contact layer 4 are collectively referred to as a semiconductor stacked portion 7.

Thereafter, as shown in FIG. 2B, a part of the semiconductor stacked portion 7 is removed by etching to expose a part of the n ⁺ type semiconductor layer 2 to form a partial region 2a. Although not shown in the examples shown in FIGS. 1 and 2, GaAs such as an AlGaAs compound, AlAs, InGaP compound or the like is interposed between the n ⁺ type semiconductor layer 2 and the p type channel layer 3. By interposing an etching stop layer of a different composition and exposing the etching stop layer, the etching solution is changed and only the etching stop layer is removed by etching without over-etching the n ⁺ -type contact layer 2. The partial region 2a can be accurately exposed.

Thereafter, as shown in FIG. 2C, a part of the p ⁺ type contact layer 4 is etched to expose the channel region 3a of the channel layer 3, and a pair of p ^{+ is formed} on the channel layer 3 on both sides thereof. The mold contact layer 4 is left. Also in this case, the thickness of the channel layer 3 is kept constant by providing an etching stop layer similar to that described above between the channel layer 3 and the p ⁺ -type contact layer 4 when the semiconductor layers are stacked. The channel region 3a of the channel layer 3 can be exposed while maintaining.

Then, the source / drain electrode 5 and the gate electrode are provided on the pair of p ⁺ -type contact layers 4 and on the partial region 2a of the n ⁺ -type semiconductor layer 2 by vacuum evaporation or sputtering. 6 is formed. As a result, a junction FET having the structure shown in FIG. 1 is obtained.

FIG. 3 is a cross-sectional explanatory view similar to FIG. 1, showing another embodiment of a junction FET according to the present invention. In this example, when the semiconductor layers are stacked, the channel layer and the p ⁺ -type contact layer are not grown, but the n ⁺ -type contact layer 2 is formed thick, for example, about 1 μm, and the surface of the p ⁺ -type is formed. A source / drain region 41 is formed by diffusion of zinc or the like, and a p-type channel region 31 is formed by diffusing zinc or the like therebetween, and a source / drain electrode 5 is formed on the surface of the source / drain region 41. The gate electrode 6 is formed on the exposed surface of the n ⁺ type semiconductor layer 2 as in the example shown in FIG. In addition, the same code | symbol is attached | subjected to the same part as FIG. 1, and the description is abbreviate | omitted. Even in this structure, the n ⁺ -type contact layer 2 which is the opposite conductivity type layer is provided below the p-type channel layer (region) 31, and further selective epitaxial growth is performed after the channel region 31 is formed. Alternatively, since it is not necessary to perform selective diffusion, a junction FET can be easily manufactured without causing FET characteristic fluctuations.

FIG. 4 is a similar cross-sectional explanatory view showing a modification of the FET shown in FIG. In this example, an undoped layer 8 made of GaAs is inserted between the n ⁺ -type contact layer 2 and the p-type channel layer 3. The other parts are the same as in the example shown in FIG. 1, and the same parts are denoted by the same reference numerals and the description thereof is omitted. By adopting this structure, the electric field strength of the pn junction is relaxed by the undoped layer 8, the reverse breakdown voltage can be improved, and the operating voltage range of the FET can be widened. Further, the gate-source capacitance C _GS can be reduced, and the high frequency characteristics can be improved.

FIG. 5 is also an explanatory cross-sectional view showing a modification of FIG. 1, and the first and second etching stop layers 9 described above are formed at the etching boundary so that overetching is not performed when a part of the semiconductor layer is etched. 10 is inserted. As described above, the material may be a material different from GaAs used as the operation layer, and is formed to a thickness of about 3 to 10 nm. In this example, on the first etching stop layer 9 provided between the n ⁺ -type contact layer 2 and the p-type channel layer 3, but further n ⁺ -type semiconductor layer 21 is provided, the n ⁺ The type semiconductor layer 21 may not be provided, and when it is provided, the impurity concentration may be the same as that of the n ⁺ -type contact layer 2 or may be different. By providing such an n ⁺ -type semiconductor layer 21, the electrostatic withstand voltage between the gate and the drain (source) is improved. In the example shown in FIG. 5, the second etching stop layer 10 remains in the second etching stop layer 10, but the exposed second etching stop layer 10 is removed. Also good. Further, the first etching stop layer 9 is formed to have an impurity concentration comparable to the impurity concentration before and after that, but the second etching stop layer 10 may be an undoped layer or an impurity doped layer.

  FIG. 6 shows IV characteristics of a p-channel FET (gate width: 100 μm) of the semiconductor device manufactured with the structure shown in FIG. Since the channel is a p-channel FET, the signs are all reversed with respect to the n-channel FET. FIG. 6A shows ID with respect to VGS, and it can be seen that a normally-off characteristic with a pinch-off voltage of about -0.2 V is obtained. FIG. 6B is a characteristic showing the change of ID with respect to VDS when VGS is changed, and a satisfactory saturation characteristic is obtained up to VDS = 6V. Further, FIG. 6C is a diagram showing the forward characteristics of the gate, which has a pn junction characteristic, has a wide operating range of the gate forward voltage Vf = 1.0 V, and has a wide operating voltage of VGS. It shows that the range is secured. Further, FIG. 6 (d) shows the reverse characteristics of the gate, the reverse breakdown voltage is about 8V, the effect of interposing the undoped layer 8 is added, and the reverse voltage is also reduced. It can be seen that it has a very high pressure resistance.

  As described above, according to the present invention, a semiconductor layer having a conductivity type different from that of a channel layer is formed below the channel layer, and a gate electrode is formed on the conductivity type layer to form a pn junction of the junction FET. Therefore, it is not necessary to form a conductive type layer opposite to the channel layer by selective epitaxial growth or selective diffusion, and a junction FET can be formed by a very simple manufacturing process. As a result, it is possible to manufacture a semiconductor device with a very wide operating voltage range, which can be manufactured very easily even when a complementary circuit is simply configured in a normally-off type.

It is a section explanatory view showing one embodiment of a semiconductor device of the present invention. It is process cross-sectional explanatory drawing which shows an example of the manufacturing method of the semiconductor device of FIG. It is sectional explanatory drawing which shows other embodiment of the semiconductor device by this invention. FIG. 7 is an explanatory cross-sectional view showing a modification of the semiconductor device of FIG. 1. FIG. 7 is an explanatory cross-sectional view showing a modification of the semiconductor device of FIG. 1. It is an IV characteristic of p channel FET of the structure shown by FIG. It is sectional explanatory drawing which shows the example of the conventional junction type FET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 n ⁺ type contact layer 2a Partial region 3 Channel layer 3a Channel region 4 P ⁺ type contact layer 5 Source / drain electrode 6 Gate electrode 7 Semiconductor laminated portion 8 Undoped layer 9 First etching stop layer
10 Second etching stop layer
21 n ⁺ type semiconductor layer
31 Channel region (layer)
41 p ⁺ type contact region (layer)

Claims (3)

  A channel layer having at least a first conductivity type channel region; a pair of first conductivity type contact layers provided on both sides of the channel region or on the channel layer on both sides of the channel region; A second conductivity type contact layer provided on a lower side; a source electrode and a drain electrode in ohmic contact with the pair of first conductivity type contact layers; and a gate electrode in ohmic contact with the second conductivity type contact layer. A semiconductor device comprising a junction field effect transistor.   2. The semiconductor device according to claim 1, wherein an undoped layer is interposed between the second conductivity type contact layer and the first conductivity type channel layer.   The semiconductor device according to claim 1, wherein each semiconductor layer constituting the junction field effect transistor is made of a compound semiconductor.

Images