JP2001177111A - Lateral junction field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lateral junction field-effect transistor which can be easily manufactured as a semiconductor switching device that is of high power, high in breakdown voltage, and capable of operating at a high speed. SOLUTION: A lateral junction field-effect transistor is equipped with a P-type SiC film 2 which is possessed of no groove on its surface and formed on an SiC substrate 1, an N-type SiC film 3 formed thereon, a channel region 11 formed by thinning the N-type SiC film 3, a source region 22 and a drain region 23 formed on the N-type SiC film 3, and gate electrodes 14 where the two gate electrodes 14 are formed on the flat surface of the P-type SiC film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral junction field effect transistor, and more particularly to a lateral junction field effect transistor using SiC as a semiconductor.

[0002]

2. Description of the Related Art A junction type field effect transistor (JFET: Jun)
ction Field Effect Transistor) is to apply a reverse bias voltage from a gate electrode to a pn junction provided on the side of a channel region through which carriers pass, thereby expanding a depletion layer from the pn junction to the channel region, And conducts operations such as switching. Among them, the “lateral” junction field effect transistor refers to a transistor in which carriers move parallel to the element surface in a channel region. Channel carriers are electrons (n
Type) or hole (p-type), but SiC, which is the object of the present invention, has a higher electron mobility than holes.
Usually, the channel region is an n-type impurity region. Therefore,
In the following description, for the sake of convenience, the carrier of the channel will be electrons, and the channel region will be described as an n-type impurity region. However, it goes without saying that the channel region may be a p-type impurity region.

In recent years, JF using silicon carbide (SiC)
ET is attracting attention. SiC has carrier mobility of S
Since it is as large as i, the saturation drift velocity of electrons is as large as GaAs, and the withstand voltage is large, studies on high-speed switching elements and high power elements are being studied. S
The crystal structure of iC includes a hexagonal close-packed structure and a cubic close-packed structure. In the hexagonal close-packed structure, there are many structures having different repetition periods of the layers. Type) is known. Representative polytypes include 3C, 4H, 6H, and the like. C is cubic,
H means hexagonal, and the number before it indicates the repetition period. The cubic form is only 3C, which is
C and others are collectively read as α-SiC. In the following description, only 6H or 4H of α-SiC is used.

FIG. 6 is a sectional view showing the structure of a JFET using SiC (PA Ivanov et al: 4H-SiC field-effect t).
ransistor hetero-epitaxially grown on 6H-SiC subst
rateby sublimation, p757 Silicon Carbide and Relat
ed Materials 1995 Conf., Kyoto Japan). In FIG. 6, a buffer layer 109 is formed by heteroepitaxially growing a 4H-SiC film 109 containing Sn on a 6H-SiC substrate 101 by a vacuum evaporation method. Buffer layer 10
9, an SiC film 1 containing Al which is a p + -type impurity
The n-type SiC film 103 having a source region 117 and a drain region 118 is formed on both sides thereof. The source electrode 112 and the drain electrode 113 are provided above the left and right of the channel region, and the gate electrode 114 is formed below the source and drain electrodes with a groove 115 therebetween. As the electrodes 114, a Ni film of the base film 120 and an Al film of the upper film 121 are formed. By using this lateral JFET, a JFET having a high electron drift mobility and an extremely high electron mobility can be formed.

[0005]

However, this J
The FET has the following problems. (A) It is insufficient in that it has both low on-resistance and high withstand voltage.

The breakdown voltage of a JFET is determined by the breakdown voltage of a pn junction formed by an n-type impurity region of a channel and a p-type impurity region in contact with the region. Therefore, JFET
In order to improve the breakdown voltage performance, the breakdown voltage of the pn junction may be improved. In order to improve the breakdown voltage of the pn junction, the concentration of the n-type impurity, which is the impurity of the channel, should be reduced and the film thickness should be equal to or greater than the maximum depletion layer width. Resistance in a state where carriers are flowing through the region). As a result, power is consumed and the element temperature rises. Horizontal JFE
Since T has a negative temperature coefficient in a range where the drain current is large, negative feedback is applied to the temperature rise, but no negative feedback is applied in a range where the drain current is small. Further, regardless of the magnitude of the drain current, power consumption in the element is not preferable. Another reason why the on-resistance of the JFET cannot be reduced is the contact resistance at the electrodes. FIG.
In the configuration shown in (1), when each electrode is formed of Ni, the impurity concentration is too low, so that the Schottky contact is likely to remain, and the ohmic contact cannot be obtained. (B) The switching speed is insufficient.

[0007] The switching speed is determined by the charge / discharge time of the depletion layer of the pn junction. Assuming that the depletion layer capacitance is Cg and the gate resistance is Rg, the charge / discharge time is determined by CgRg. Therefore, if the gate resistance Rg can be reduced, the switching time can be shortened. However, in the conventional JFET shown in FIG. 6, a groove is formed in the second conductivity type region, and the gate resistance cannot be sufficiently reduced. In addition,
The gate resistance Rg can be said to be the resistance of the path from the gate electrode 114 to the pn junction interface at the center of the channel 111 if emphasis is placed on grasping intuitively at the expense of some accuracy. (C) The manufacturing process is complicated and requires high precision and strict control.

When the JFET shown in FIG. 6 is manufactured, it is manufactured by the following method. The buffer layer 109 is formed on the SiC substrate 101, and then the p + type SiC film 10
2 is formed. Next, as shown in FIG. 7, an n-type SiC film is formed, and a portion where a channel, a source, and a drain region are to be formed is patterned using RIE (Reactive Ion Etching). Next, as shown in FIG. 8, a Ni film is formed as the lower layer 120 of the electrode. On this Ni film,
As shown in FIG. 9, an Al film for forming the upper layer 121 of the electrode is formed. At this time, the Al film cannot be positioned just above the Ni film to form a film, which often causes misalignment. If Al adheres to the side wall or the like, it acts as a floating electrode and makes the device operation unstable. Next, as shown in FIG. 10, a channel region 111 is formed by RIE using the source electrode 112 and the drain electrode 113 as a mask and etching between them. At this time, the surface of the p + film 102 is also etched, and a groove 115 is formed together with the channel region. At the time of this etching, Al and the like adhered due to the above positional shift are also removed. Note that the electrodes are Ni film and A
The two-layer film with the 1 film is used to form an ohmic contact. Due to this groove, the resistance Rg of the path from the gate electrode to the pn junction interface at the center of the channel region increases, and when used for a switching element, the rise (fall) time becomes long. In addition, extra man-hours are required for the manufacturing process, which causes an increase in cost. (D) The operation becomes unstable due to the surface charge, and the surface leakage current is large.

A malfunction occurs due to the surface charge and the surface leakage current, and the yield is reduced. Therefore, the present invention
It is an object of the present invention to provide a lateral junction type field effect transistor which is easy to manufacture as a high power and high withstand voltage semiconductor switching element having excellent high speed performance.

[0010]

According to a first aspect of the present invention, there is provided a lateral JFET comprising: an SiC substrate; a second conductivity type SiC film formed on the substrate and having a groove-free surface;
a first conductivity type SiC film formed on the iC film, a channel region formed by reducing the thickness of the first conductivity type SiC film, and a first conductivity type SiC film. A film made of SiC of the first conductivity type, comprising a source region and a drain region separately formed on both sides of a channel region, and a gate electrode. The gate electrode is composed of two gate electrodes formed on the flat surface of the second conductivity type SiC film.

With this configuration, since no groove or the like is provided between the source / drain and the gate, the gate resistance can be reduced, and as a result, the switching response speed can be increased. In addition, in the manufacturing process, there is no problem with slight displacement of the formation of the gate electrode, so that a decrease in yield can be prevented. Therefore, it can be used for a high-speed switching element. The first conductivity type may be p-type or n-type, and the second conductivity type may be n-type or p-type.

According to a second aspect of the present invention, a lateral JFET is formed on a second conductivity type SiC substrate, a second conductivity type SiC film formed on the substrate and having a groove-free surface, and a second conductivity type SiC film. The first conductivity type SiC film, the channel region formed by reducing the thickness of the first conductivity type SiC film, and the first conductivity type SiC formed on the first conductivity type SiC film. And a source region and a drain region separately formed on both sides of the channel region, and a gate electrode. The gate electrode is
The back gate structure is provided over the back surface of the second conductivity type SiC substrate.

According to this structure, the gate electrode is provided on the entire back surface of the second conductivity type SiC substrate, so that the gate resistance is reduced. As a result, the response speed of the switching is improved, and the switching element can be used as a high-speed switching element. Further, the formation of the gate electrode becomes easy, and the yield can be improved.

According to a third aspect of the present invention, in the lateral JFET of the first or second aspect, the source region and the drain region have a higher impurity concentration than the impurity concentration of the first conductivity type SiC film on both sides of the channel region. Contains one conductivity type impurity.

With this configuration, the on-resistance can be reduced without lowering the breakdown voltage. The electrodes are Ni and A
Ohmic contact can be formed without using a two-layer structure using 1 or the like. For this reason, it is not necessary to form a groove as a result in the manufacturing process. As a result,
The gate resistance can be kept low, and the rise (fall) time of switching can be reduced.

In the lateral JFET according to the fourth aspect,
3 in the lateral JFET of the second conductivity type,
The impurity concentration of the C film exceeds 10 ¹⁹ cm ^-3 .

With this configuration, even in the case of a single-layer electrode made of Ni or the like, ohmic contact is established in the gate electrode, and the gate resistance is reduced. For this reason, the rise time and the fall time at the time of switching can be shortened, and a high-speed response can be achieved.

In the lateral JFET according to claim 5, claims 1 to
4. In any of the lateral JFETs according to 4, the source electrode formed on the source region, the drain electrode formed on the drain region, and the second conductivity type SiC film or the second conductivity type SiC film are formed on the second conductivity type SiC substrate. The gate electrode is made of a metal that makes ohmic contact with SiC containing impurities with which the respective electrodes come into contact.

With this configuration, the electrodes can be formed by simple steps. That is, the electrode plate may have a single-layer structure, and need not have a two-layer structure or the like. As a result, a groove or the like for increasing the gate resistance is not formed as a result, and the rise (fall) time of switching can be shortened. Note that a metal that makes ohmic contact with the second conductivity type and the first conductivity type SiC film containing impurities at a high concentration includes Ni and the like.

In the lateral JFET according to the sixth aspect,
In any one of the lateral JFETs 5, the surface excluding the source electrode, the drain electrode, and the gate electrode is covered with an insulating film.

When the element surface is exposed, operation instability occurs due to surface leakage current and surface charge formation. By the coating with the insulating film, such troubles can be prevented and the switching operation can be performed stably.

In the lateral JFET according to the seventh aspect,
In any of the lateral JFETs of No. 6, the SiC substrate is 6
An H-SiC substrate, a second conductivity type SiC film and a first conductive type SiC film;
Each of the conductive SiC films is 6H-SiC.

According to the above-described structure, thin films having good crystallinity are stacked, and there is no case where the yield is reduced due to malfunction or the like due to poor crystallinity.

In the lateral JFET of claim 8, claims 1 to
6, in the lateral JFET of the second conductivity type,
The C film and the first conductivity type SiC film are both 4H-Si
C, and a second conductivity type SiC film made of 4H-SiC is formed on a 6H-SiC substrate via a 4H-SiC buffer layer.

4H-S with good crystallinity due to buffer layer
Since an iC film can be obtained, and 4H-SiC has a higher electron mobility than that of 6H-SiC or the like,
It can be suitable for a high-speed switching element or the like.

According to the ninth aspect of the invention, there is provided a lateral JFET.
6, the SiC substrate is 4
An H-SiC substrate, a second conductivity type SiC film and a first conductive type SiC film;
Each of the conductive SiC films is 4H-SiC.

According to the above configuration, thin films having good crystallinity are stacked, and there is no case where the yield is reduced due to malfunction or the like due to poor crystallinity. In addition, as described above, since 4H-SiC has a higher electron mobility than that of 6H-SiC or the like, 4H-SiC can be suitable for a high-speed switching element or the like.

In the lateral JFET according to the tenth aspect, the first aspect has the following features.
In any one of the lateral JFETs Nos. 1 to 6,
Both the iC film and the first conductivity type SiC film are 6H-S
The second conductivity type SiC film made of iC and made of 6H-SiC is formed on a 4H-SiC substrate via a 6H-SiC buffer layer.

6H-S with good crystallinity due to buffer layer
An iC film can be obtained, and SiC of an appropriate crystal type can be used depending on the application.

[0030]

Next, an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a cross-sectional view of a lateral JFET according to a first embodiment. In FIG. 1, 6
On a H-SiC substrate 1, a 6H-p + type SiC film 2 is formed. Hereinafter, the SiC film formed on these will be
Since all are 6H-SiC films, "6H-" is omitted. On the p + -type SiC film 2, an n-type SiC film 3 in which a channel region is formed is formed. Channel region 11
Is formed at the center portion of the n-type SiC film 3 having a reduced thickness. Source electrode 12 and drain electrode 13
Are formed in the source region and the drain region, which are the n + SiC films 4 respectively located above both sides of the channel when viewed from the channel region. Further, the end of the p + -type SiC film 2 is not covered with the upper n-type Si film 3,
The source electrode 12 and the drain electrode 1 formed above the center on one relatively wide uncoated surface.
3, two gate electrodes 14 are formed. That is, the conductive path between the source / drain region and the gate electrode has a wide cross section without any narrow part constricted by a groove or the like in the middle. The n-type impurity concentration in the source region and the drain region is set high so that ohmic contact with Ni or the like can be obtained. The impurity concentration in each region is desirably set as follows, for example. Channel region 11 and n-type SiC film 3: n-type impurity
2 × 10 ¹⁷ cm ⁻³ source and drain regions (n + -type SiC film) 4: n-type impurity> 1 × 10 ¹⁹ cm ⁻³ p + -type SiC film 2: p-type impurity> 1 × 10 ¹⁹ cm ⁻³ The channel region has a thickness a, a length 1 and a width w in the direction perpendicular to the plane of the drawing that can be determined according to the size of the element.
The source electrode 12 and the source region 22, the drain electrode 13 and the drain region 23, and the gate electrode 14 and the p + -type SiC film 2 serving as the gate region all have an impurity concentration of 1.
Since the region having a high concentration of more than × 10 ¹⁹ cm ⁻³ is connected to the metal film, an ohmic contact can be formed by using, for example, Ni as the material of the metal film.

When the gate electrode 14 is turned off,
, A depletion layer extends from the pn junction below the channel region 11 to the channel region 11,
The cross section of the channel region is closed. Roughly,
The gate resistance from the gate electrode to the lower end of the center of the depletion layer is Rg.
And the capacitance of the depletion layer can be regarded as the gate capacitance Cg. In order to turn on the depletion layer, the reverse bias is eliminated to remove the depletion layer. In the ON state, the channel region 11 extends from the source electrode.
Carriers flow toward the drain electrode via. When turning on and off are repeated, it can be considered that the gate resistance Rg and the gate capacitance Cg are connected in series, and the rise (fall) time is proportional to the time constant RgCg in the transient phenomenon of this circuit. I do. Therefore, the rise (fall) time of switching can be shortened by reducing the gate resistance Rg.

By using the structure of the lateral JFET shown in FIG. 1, it is possible to improve the breakdown voltage without increasing the on-resistance, shorten the switching response time, and provide a JFET with stable performance. This JFET has a simple and easy manufacturing process and rarely causes troubles such as a decrease in yield, so that it can be manufactured at a low cost after all.

(Embodiment 2) FIG. 2 is a sectional view of a lateral JFET according to Embodiment 2. The impurity concentration of portions other than the gate electrode is the same as that of the lateral JFET of FIG.
FIG. 2 is characterized in that the gate electrode 14 is formed over the back surface of the p-type SiC substrate 1. According to the configuration of FIG. 2, the ON / OFF state can be realized by applying the same gate voltage as in FIG. Further, the gate resistance Rg can be further reduced, and as a result, the rise (fall) time of switching can be shortened. Further, the manufacturing method is simplified, and the yield can be improved.

[0035]

EXAMPLE A lateral JFET using the structure shown in FIG. 1 was manufactured. In the channel region 11, the channel length l is 10
μm, the channel thickness was 300 nm (0.3 μm), and the channel width w perpendicular to the paper was 700 μm. FIGS. 3 to 5 are views illustrating steps in the present invention corresponding to FIGS. 7 to 10 illustrating a method for manufacturing a conventional lateral JFET. First, a p + -type SiC film is formed to a thickness of 1 μm on a p-type SiC substrate, and then an n-type SiC film is formed. Further, after forming an n + -type SiC film thereon, etching is performed by RIE to pattern a region including the source and drain regions (FIG. 3). Next, etching is performed by RIE in the center of the portion including the source and drain regions to form a groove, thereby forming a structure in which the source region 22 and the drain region 23 are separated (FIG. 4). Then, p +
A gate electrode is provided on SiC film 2, and a source electrode 12 and a drain electrode 13 are provided in source region 22 and drain region 23, which are n + impurity regions, respectively (FIG. 5). Thereafter, an etching step for forming a groove in p + SiC film 2 is not performed. In the lateral JFET of the comparative example, as shown in FIG. 6, the impurity concentration of both the source region and the drain region was not particularly increased, and the concentration of the n-type SiC film 3 was 2 × 10 ^17.
cm ⁻³ . The depth of the groove in the p-type SiC film of FIG.
A lateral JFET in which the thickness of C was 0.3 μm was also prototyped as a comparative example. The rise (fall) time of switching was measured for both lateral JFETs. Table 1 shows the measurement results obtained by standardizing the rise time of the comparative example to 1.

[0036]

[Table 1]

As shown in Table 1, by forming the p-type SiC film 2 on a smooth surface without grooves and forming the gate electrode 14 thereon, the switching rise time (fall time) can be reduced to 3 times.
It could be shortened by a factor of one. As a result, the horizontal J with high breakdown voltage, low on-resistance and high-speed switching
It became possible to obtain FET.

While the embodiments and examples of the present invention have been described above, the embodiments and examples of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these. The invention is not limited to the embodiments and examples. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

[0039]

According to the present invention, it is possible to provide a lateral JFET suitable for a high-power semiconductor switching element having high withstand voltage and high speed. Since this lateral JFET can be manufactured by a simple and stable manufacturing process, it can be manufactured with a high yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a lateral JFET according to a first embodiment.

FIG. 2 is a cross-sectional view of a lateral JFET according to a second embodiment.

FIG. 3 is a cross-sectional view of a stage in which an n + SiC film is formed and patterned by RIE in an intermediate fabrication stage of the lateral JFET of FIG. 1;

FIG. 4 is a cross-sectional view of a stage where a channel region is formed by RIE after the stage of FIG. 3;

FIG. 5 is a cross-sectional view of a stage where an electrode is formed by forming a Ni film after the stage of FIG. 4;

FIG. 6 is a configuration sectional view of a conventional lateral JFET.

FIG. 7 is a cross-sectional view of a stage in which an n-channel layer is formed in an intermediate fabrication stage of the lateral JFET of FIG. 6;

FIG. 8 shows the first layer N of the two-layer electrode after the step of FIG. 7;
It is sectional drawing in the stage which formed the i film.

FIG. 9 shows the second layer A of the two-layer electrode after the stage of FIG. 8;
FIG. 4 is a cross-sectional view at the stage when an l film is formed.

FIG. 10 is a cross-sectional view of a stage where a groove is provided between the gate region and the center after the stage of FIG. 9;

[Explanation of symbols]

1 p-type SiC substrate, 2 p-type SiC film, 3 n-type Si
C film, 4 n + type SiC film (source and drain regions),
5 insulating film, 7 low concentration layer (n-type SiC film), 11
Channel region, 12 source electrode, 13 drain electrode, 14 gate electrode, 20 Ni layer, 22 source region, 23 drain region, 114 gate electrode, 120
Ni film, 121 Al film, 1 channel length, a channel thickness, w width in the direction perpendicular to the paper.

Claims (10)

[Claims] An SiC substrate, a second conductivity type SiC film formed on the substrate and having a surface without a groove, and a first conductivity type S formed on the second conductivity type SiC film.
an iC film, a channel region having a reduced thickness in the first conductivity type SiC film, and a first conductivity type S formed on the first conductivity type SiC film.
a source / drain region separately formed on both sides of a channel region; and a gate electrode, wherein the gate electrode is formed on a flat surface of the second conductivity type SiC film. A lateral junction field-effect transistor comprising two formed gate electrodes. 2. A second conductivity type SiC substrate, a second conductivity type SiC film formed on the substrate and having a groove-free surface, and a first conductivity type SiC film formed on the second conductivity type SiC film. Conductivity type S
an iC film, a channel region having a reduced thickness in the first conductivity type SiC film, and a first conductivity type S formed on the first conductivity type SiC film.
a film made of iC, comprising: a source region and a drain region separately formed on both sides of a channel region; and a gate electrode, wherein the gate electrode is provided over a back surface of the second conductivity type SiC substrate. Lateral junction field-effect transistor comprising a back gate structure. 3. The method according to claim 1, wherein the source region and the drain region are:
3. The lateral junction field-effect transistor according to claim 1, further comprising an impurity of a first conductivity type higher than an impurity concentration of a portion of the first conductivity type SiC film on both sides of the channel region. 4. 4. The lateral junction field effect transistor according to claim 1, wherein an impurity concentration of said second conductivity type SiC film exceeds 10 ¹⁹ cm ⁻³ . 5. A source electrode formed on the source region, a drain electrode formed on the drain region, and the second conductivity type SiC film or the second conductivity type S.
5. The gate electrode formed on the iC substrate is made of a metal that makes ohmic contact with SiC containing impurities with which each electrode contacts. 6.
The lateral junction field-effect transistor according to any one of the above. 6. The lateral junction field effect transistor according to claim 1, wherein a surface excluding the source electrode, the drain electrode, and the gate electrode is covered with an insulating film. 7. The SiC substrate is a 6H-SiC substrate, and the second conductivity type SiC film and the first conductivity type SiC film are provided.
The lateral junction field effect transistor according to claim 1, wherein the C film is 6H—SiC. 8. The second conductivity type SiC film and the first conductivity type SiC film.
Each of the conductive SiC films is 4H-SiC and 4H-SiC.
The second conductivity type SiC film made of SiC is 6H-SiC.
7. The lateral junction field-effect transistor according to claim 1, wherein the lateral junction field-effect transistor is formed on a substrate via a 4H-SiC buffer layer. 9. The SiC substrate is a 4H—SiC substrate, and the second conductivity type SiC film and the first conductivity type SiC film.
The lateral junction field-effect transistor according to claim 1, wherein each of the C films is 4H—SiC. 10. The SiC film of the second conductivity type and the SiC film of the first conductivity type are both 6H-SiC.
The second conductivity type SiC film made of H-SiC is 4H-Si.
7. The lateral junction field-effect transistor according to claim 1, wherein the transistor is formed on a C substrate with a 6H-SiC buffer layer interposed therebetween.