TW474015B - Lateral junction field-effect transistor - Google Patents

Abstract

A lateral SiC JFET including a high-mobility-carrier channel region is manufactured with high yield using an n-type SiC substrate. The horizontal JFET comprises an n-type SiC substrate (1n), p-type SiC film (2) formed on the front surface of the n-type SiC substrate, n-type SiC film (3) formed on a p-type SiC film and including a channel region (11), source and drain regions (22, 23) formed on the n-type SiC film and separated by the channel region, and a gate electrode (14) formed in contact with the n-type SiC substrate (1n).

Description

474015 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -------- B7_______ V. Description of the Invention (1) Technical Field The present invention relates to horizontal joint type% efficiency transistors _T: Junction Field Effect Transistor ) 'Specifically, it relates to a horizontal joint type field effect transistor which can be used as a power supply transistor. 2. Description of the Related Art A junction field effect transistor (JFET) is a ρ η junction on the side 4 of a channel region through which a carrier passes. By applying a reverse bias voltage from a gate, the layer direction from the ρ η junction is directed. The channel area is expanded to control the conductivity of the channel area and perform switching and other actions. The towel, "horizontal" JFET refers to those in which the carriers move parallel to the surface of the element in the channel area. Although the carrier of the channel may be an electron (n-type) or a positive charge (p-type), the Sic of the subject of the present invention has an electron mobility higher than that of the positive charge. Generally, an 11-type impurity region is used as the channel region. Hereafter, for convenience of explanation, the carriers of the channel are electrons, and the n-type impurity region is used to describe the channel region, but it goes without saying that the p-type impurity region may also be used in the channel region. As mentioned above, the carrier mobility of Sic is larger than that of Si, the saturation drift (electron drift) speed and GaAs are large, and the withstand voltage is large. Therefore, it is used for the research of high-speed switching elements or high-power components. In progress. The Sic crystal structure has the hexagonal closest packing structure and the cubic closest packing structure. In the hexagonal closest packing structure, there are many different layers with different repetitive cycles. It is known that there are more than 100 types of crystal polymorphs (p〇ly_type). . Representative polymorphisms are 3C, 4H, etc. C represents a cubic crystal, and 六 represents a hexagonal crystal, and the number preceding it represents a repetition period. The cubic crystal form is only 3C, which is called 々-Sic, and others are collectively called π-sic. Subsequent descriptions only use α-siCi 6H or -4- This paper size applies to China National Standard (CNS) A4 (210 χ 297 issued) '------- --------- ----- Φ (Please read the notes on the back before filling this page) Order --- Thread—Awi.% A7

474015 V. Description of the invention (2) 4H. FIG. 34 is a cross-sectional view of an example of a JFET using SiC (u.s. patent v. 5,264,713, John W. Palmour, etc.). In the same figure, the conductivity type of the Sic substrate 101 is preferably a p-type, and is set to a p-type SiC substrate. The conductivity type of the SiC film 102 formed on one of the regions of the Sic substrate ι01 is also preferably n-type, and is set to be a p-type SiC film 102. In addition, on the p-type SiC film 102, an n-type sinker film 103 is formed, which contains a thin fleshed portion u1 corresponding to the channel region. On this n-type SiC film 103, an n + -type impurity layer 117 is formed, which is in contact with the source 112 ohms; and a n + -type impurity layer 118 is made in contact with the drain, 113 ohms. The gate 114 is formed as a back gate 114 on the inner side of the p-type Sic substrate ι01. The surfaces other than the source, drain, and gate are covered with a protective film 126. In the conventional technique (Fig. 34), the reason why the conductivity type of the SiC substrate is preferably p-type is as follows. As described above, since the carrier in the channel region can obtain a high degree of mobility, it is assumed to be an electron. Therefore, the layer included in the channel region is an n-type sic film. Therefore, the layer in which the carriers in this n-type SiC film are restricted around becomes a p-type sic film. If an 11-type ^ (: substrate is used as the sic substrate for the p-type sic film, a reverse bias is applied to the junction of the n-type Sic substrate and the p-type SiC film when a positive potential is applied to the gate. An empty layer is generated. Therefore, it is necessary to evaluate the effect of this empty layer to judge. Conversely, depending on the use of a p-type sic substrate, it is not necessary to evaluate the effect of this empty layer. In the switching (〇n_〇ff) operation, it is not necessary to consider The reverse bias of the junction of the laminated part on the way to the channel area. Therefore, by using the above-mentioned conductive SiC substrate, the empty layer can be grown only in the channel area if necessary, and a high-mobility carrier can be used to obtain large power — (Please read the precautions on the back before filling this page} J ^ T · --Line-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -5- 474015 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ____B7 __ V. Description of the invention (3) High-speed switching elements used. However, compared with n-type SiC substrates, p-type SiC substrates have higher defect density than micro pipes. Therefore, even in the production of semiconductor devices such as JFETs Indispensable SiC substrate In the crystal growth layer, the defect density also becomes higher. Reflecting this high defect density, the JFET formed on the p-type SiC substrate has a low manufacturing rate of good quality JFET and the finished JFet also has a large leakage current ... When the horizontal JFET of FIG. 34 is in the “ON” state, the source region 103 of the n-type impurity region and the p-type impurity layer 10 A forward bias is applied to the joint surface. In the OFF state, a reverse bias is applied to the joint surface, and the layer grows in the channel region and cuts off the channel region. In the ON state At the junction of the source region 1 0 3 and the p-type impurity layer 1 2 of the n-type impurity region, it is desirable to apply a forward bias so that the current escapes from the channel region and flows into the gate 114. From this channel region, the leakage flows into the gate. The current of 丨 14 increases with the increase of forward bias voltage and temperature. The current leaked into the gate from the channel area will affect the amplification. If this current is increased, the amplification will be reduced, causing problems. The horizontal JFET shown in FIG. 34 is a p-type epitaxial Sic film to form the above-mentioned pn junction surface. Compared with the area of the pass-through region of the portion connected to the bottom of the trench 124, the n-type impurity region 103 and the 1) -type channel region have a problem that the area of the pn junction is too large. That is, the switching operation is performed on the junction plane. The ratio of the area of the I channel area is small. Compared with this, it does not help the switching operation, and it becomes a circuit path leaking from the above channel area. ---— (Please read the precautions on the back before filling this page) Order-I line. -6-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 474015 A7 _ B7 V. Description of the invention (4) Figure 3 5 is a structural cross-sectional view of another conventional mode JFET using SiC (PA Ivanov et al: 4H-SiC field-effect transistor hetero-epitaxially grown on 6H-SiC substrate by sublimation, p757 Silicon Carbide and Related Materials 1995 Conf ·, Kyoto Japan). In FIG. 35, a 4H-SiC film 109 containing Sn is formed on a 6h-SiC substrate 101, and uneven epitaxial growth is performed by a vacuum evaporation method to form a buffer layer 109. On the buffer layer 109, a p + -type impurity-containing A1 SiC film 102 is formed, and a channel region 111 is arranged on the central portion, and on both sides of the buffer layer 109, a source region 117 and a drain region 118 containing nitrogen are formed. The n-type SiC film 103 is formed. The source electrode 112 and the drain electrode 113 are disposed above and below the channel region, and the gate electrode 114 is formed below the source and drain electrodes via a trench 115. The gate 114 is a Ni film with a base film 120 and an A1 film with an upper film 121. By using this horizontal JFET, a JFET with high electron drift mobility and very high electron mobility can be formed. However, the JFET of Fig. 35 has the following problems. (a) The high withstand voltage and j 氐 "(0N) resistance cannot be fully provided. The withstand voltage of the JFET is formed by the ρη junction formed by the n-type impurity region of the channel and the mouth-type impurity region connected to this region. The withstand voltage is determined. Therefore, in order to improve the withstand voltage performance of the JFET, it is only necessary to increase the withstand voltage of ρ η junction. In order to increase the withstand voltage of ρη junction, it is only necessary to reduce the concentration of channel impurities, that is, n-type impurities. As a result, the channel current will decrease, and the ON resistance (resistance of the carrier flowing in the channel region) will increase. Therefore, power will be consumed, which will cause the component temperature to rise. The horizontal JFET has a large range without current. At this time, the temperature coefficient is negative. Although there is a negative feed back corresponding to the temperature rise, there is no negative feedback in the range where the sink current is small. Also, --------- ------- (Please read the notes on the back before filling this page) _ Line ·

474015 A7

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (5) Regardless of the amount of current drawn, components are not expected to consume power. Another reason for reducing the above-mentioned JFET blocking method is the contact resistance of the electrodes. In the structure shown in FIG. 3, if each electrode is formed with n i, the impurity concentration is too low, and schottky is easy to remain, and ohmic contact cannot be obtained. (b) The switching speed is not fast enough. The switching speed is determined by the charge and discharge time of the empty layer bonded by ρ η. If the empty depletion layer capacitance is C and the gate resistance is Rg, the charge and discharge time is proportional to the product CRg of the two. Therefore, if the gate resistance Rg can be reduced, the switching time can be accelerated. However, the conventional JFET shown in FIG. In addition, if the gate resistance Rg sacrifice a little accuracy and value intuition, it can be regarded as the resistance of the path from the gate U4 to the ρ η junction interface of the center of the channel i. (c) The manufacturing steps are complex and require high precision and strict management. In the case where the above-mentioned JFET of Fig. 35 is manufactured, it is manufactured by the following method. A buffer layer 109 is formed on the SiC substrate 101, and then a p + -type sic film 102 is formed. Next, as shown in FIG. 36, an n-type SiC film is formed, and portions where the channels, sources, and drains are formed are patterned by RIE (Reactive Ion Etching). Next, as shown in Fig. 37, a Ni film is formed as the lower layer 120 of the electrode. On this Ni film, an A1 film is formed as the upper layer 121 of the electrode as shown in Fig. 38. At this time, the A1 film cannot be formed at a position directly above the Ni film, and there are many cases where positional deviation occurs. If A1 is attached to the side wall, etc., it will act as a floating electrode, making the device unstable. Secondly, as shown in FIG. 39, the channel region 111 is formed by etching using the source 112 and the drain 113 as masks according to RIE. At this time, the surface of the p + film 102 is also etched, forming a through hole and forming -8-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) (Please read the notes on the back before filling (This page) ---- ^ — Order --------- · 474015

Explanation of the invention (6) When Λ 15 is etched here, the a 1 and the like attached due to the above position deviation are also removed = the reason for making the private electrode a two-layer film of the Ni film and the A 1 film is to The contact is formed. Because of the above groove, the resistance Rg of the path from the gate to the pn interface interface at the center of the channel region increases, and the rise (fall) time becomes longer when used as a switching element. Moreover, the formation of the groove requires Adding more manufacturing steps' causes cost increase. (D) Transistor 4 is highly variable due to variations in impurity concentration or thickness in the channel area. This avoids deviations between such components, and reduces the pass area. For the purpose of resistance, if a high concentration of impurity elements is implanted, the withstand voltage performance will be inferior. B. Therefore, it is hoped that JFETs that do not use high concentration impurities and are not easily affected by variations in impurity concentration or thickness of the channel region will be affected. ^ (e) The above jfeT is usually "normally open" (n〇rmaUy 〇N) type (0N state when no pressure is applied to the brake). When used for rotating machine control, the gate circuit structure is complicated. gp, because when no voltage is applied to the brake Because of the state of ON, in the case of the brake circuit failure, the rotating machine maintains rotation to cause danger. Therefore, in order to respond to the failure, it is necessary to set up a mechanism to "close" (OFF) when the brake circuit fails. In the FF state, electric power must be continuously applied. 'It will still consume power during OFF. (F) Unstable operation due to surface charge and large surface leakage current. Malfunction due to surface charge or surface leakage current such as 1¾, The present invention is developed to solve the above-mentioned problems. The first object of the present invention is to obtain a Sic-type horizontal JFET, which uses an n-type sic substrate and has a channel region with a highly mobile carrier. Good rate. # (Please read the precautions on the back before filling out this page) Ordering line 丨-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-9-

474015

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The second item of the invention is to provide horizontal JFETs that can be easily manufactured, with low losses, high endurance, and high-speed switching characteristics. Therefore, a third object of the present invention is to provide a horizontal warship, which suppresses the leakage current in the straight channel region in the shape of a cymbal, and does not cause a reduction in magnification. The invention discloses that the first horizontal JFET of the present invention is provided with ·· n-type Sic substrate; p-type Sic film 'which is formed on the aforementioned 11-type (: substrate surface; 11-type (:: film) is formed on the aforementioned P-type SiC film and contains a channel region Source and drain regions, which are formed on the n-type SiC film, are formed on both sides of the channel region, and gates, which are provided in connection with the n-type SicS plate. According to the above structure, the Using an n-type SiC substrate with a low defect density, a JFET that drives high-mobility carriers is manufactured at a high aperture rate. At this time, a problem may occur when the JFET is on or off. Also, the i-th aspect of the present invention For horizontal JFET, it is significant to make a horizontal JFET on an n-type Sic substrate. The horizontal JFET of the first aspect of the present invention is that the n-type and p-type cannot be replaced with a chip. In other forms of the present invention, η-type and ρ-type can be replaced. It is assumed that η-type and ρ-type are replaced. In the "normally open," type 0 N state of the JFET, no problem occurs because of applying a negative gate voltage. That is, in the 0FF state, the junction of the n-type Sic substrate and the 卩 -type SiC film is applied. In the OFF state, reverse bias is applied only at the junction of the p-type SiC film and the η-type SiC film, and the empty layer expands in the channel region of the impurity concentration. Cut off the carrier path. ------- Order— (Please read the notes on the back before filling this page) Line-Φ · -10- 474015 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs Invention description (8)

In the "OFF state" of "normally OFF" type JFETs, diffusion potentials occur at the junction between the n-type siC substrate and the p-type SiC film and the junction between the p-type siC film and the η-type SiC film. Empty layers occur, but no problem occurs because each department is independently expanded. In the “N” state of the “normally ON” type, although the gate voltage can be set to ON, the empty layer caused by the diffusion potential expands. In order to allow more current to flow and to eliminate the empty layer caused by the diffusion potential, a positive potential must be supplied to the gate. Therefore, it is necessary to inspect the jade layer derived from the application of a positive potential to the gate. When the gate potential becomes positive, a reverse bias is applied to the junction between the n-type substrate and the p-type SiC film. However, by increasing the impurity concentration of the n-type SiC substrate and the impurity concentration of the p-type siC film at the same time, the width of the empty layer becomes smaller. Therefore, according to the effect of the channel, the empty layer is removed and the current flows. In addition, there is a case where the pressure resistance of the joint is lost due to an increase in the impurity concentration, and a current may flow. Therefore, the empty layer in the joint portion has almost no effect on the operation. In order to obtain the above-mentioned junction portion, the N-type impurity concentration of the n-type 3 redundant substrate may be 1 × 1019 cm · 3, and the p-type impurity concentration of the P-type SiC film may be 1 × 1019 × 3. This result can improve the yield from the Sic substrate to the finished product, and 31 (:; system jfet) that can perform high-speed operations such as high-speed switching. '· Normally off, the type JFETiON state will occur with the above The same phenomenon occurs when the ON state of the JFET is normally turned on, as described above, and no particular problem occurs. That is, the corresponding JFET is the "normally open" type or the "normally closed" type, as follows Apply voltage and perform "switch" (0N_0FF) operation., The normally open "type" gate voltage changes between the range of negative (OFF) to positive (ON). Also, the "normally closed" type ------- ^ --------- line-- (Please read the notes on the back before filling this page)

474015 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The description of the invention (9) varies from ο (OFF) to positive (0N). As usual, the type JFET is realized as described above, so that the impurity concentration or structure meets certain requirements. The above-mentioned horizontal junction type field-effect transistor of the present invention is, for example, viewed from a plane, and is in the aforementioned p The area of the n-type sic film includes the area of the n-type sic film. According to this configuration, the end face of the n-type SiC film is located on the inner side of the end face of the p-type Sic film under the plane. The structure of the type 3 redundant film and the n-type SiC film above it has a stepped structure. The end faces of these Sic films are usually formed by RIE (Reactive Ion Etching). As is known, the end faces of the n-type Sic film and the P-type SiC film In the structure with the same end faces, when the 11-type ITO film and the underlying p-type SiC film are etched together, the above-mentioned end face is continuously exposed to ions. On the other hand, in the above structure, the n-type SiC film end face is at p After etching the end face of a type Sic film, the end formed by the second etching @. Because of &amp;, only the second etching <short time exposure to ions. As a result, the n-type SiC film including channels, sources, and regions The exposure time of the end face to ions becomes shorter, which has a great influence on the characteristics of the transistor. The problem of deterioration of the surface crystalline layer is difficult to occur. In the above-mentioned horizontal junction type field effect transistor of the present invention, for example, the gate is arranged on the surface of the n-type Sic substrate, and is arranged close to the p-type sic film. With this structure, it can be manufactured by an easy manufacturing method, and a reverse bias can be applied to the junction portion of the P-type semiconductor film and the channel region (n-type semiconductor film) to form an empty layer, thereby realizing an OFF state. The above-mentioned horizontal junction type field-effect transistor of the present invention, wherein the gate is formed in the aforementioned 11-type (: the inside of the substrate is a back-gate structure (please read the precautions on the back before filling this page) # ------- Order

474015 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Disposition of the invention description (10). According to the above-mentioned back gate structure, the signal applied by the gate voltage is transmitted from the front of the channel area to the channel area in a wide range of straight lines, which can improve the switching speed. In addition, the gate system does not need to be arranged at a position far from the channel region, but can be stacked and arranged in the channel region, which can increase the integration of the jFET. Even with a back-gate structure, a negative voltage is applied to the gate at the junction between the n-type SiC substrate and the p-type siC film to form an empty layer. However, as described above, by increasing the impurity concentration on both sides, it is possible to prevent the empty layer from affecting the operation of the JFET. According to the first lateral junction field effect transistor of the present invention, the thickness of the aforementioned channel region is smaller than the width of the empty depletion layer in the n-type SiC film; the n-type

The empty layer system in the SiC film is based on the diffusion potential of the junction portion of the aforementioned n-type SiC film formed on the 1) type 31 (: film and the 匸 -type ^ 匸 film. According to this structure, the gate potential is 0. At this time, a void layer is generated at the junction of the p-type Sic film and the n-type sic film. The front end of the empty layer is wider than the thickness of the channel area. Therefore, the channel area is cut off and the gate voltage is zero. The above-mentioned horizontal junction type field effect transistor of the present invention further includes a low-concentration η-type SiC film, which includes a connection and sandwiched between the p-type Sic film and the n-type SiC film, and has a higher concentration than the channel. ^ -Type impurities with low 11-type impurity concentration in the region. 'With this structure, a horizontal JFET with a high withstand voltage can be obtained, which uses an η-type SiC substrate with a low defect density and does not affect the current in the channel region. Therefore The horizontal calendar can be manufactured at low cost, even if high current flows, the power consumption is reduced and the temperature rise is small. (Please read the precautions on the back before filling this page) -I 1 n II ϋ 1 I 1 —Bi I ϋ ϋ n · 1_— I mMMm · -13-

474015 A7, description of the invention (11), the above-mentioned present invention <i-type horizontal junction type field effect transistor, wherein the above-mentioned region contains η-type impurities having a higher concentration than the impurity concentration of the osmium sinker portion on both sides thereof . According to this structure, an η-type Sic substrate having a low defect density is used to form an empty layer in the channel region ^ by closing the channel cross-section to make a 0ff shape.

It can make Shaofen of the two lacking layers bear the voltage. Therefore, the on-resistance can be reduced without reducing the breakdown voltage of the lateral JFET, and it can be used as a switching element with low loss and high breakdown voltage. The first horizontal junction field effect transistor of the present invention described above, which has a conductive film, is arranged to be connected to the aforementioned channel region. ―According to this structure, the channel area and the conductive film are arranged in parallel with the current flowing in the channel. Therefore, for example, in the case where the resistance of the conductive film is i-order lower than that of the channel region (ordef, the current flowing through the conductive film in the ON state is about 10 times higher than that of the channel region. Therefore, even if there is a deviation in the impurity concentration or a deviation in the thickness of the channel region The effect on the transistor characteristics is also slight, and the deviation of these factors will not cause substantial problems. On the other hand, in the 0FF state, the negative potential (reverse bias) applied to the gate is applied to the area containing the channel. The connection between the ^ -type ^ 匸 film and the underlying p-type SiC film Shao Zhong, on the side of the n-type ye film, the empty layer extends. The two layers are proportional to the above-mentioned reverse bias voltage, and η-type SiC containing the channel region. The impurity concentration of the film and the underlying p-type Sic film is inversely proportional, and it is greatly expanded from the low concentration side. If this empty layer cuts the channel region, the path of the carrier through the channel region is cut. Therefore, it can be easily realized. FF state. The first horizontal junction field-effect transistor of the present invention described above, wherein the length of the conductive film in the channel length direction is shorter than the channel length. -14- ^ The paper size applies the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page) -I ------- Order --------- line! Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474015 Printed A7 by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (12) At least one end of the conductive film is insulated from the side wall, as long as the empty layer cuts off the channel area on the side of TT Hai and Luoba. In the first horizontal junction field-effect transistor of the present invention, the thickness of the channel region is smaller than the width of the empty layer in the n-type Sic film. K is in the n-type Sic film. The empty depletion layer is based on the diffusion potential of the junction of the n-type sic film formed on the 1) type 0 film and the type Sic film. When the gate potential is 0, the p-type SiC film and the 11-type cut off the channel area at the junction between the p-type SiC film and the (-) film depending on the vacant layer generated by the diffusion potential. Therefore, it can be obtained that the π-type mode JFET is normally turned off, which is not necessary. It can be used for the control of the rotating machine and the like due to the failure of the brake circuit. It can also reduce the power consumption in the state of 0, and can avoid the influence of the uneven concentration of impurities in the channel area. The first horizontal joint type of the present invention described above A field effect transistor, in which the aforementioned conductive film is a semiconductor film containing a metal film and a high concentration of impurities. According to the above structure, a low-resistance metal film can be used, and a low-resistance parallel bypass (by_pass) can be easily set in the channel area. ) e Although the metal film can be any material that can be used as an electrode material, it is preferable to use aluminum (A1) or aluminum alloy for the metal film in consideration of the ease of etching and high electrical conductivity. The horizontal joint type field effect transistor, wherein the SiC substrate is a 6H_sic substrate, the p-type Sic film and the 0-type M. The films are all 6H-SiC substrates. According to this structure, a film with excellent crystallinity is laminated There will be no cause Poor crystallinity may cause malfunction due to malfunction, which may result in a decrease in yield. &Quot; The first horizontal junction type field effect transistor of the present invention described above, wherein the aforementioned ρ ------- ^ ------- -^ — (Please read the precautions on the back before filling this page) -15- Printed clothing of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474015 Α7 ---: __Β7 V. Description of the invention (13) SiC film and the aforementioned The n-type SiC films are all 4H-SiC, and the aforementioned p-type SiC films' formed of 4H-SiC are formed on a 6H-SiC substrate via a 4H-SiC buffer layer. Depending on the buffer layer, a crystal with good crystallinity can be obtained. 4H-SiC film, and because 4H-SiC has better electron mobility than 6H-SiC, it can be applied to high-speed switching devices, etc. The first horizontal junction type field-effect transistor of the present invention described above, wherein the aforementioned SiC substrate It is a 4H-SiC substrate, and the p-type siC film and the n-type sic film are both 4H-SiC substrates. According to the above structure, the thin film with good crystallinity is laminated, and there will be no malfunction due to poor crystallinity. Causes a reduction in yield, etc. As mentioned above, 4H-SiC has superior electron mobility than 6H_Sic, etc., and is suitable for high-speed applications. In the above-mentioned first type of horizontal junction field effect transistor of the present invention, the p-type SiC film and the n-type SiC film are both 6H-Sic, and the 6P-type Si is used to form the aforementioned p-type The SiC film is formed on a 4H-SiC substrate through a 6H-Sic buffer layer. Depending on the buffer layer, a 6H_Sic film with good crystallinity can be obtained. Depending on the application, an appropriate crystalline SiC can be used. As described above, the first of the present invention For the horizontal JFET of the form, it is meaningful to make the horizontal type on an n-type Sic substrate. Within the range of the horizontal JFET of the tough form of the present invention, it is assumed that the 11-type and the p-type cannot be replaced. In contrast to the muscle T of the present invention after the second aspect, even if the η-type and the p-type are replaced, the conductivity type of the impurity is expressed as the ^ -type or the second-type. The first conductivity type may be a P-type or an η-type, and the second conductivity type may be an η-type or a ρ-type. -------------- Φ -------- ^ _________ ^ — φ _______._________________ (Please read the notes on the back before filling this page) -16-

474015 A7 B7 V. Description of the invention (14 The second type of horizontally bonded field-prepared SiC substrate of the present invention, the second soil tincture is characterized by: It is formed on the upper and lower surfaces of the aforementioned second conductive SiC film, "7 ^ product", which is formed in the aforementioned first conductive Sic film, and the film is made thinner; the source region · Pre-charged sm γ-domain which is formed by the first conductive type &lt; The first conductive type Sic is formed on the two sides of the channel area; Gate ”: The gate system is formed as a flat region of the second conductivity type SiC. According to this structure, the gate system is formed on the flat region of the second conductivity type sic: the second is to reduce the closed resistance, so that the resistance can be increased. Switching response speed. In addition, even if there is a slight deviation in the position of the closed electrode formation, no problem will occur. This can prevent the reduction of the product rate. Therefore, it can be used for high-speed switching. In the field-effect transistor, the conductive SiC film has a groove-free surface, and the gate is formed by two closed electrodes. It is formed on the flat area of the second conductive type Sic, that is, the flat surface of the second conductive type Sic film. According to this structure, there is no groove between the source, gate, and gate, and the interval can be reduced. The resistance can then increase the switching response speed. Χ, in the manufacturing step, even if the position of the second gate electrode is slightly different, no problem will occur, and the rate of product can be prevented from being reduced. In contrast to the second horizontal joint of the present invention, Field-effect transistor, wherein the aforementioned sic substrate is a second-conductivity-type sic substrate containing a second-conductivity-type impurity; the gate is a back-gate structure, which is provided in the flat region of the aforementioned second-conduction-type Sic-17- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A7

474015 V. Description of the invention (15) The domain is the one provided on the inner surface of the second conductive SiC substrate. According to this structure, the gate electrode is provided on the entire surface of the second conductive type SiC substrate. Therefore, the gate resistance is reduced. As a result, the response speed of switching is increased, and it can be used as a high-speed switching element. Moreover, the formation of a gate electrode becomes easy. The above-mentioned second type of horizontal junction field effect transistor of the present invention further includes a low-concentration first-conduction-type SiC film, which includes a connection sandwiched between the first-conduction-type SiC film and the first-conduction-type SiC film. In the meantime, the first conductive type impurity having a lower concentration than the first conductive type impurity in the channel region. With this structure, the withstand voltage can be improved without affecting the current in the channel area. Therefore, even if a high current flows, the power consumption is small and the temperature does not increase, and it is possible to achieve a high withstand voltage. Therefore, it can be used as a switching element for high voltage and high power. In the above-mentioned second type of horizontal junction field-effect transistor of the present invention, the channel region contains a high concentration of the first conductivity type impurities, the concentration of which is higher than the impurity concentration of the first conductivity type SiC film portion on both sides thereof. .

According to this structure, the empty layer is formed in an OFF state by closing the channel from both sides of the channel region, so that the empty layer partially shares the voltage, and the ON resistance can be reduced without lowering the withstand voltage of the horizontal JFET. Therefore, this horizontal jFET does not consume power even if a large current flows, and it can be used as a switching element with low loss and high withstand voltage. In the above-mentioned second type of horizontal junction field-effect transistor according to the present invention, the through hole region contains a high concentration of the i-th conductivity type impurity, the concentration of which is higher than the impurity concentration of the first conductivity-type SiC film portion on both sides thereof. By. Based on this structure, it is possible to reduce the voltage of the horizontal JFET without greatly reducing the 〇N electrical -18- This paper size applies the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) (Please read the precautions on the back before (Fill in this page) -1 -------- Order ---- · Line 丨-Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 474015 A7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 16 resistance. Therefore, it can be used as a switching element for high voltage and high power. The above-mentioned second type of horizontal junction field effect transistor of the present invention, wherein the thickness of the aforementioned transport region is greater than the thickness of the first conductive siC film. The vacant sound inside the wide-producing small t-th i-conducting Sic film is the empty layer in the i-conducting Sic film; the implanted film and the second conductive type Sic film are formed with the diffusion potential of the first junction portion. According to the above structure, For example, in the channel region (i-conducting second-conducting semiconductor of the lower layer; ^ ^ ^ &lt; * 1000 layers to join the layers again, you can expand the m &quot; usually off &quot; type JFET according to the diffusion potential. For example, the concentration of impurities in the channel region is below 5 × 1 ~ -3. The thickness of the region is 550 nm or less. When the impurity concentration in the channel region is 5 &gt; ^ 〇16 ^ · 3 or less, when the impurity concentration in the second conductivity type Sic film is a general level higher than the concentration, the above is empty. The width of the layer exceeds 55 () nm. Therefore, in the state where the closed voltage is 0, the empty layer extending to the channel region can achieve the state of blocking the channel region. That is, a “normally off” type JFET is not required to be set For the circuit corresponding to the failure of the gate circuit in I, the IFET can be mounted on a rotating machine, etc. In the ON state, as long as a positive potential exceeding the diffusion potential is applied, it can pass through. The diffusion potential generated in the thermal equilibrium state is For the reason of 2 v ~ 3 V, the above-mentioned empty layer is removed by supplying a positive potential of 2V ~ 3V to the gate, and the channel region is turned on. In addition, the above-mentioned applied voltage of 0FF is 0v, which is the same as &quot; In comparison with the application potential of ”FF” type JFET, which is about 22v, in addition to ensuring high-speed switching performance with low loss and high withstand voltage, it can provide JFETs with low power consumption that can be easily mounted on rotating machines. Φ-- ----- ^ --------- ^ — φ. (Please read the precautions on the back before filling this page) -19- 474015 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (17 The second type of horizontal junction field-effect transistor of the present invention described above Where the thickness of the foregoing conductive region is smaller than the width of the empty layer in the first conductive type SiC film; the empty layer in the first conductive type sic film is based on the second conductive earth SiC film and the first conductive type SiC film. Diffusion potential at the junction of the first conductive sic film formed on the second conductive sic film. According to this structure, in the state where the gate voltage is 0, the empty layer extending to the side of the ith conductive type SiC film on the side of the channel area is realized, and the two depleted layers that close the channel area can only block one side of the channel area. It can also block both sides of the channel area. Therefore, the "normally-closed" type JFET can be used in the control of rotating machinery without having to form a complex gate circuit failure to the application mechanism. / The second horizontal field-effect transistor of the present invention, which has a remote film which is arranged to be connected to the surface of the channel region as described above. According to the above structure, the channel region and the conductive film are arranged in parallel with the electric current flowing in the channel. Therefore, for example, when the resistance of the conductive film is lower than that of the channel region, the current flowing on the conductive film in the ON state is about 10 times higher than that of the channel region. Therefore, even if there is unevenness in the impurity concentration or unevenness in the thickness of the channel region, the effect on the transistor characteristics is slight, and the influence of the unevenness of these factors will not cause a problem. On the other hand, in the ⑽ state, depending on the negative potential (reverse bias) applied to the gate, in the junction portion of the conductive semiconductor layer containing the channel region and the second conductive semiconductor layer below it, ..., The empty layer extends to the side of the first conductive semiconductor layer. This empty layer is proportional to the above-mentioned reverse bias voltage, and inversely proportional to the degree of impurities ′ of the i-th conductive layer and the second conductive layer. If this empty layer cuts off the channel area =, the path of the carrier through the channel is cut off. The above conductive film is based on Shuangzhu-20- this paper size 1§ ¥? 5 ^ standard (CNS) A4 size coffee 297 cm) — — — — — — — — I · IIIIIII t IIIIIIIII (Please read the back first Please note this page, please fill in this page) 474015 Printed by A7, Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (18) The first conductive semiconductor layers on both sides of the channel area are not connected to their sides (Wan-type configuration In the case of the above-mentioned cutting, not only the channel region but also the conductive film is cut. Therefore, the OFF state can be easily realized. Furthermore, even if the conductive film is connected to only one side of the first conductive semiconductor layer, In the case of not connecting to the other side, the above-mentioned state can be easily realized, and the resistance can be reduced. The reduction of this resistance can reduce the effect of uneven impurity concentration or uneven thickness of the channel region. When the sides on both sides of the film are each connected to the above-mentioned first conductive semiconductor layer, the resistance can be further reduced, which can be less affected by the above-mentioned unevenness in impurity agronomy or uneven thickness in the channel region. Also, the first 1 The electrical type may be η-type or 卩 -type, and the second conductive type may be P-type or η-type. Also, the semiconductor substrate may be 11-type 8 丨 substrate or ρ-type. The substrate may also be η-type SiC substrate or ρ-type. Sic substrate. In the above-mentioned second type of horizontal junction field effect transistor of the present invention, the length of the conductive film in the channel length direction is shorter than the channel length. With this structure, the two ends of the conductive film and the conductive film can be eliminated. It is difficult to achieve the OFF operation when the side wall is connected. That is, at least one end of the conductive film is insulated from the side wall, as long as the empty layer is cut off the channel area on the insulating side, the OFF state can be achieved. The second type of horizontal junction field effect transistor, wherein the thickness of the aforementioned channel region is smaller than the width of the empty layer in the first conductive sic film; the empty layer in the first conductive SiC film is based on The diffusion potential of the junction portion of the aforementioned% conductivity type SiC film and the second conductivity type Sic film formed on the second conductivity type SiC film. According to the above structure, when the gate potential is 0, the second conductivity type semiconductor film And -21-This paper has used the national standard (CNS) A4 specification (21〇X 297mm) --------------------- Order --------- line (Please read the back first Please fill in this page again) 474015 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7, Description of Invention (19) The junction of the first conductive semiconductor, the empty layer generated by the post and conversion diffusion potential will cut through the path Area. Therefore, it is possible to obtain a pass for each of the old land materials of Pingluo Road (bribery, without the need to implement a closed circuit fault on the temple, you can control the rotator, etc.). (, 0 N state power consumption, can be said immediately ， Research low impact. 'In order to avoid the uneven concentration of impurities in the general domain = the second type of horizontal junction field-effect transistor of this month, in which the above-mentioned conductive-is any of the semiconductor film containing a metal film and a high concentration of impurities- By. According to the above structure, a low-resistance metal film can be used to simply and easily set up a low-resistance parallel bypass (by_pass). As long as the metal film is the electrode material I, it is desirable to consider (A1) or an aluminum alloy in view of the ease of etching and high conductivity. You Ma Ming The second type of horizontal junction field effect transistor of the present invention, wherein the front region and the drain region contain a high concentration of the first conductivity type impurity, and the impurities of the i-th conductivity type sic film portion on both sides of the track region Those with high concentrations will use this structure to reduce ON resistance without reducing the withstand voltage. In addition, g can also be used to form an electrode without the use of ... and eight-layer] structures. Therefore, in the manufacturing steps, there is no need to form a groove in the conclusion. Wu yes, the gate resistance can be suppressed to be very low, and the rise (fall) of switching can be reduced = the second type of horizontal junction field effect transistor of the present invention, in which the impurity concentration of the M 2 conductive SiC film exceeds 10i9 cm · 3 person. According to this structure, even in the case of a single-layer electrode such as ▲ Ni, the contact between the electrodes is also established, and the gate resistance is reduced. Therefore, the upper * lower * areas of B can be shortened when switching, and high-speed response is possible. -22- This paper ruler uses the Chinese National Standard (CNS) A4 specification (21Q χ 297). I ---- I ---- Order ----- I --- Line C Please read the (Please note this page, please fill in this page again) 5. Description of the invention (20) The boundary electrode, 'effect transistor' formed on the second type of horizontal connection region of the present invention, among which the ㈣ formed by the aforementioned source μ, and Yu Ten, two, conductive Sic film or the foregoing and said poles, is composed of metal MV A, and R R &quot; ^ SlC substrate formed on the substrate of the bamboo field, the child metal is a variety of SiC Become an ohm contact. Miscellaneous: structure, electrodes can be formed in simple steps ... Early layer structure of the electrode is not necessary, and it is not necessary to make a two-layer structure = to increase the closed resistance trench, etc., and it can shorten the switching. Upper: Europe: Farming: Impurities The second conductivity type and the first conductivity type _ Feng Ou: Ni and other metals are in contact. ^ The second type of horizontal junction field-effect transistor of the present invention, in which the surfaces other than the source electrode, the non-electrode electrode, and the gate electrode are covered by an insulating film. When exposed on the surface of the device ', surface leakage currents or surface charge formation may cause malfunction. Such a coating of the insulating film can prevent such a problem, and can perform a switching operation stably. The above-mentioned second type of horizontal junction field effect transistor of the present invention, wherein the Sic substrate is a 6H-Sic substrate, the second conductive sic film and the first conductive SiC film are both 6H-SiC. According to the above-mentioned structure, a thin film having good crystallinity is laminated, and a failure in yield caused by malfunction due to poor crystallinity will not occur. In the above-mentioned second type of horizontal junction field effect transistor of the present invention, the second conductive SiC film and the first conductive sic film are both 4H-SiC, and the second conductive type formed of 4H-SiC. A sic film is formed on a 6H-SiC substrate through a 4H-SiC buffer layer. 474015 Printed by A7 B7, Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs. 5. Description of the invention (21) 4H_siC film with good crystallinity can be obtained by the buffer layer, and it is applicable because the electron mobility of 4H_siC is better than 6H-SiC. For high-speed switching components. In the second lateral junction field effect transistor of the present invention, the SiC substrate is a 4H-SiC substrate, and the second conductive sic film and the i-th conductive SiC film are both 4H-SiC. According to the above-mentioned structure, a thin film having good crystallinity is laminated, and a defect such as a reduction in yield due to malfunction due to poor crystallinity, etc., does not occur. In addition, as described above, 4H-SiC has a higher electron mobility than 6H-SiC and can be applied to high-speed switching devices and the like. '' The second lateral junction field effect transistor of the present invention described above, wherein the second conductive SiC film and the first conductive sic film are both 6H-SiC, and the second conductive made of 6H-SiC A type siC film is formed on a 4H-SiC substrate via a 6H-SiC buffer layer. Depending on the buffer layer, a 6H-SiC film with good crystallinity can be obtained, and an appropriate crystalline SiC can be used depending on the application. The third lateral junction field-effect transistor of the present invention described above is characterized by having a SiC substrate and a gate electrode; the first! The siC film is formed on the aforementioned SiC substrate, and the second siC film of the first conductivity type is formed on the aforementioned first SiC film, and includes a thin channel region and a The channel area or the source and the area sandwiched from both sides; the above-mentioned 1 S i C film is located at the lower part of the channel area, has the same width as the channel area, and is shorter than the channel area. The length of the region; composed of the following regions: high-concentration impurity region, the second conductivity-type impurity concentration is higher than the first conductivity-type impurity concentration of the aforementioned channel region; and high resistance AW .------- ^- -------- (Please read the notes on the back before filling this page) -24- 474015 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Invention Description (22) Area: f is at the high level Those with high resistance outside the concentration impurity region.

The 3 ′ 2′-C hybrid region is formed between the channel region and the channel region, forming a high potential i I, _ A U for the carrier, but the carrier invades the high region according to the channel effect. Carriers that invade high-concentration impurity regions are combined with the high-concentration #shell to reduce and become an ineffective shallow leakage current, which results in a decrease in the magnification. The 2% supply leakage has a flow that increases with forward bias or increases with high temperature. The tendency. The length of the high-concentration impurity region is made shorter than the channel region, and the cross-sectional area of the thickness is smaller, which can increase the resistance in the thickness direction of the high-concentration impurity region. In addition, although the cross-sectional area in the thickness direction of the i-th Slc film outside the high-concentration impurity region is large, it is made into a high-resistance region: by providing this high-resistance region and not providing it, the whole is made. Compared with the case of the concentration impurity region, the leakage current from the source and carrier regions to the first Sic film can be reduced. That is, by increasing the resistance of the first Sic film connected to the source region and the channel region as a whole, leakage current from the source region or the channel region to the i-th Sic film can be suppressed in the ON state. Therefore, the current of Dashafen passes through the channel area and flows from the source area to the drain area. On the other hand, the OFF state can be achieved by applying a reverse bias to the junction surface of the above-mentioned high-concentration impurity region and the channel region by cutting off the empty layer extending to the channel region. Here, the length direction of the channel region is set to a length, the direction perpendicular to the lamination plane is set to a thickness direction, and the direction perpendicular to the two is set to a width direction of the horizontal JFET. Also, the above-mentioned gate electrode may be placed inside the SiC substrate, or may be provided on the Sic substrate on both sides of the first SiC film. In order for the Sic substrate to be in ohmic contact with the gate electrode, it is desirable to contain a high concentration of impurities regardless of the first or second conductivity type. -25- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) i ------- Order ------ ---line! 474015 A7 _, description of the invention (23) / The growth of the empty layer to the channel region when the reverse bias is applied is the ratio of the 24th electrical type impurity concentration in the high-quality region to the channel-type impurity concentration in the channel region. The bigger the easier it is. Therefore, although the channel region and the reverse conductivity type impurities are set to have a higher concentration than the channel region, the high-concentration impurity =: domain is required, but the cross-sectional area corresponding to the thickness direction must be made small and the resistance &amp; Make the length shorter than the channel area. The shorter the length of the high-concentration impurity region f, the smaller the cross-sectional area corresponding to the thickness direction. By making a person] 3, '# 1 # m or less, the inflow The gate current is suppressed to the extent that it causes practical problems. If the length is too short, the empty layer will not easily pass through the channel area, and even if the channel area is cut off, the carrier will pass through the layer due to the channel function, so it can be made possible. The length of the 0FF state is achieved by the formation of the empty layer, so that leakage from the source and channel regions to the first! SiCM can prevent the reduction of the magnification. 1 The third horizontal junction type field effect transistor of the present invention is manufactured, which The second region contains the first conductivity type impurity, whose concentration is lower than that of the aforementioned first M conductivity type impurity. The structure described above is equivalent to the following four structures. The channel region and the high resistance region are equivalent to The case where the plate (closed) is ρ type; ( b) Channel area and high resistance ": η :, the case where the plate (between) is η-type; (C) the case where the channel area and the high-resistance E-domain ⑽ type, and the substrate (gate) is„ type; (d resistance area It is a type with the substrate (on) being ㈣. For these reasons: the same as the two and ⑷ <case ', that is, in the high-resistance area and the substrate are the same conductivity type, the joint between the high-resistance area and the substrate does not Will produce empty layers: L___ _ 26-Λ Zhang scale applies Chinese National Standard (CNS) A4 specification ⑽χ 297 public love -------------- Φ ------- order- ------- Line! {Please read the precautions on the back before filling this page) 474015 A7 V. Description of the invention (24 High resistance caused by low impurity concentration to suppress the above-mentioned leakage current. Another-Wan®, in The case of ⑷ and ⑷, that is, the case where the high resistance region and the substrate are of different conductivity types are as follows. In the case of ⑷, a positive potential is applied to the gate at 0n. In the case of ⑷, at 0N Self-potential is applied to the gate. Therefore, in the case of ⑷ and ⑷, the substrate is forward biased with the high-resistance layer in the Sic film, and the empty layer * will expand. Therefore, in the case of ⑷ and ⑷, low impurity Due to the high resistance layer, the above-mentioned leakage current can be suppressed. In any of the above-mentioned cases, most of the current in the 流 state flows from the source region to the drain region through the channel region. Therefore, the self-source and channel region side I / iC is suppressed. The ineffective current leaked from the film can prevent the reduction of ytterbium magnification. The above-mentioned horizontal type, Nandian, low concentration of impurity concentration in the area (I hope it is ixiqi7⑽ · 3 by y by the first of the above high-resistance area! Conductive type or The low concentration of the second conductivity type is set below IX 10 &quot; cm-3, which can make the resistance of the empty layer formation very high, or it can make the resistance very high without forming the empty layer. The present invention (third type A field-effect transistor of the type junction type = the domain contains a second conductivity type impurity whose concentration 値 is lower than the 前述 1 conductivity type impurity concentration of the aforementioned two c films. The resistance structure in the situation is equivalent to the following four cases. ⑷ channel is η-type, high resistance nine 'horse P-type' substrate (closed) is ρ-type; (f) channel is η-type, area is P-type, substrate (gate) is „type; (g) Channels:: When the area is η-type substrate (open ... type; (h) When the channel is p-type-Inclusion area is η-type, substrate (gate type. Among them, ⑷ and (g) < The situation is that in the high-resistance area and the substrate are the same state, there will be no empty layer at the junction between the high-resistance area and the substrate, according to :: L_______ -27- This paper is applicable to the printing of the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System 474015 V. Description of the invention (25) High resistance caused by concentration impurities can suppress sj and suppress the above leakage current.-Wan surface, in the case of (f) and (h) (high resistance, wide state 'on the substrate and high two = Mouth punched open> into the empty layer. That is, Yu Buzhuwen ---, h / brother, the substrate is η-type, and ηρ- junction with the high lightning resistance region; (h) 1,

PiL F ^ ^ ^ r input, (h case, the substrate is P-type, and ηρ · joint with the high-resistance £ domain; in the case of ⑴1 愔, 、, 兄, 兄 1, when the conductive type is η-type, ON State, apply zero or a little positive potential to the gate. And the conductivity type is p-type), the saki state applies a closed or a little negative potential to the closed pole. At this time, 上 上 nn • 拉 人 &amp;# τ 野Any of the above ηP junctions and ρη-junctions are reverse biased to produce peak life. A ^ 2 "layer. In addition to the high fp caused by low impurity concentration and the 'empty layer according to this' The resistance of the path from the straight channel region to the 1st sic film becomes very high. Therefore, the ineffective current leaking from the source and the channel region to the i-th Sic film is suppressed to prevent the reduction of the magnification. The third aspect of the invention described above The horizontal junction type field effect transistor, in which the aforementioned high-resistance region is composed of two layers of the first layer and the second layer; the first layer contains the first conductive type impurity, and its concentration is higher than that of the second sic The lower concentration of the i-conductivity type hybrid rabbit in the film; the second layer contains the first conductivity-type impurity, the concentration of which is higher than that of the second SiC film The lower one of the first conductivity type impurity concentration. The two-layer structure is a two-layer structure of (Α) ρ · (upper layer) / n- (lower layer), or (B) η · (upper layer) / p- ( In the case of the two-layer structure of (A), in the On state, a reverse bias is applied between the upper layer and the lower layer to form an empty layer. The formation of this empty layer is related to the conductivity type of the channel region and The conductivity type of the SiC substrate has nothing to do with it. -28- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) AW .------- ^ --------- ^ — (Please read the precautions on the back before filling this page) 474015 A7 V. Description of the invention (26 in (B) &lt; 2-layer structure, when the conductivity type of the sic substrate is n-type, in the ON state, in the A reverse bias is applied to the junction surface of the P- (lower layer) and the n-type SiC substrate to generate an empty layer. In the above case, the resistance becomes very high due to the formation of the empty layer. The formation of this empty layer and the conductive type of the channel region Regardless, in the case of (B) above, when the conductivity type of the SiC substrate is p-type, although no empty layer is formed, the impurity concentration of the upper layer and the lower layer of the second layer structure is high. Because the resistance is low, the horizontal type hopes that the low concentration of the impurity concentration in the high-resistance region should be less than 1/10 cm. By making the i-conductivity type or the second-conductivity type in the high-resistance area The low concentration of impurities 値 is less than χχι〇7ΐ3, which can make the resistance caused by the formation of the empty layer very high, or the resistance can be made very high without forming the empty layer. All ensure the resistance of the 鬲, suppress the invalid current from the source, pass through the C area or the side 1 SiC film leakage, can prevent the reduction of the amplification factor 0 j S The crystal, in which the aforementioned high-trace impurity region and the aforementioned channel region, are formed in a junction portion of the two, and are formed by cutting the aforementioned channel region in accordance with an empty layer of a diffusion potential. The structure can perform the "normal closing" action. That is, when the closed potential pair = (the suspension potential is the ground potential) is. When the 'diffusion potential', the channel region is directly extended by the junction surface of the concentration impurity region. It is cut off. Therefore, the state of the gate: 0 becomes the 0FF state. To achieve the 0ν state, it is only necessary to violate the positive potential of Gartner. At the diffusion potential, the empty layer is as described above. The scale is applicable to the Chinese National Standard (CNS) A4 specification (_21 () χ 297 Gong Chuding (please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs I — — — — — — — --- — — — — — — ^ I ---------------------- 474015 A7 B7 V. Description of invention (27) In the case of growth, proceed with & quot "Normally open" action. That is, at 0, the carrier in the channel region moves without restraint: the potential horse state 'applies a negative potential to the gate, applies a high reverse bias, and enters the second C as an fFET to be mounted on the rotation In the case of the machine, even if the peripheral circuit is open = it is supplied to the rotating machine. It must be installed to prevent danger. The control circuit responding to this situation. As mentioned above, when borrowing, dysfunctional | μ, +, 4, seat 丨 + * Ding off when the action is closed, the above control circuit is not required. Also, the "normal time off" action is performed. Or open at the time of the operation, depending on the impurity concentration ratio of the channel region and the high-concentration impurity region, the length of the high-concentration impurity region, and the thickness of the channel region, etc.-and set it again. As above, the high-concentration impurity region The larger the ratio of the second conductivity type impurity concentration to the channel 1first conductivity type impurity concentration, the easier it is to perform the "normally off" action. In this description, the "normally off" is not specified otherwise. In the case,

It is assumed to be "normally open". Xiao Fanbei J. The above-mentioned third type of horizontal junction field effect transistor of the present invention, wherein the above-mentioned pass region contains a high concentration of the first conductive type impurity, which is a portion of the first conductive type Sic film having a concentration ratio on both sides of 眞High impurity concentration. According to this structure, the cross section of the channel is closed from both sides of the channel area to form an empty layer to be in an OFF state, so that the empty layer partly shares the voltage, which will not reduce the withstand voltage of the horizontal JFET, but can reduce the 0N resistance. . Therefore, this horizontal JFET does not consume power even if a large current flows, and it can be used as a switching element with low loss and withstand voltage. The third type of horizontal junction field effect transistor of the present invention has a conductive film &apos; which is arranged on the surface of the channel region. -According to the above structure, even if the impurity concentration in the channel area is uneven or the channel area is -30 M ’s scale, the Chinese National Standard (CNS) A4 specification (210 X 297 public love) is applied ------- ^ --- ------ (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 474015 A7 B7 V. Description of the invention (28) The thickness of 0's has an effect on the electrical characteristics However, the influence of these factors will not cause any substantial problems. On the other hand, in the case of Yu Zhe, in the case where the above conductive film is configured to keep the first conductive type + f body layer on both sides of the channel area not connected to its side, according to the above-mentioned knife fe / f "only The conductive film is also cut off in the through area. Thus, the OFF state can be easily realized. In the above-mentioned present invention <the third type of horizontal junction field-effect transistor, the length of the conductive film in the direction of the through-hole length is shorter than the channel length. According to this structure, at least the end of the conductive film is insulated from the side wall, so long as the empty layer cuts the channel area on its insulating side, it can be made lumpy. The third type of horizontal junction field-effect transistor of the present invention, wherein the above-mentioned pass area <thickness' is smaller than the width of the empty layer in the i-type conductive Sic film; The empty layer in the film is based on the aforementioned second conductive SiC film and the second conductive Sic film formed on the aforementioned! Diffusion potential at the junction of a conductive SiC film. According to the above structure of the line, it is possible to get "normally off," and without having to implement the brake circuit failure: strategy, etc., 'can be used for the control of rotating machines, etc. ... can reduce ⑽ power consumption' and avoid impurity concentration in the channel area. In the third horizontal junction type field effect transistor of the present invention, the conductive film is any one of a metal film and a semiconductor film having a high concentration of impurities. According to the above structure, it can use a low-resistance metal film, and simply set a low-resistance parallel bypass (by_pass) in the channel region. Although the metal film only needs to be an electrode material, in consideration of the ease of etching and high electrical conductivity, it is desirable to use -31-National Standard (CNS) A4 Standard (this standard)

The inscription (A1) or aluminum alloy is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Brief Description of the Drawings Fig. 1 is a cross-sectional view of a horizontal JFET according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view of a horizontal JFET according to a second embodiment of the present invention. 3 is a cross-sectional view of a horizontal JFET according to a third embodiment of the present invention. Fig. 4 is a cross-sectional view of a comparative JFET corresponding to a horizontal JFET according to a third embodiment of the present invention. 5 is a cross-sectional view of another horizontal JFET according to the third embodiment of the present invention. 6 is a cross-sectional view of a horizontal JFET according to a fourth embodiment of the present invention. FIG. 7 is a cross-sectional view of a stage in which an n + Sic film is formed in the intermediate manufacturing stage of the horizontal JFET of FIG. FIG. 8 is a cross-sectional view of a stage in which a channel region is formed by rie after the stage in FIG. 7. FIG. 9 is a cross-sectional view of a stage where a Ni film is formed after the stage of FIG. 8 and an electrode is formed. FIG. 10 is a cross-sectional view of a horizontal JFET according to a fifth embodiment of the present invention. 11 is a cross-sectional view of a horizontal JFET according to a sixth embodiment of the present invention. FIG. 12 is a cross-sectional view of a stage in which an n + Sic film is formed during the intermediate fabrication stage of the horizontal jFET of FIG. 11 and patterned according to RIE. Fig. 13 is a cross-sectional view of a stage where a channel region is formed by RIE after the stage of Fig. 12; FIG. 14 is a cross-sectional view of a stage where a Ni film is formed after the stage of FIG. 13 and an electrode is formed. FIG. 15 is a cross-sectional view of a horizontal JFET according to a seventh embodiment of the present invention. 16 is a cross-sectional view of a horizontal JFET according to an eighth embodiment of the present invention. Figure 17 shows the formation of n + Sic in the middle production stage of the horizontal JFET of Figure 16 -32- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------- ------------- Order --------- Line (Please read the precautions on the back before filling this page) 474015 A7

V. Description of the invention (30) The section of the stage where the film is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and patterned according to RIE. FIG. 18 is a cross-sectional view of a stage in which a channel region is formed by RIE and impurities and impurities are ion-implanted after the stage in FIG. 17. FIG. 19 is a cross-sectional view of a stage where a Ni film is formed after the stage of FIG. 18 and an electrode is formed. FIG. 20 is a cross-sectional view of a horizontal JFET according to a ninth embodiment of the present invention. Figure 21 is an embodiment of the present invention! Cross section of the horizontal jFET. Fig. 22 is a graph showing the relationship between the element breakdown voltage and w. Figure 23 is the embodiment of the present invention! !! A cross-sectional view of the horizontal jFet. 24 is a cross-sectional view of a horizontal JFET according to Embodiment 12 of the present invention. Fig. 25 is a schematic diagram illustrating the OFF state in the horizontal JFET of Fig. 24; Fig. 26 is a cross-sectional view of a horizontal JFET according to Embodiment 13 of the present invention. Fig. 27 is a sectional view of a horizontal JFET according to a fourteenth embodiment of the present invention. Fig. 28 is a sectional view of a horizontal JFET according to a fifteenth embodiment of the present invention. Fig. 29 is a sectional view of a horizontal JFET according to a sixteenth embodiment of the present invention. FIG. 30 is a cross-sectional view of a horizontal JFET according to Embodiment 17 of the present invention. FIG. 31 is a cross-sectional view of a horizontal JFET according to Embodiment 18 of the present invention. Fig. 32 is a cross-sectional view of a horizontal JFET according to a nineteenth embodiment of the present invention. FIG. 33 is a cross-sectional view of a horizontal JFET according to Embodiment 20 of the present invention. Fig. 34 is a sectional view of a conventional horizontal jfet. FIG. 35 is a cross-sectional view of another conventional horizontal jFET. Fig. 36 is a cross-sectional view of a stage of forming an n-channel layer in the intermediate fabrication stage of the horizontal JFET of Fig. 35; -33- ----- 1 ------— 11 ----- Order ------- line— (Please read the precautions on the back before filling this page) Applicable to China National Standard (CNS) A4 specification ⑽χ 297) 474015 Printed by A7 B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (31) That is, a cross-sectional view of the stage of the N 丨 film. FIG. 38 is a cross-sectional view of a stage in which a second layer, that is, an a film, of a two-layer electrode is formed after the stage in FIG. 37. FIG. Fig. 39 is a sectional view of a stage in which a groove is provided between the gate region and the central portion after the stage of Fig. 38. The best mode for carrying out the invention is described below with reference to the drawings. (Embodiment 1) FIG. 1 is a cross-sectional view of a horizontal JFET according to Embodiment 1 of the present invention. A p-type Sic film 2 is formed on the n-type SiC substrate In, and an 11-type ^ (:: film 3 is formed thereon, and the portion of the channel region 11 is reduced in thickness. In addition, the channel region 11 is sandwiched. An n + -type impurity layer is formed on the n-type SiC film, and becomes a source region 22 and a drain region 23. A source electrode 12 connected to the source region 22 and a drain electrode 13 connected to the drain region 2 3 are each formed. Ohmic contact. In this embodiment, the gate electrode 14 is formed by sandwiching the source and drain regions 2 2 and 2 3 when viewed in a straight plane. The feature of the above structure 4 is the following laminated structure · n-type SiC substrate / ( L) Laminated junction / P-type SiC film / (G) Gate junction / n-type Sic film with channel area. Port (A) π normally open "type jFET adopts the above-mentioned structure, which can be large with high yield. Electricity is switched at high speed. On the other hand, (B) is normally closed, and the type jfet is based on the diffusion potential of the pn junction above. To this end, for example, the n-type impurity concentration of the n-type SiC film 3 including the channel region is set to 1 × 10 μ6 cm · 3, and the thickness a of the LiL region is not set to 5000 nm or less. This "normally off" -34- / yz X. υ 1 FREE V-\ 0 -------- t --------- ^ — φ ------- ^ --- 1 ------------- (Please read the notes on the back before filling this page) 474015 A7

The operation is performed in the following manner. In the case of 乂 B, that is, when the gate potential is 0, a diffusion voltage is applied to the gate junction to produce a red 1 ^ quality: fR τ v process &lt; layer, at this junction, the P-type SiC film is miscellaneous. The P-depleted layer when the reverse bias is applied to the (L) laminated junction is set to be relatively separated. Yang 丄 ^ ^ ^ The selected ancient, Shi / r,, δ is n-type miscellaneous / Chen and I again asked the channel area, the empty layer extends to the channel area side, and to the ρ type

Sic membrane side extension is small. Due to the adjustment of the impurity concentration by m., It is possible to cut off only the channel region by 2 layers. Thus, an OFF state can be achieved. \) In the h state of ON, that is, when the brake and voltage are positive, (G) the junction of the brake is biased with *, not &quot; ^ &lt; m —, the main unit generates an empty layer, and realizes the ON state. . When the closed-electrode potential becomes positive, a reverse bias voltage is applied to the (L) laminated junction. However, by making the p-type impurity concentration of the p-type Sic film and the n-type impurity concentration of the 11-type 8110 substrate higher, the width of the empty layer is small, and the current will flow according to the channel effect. The above-mentioned high-concentration impurity concentration is, for example, a type 11 with (: n-type impurity concentration of the substrate In being set to about 1 × 1019em · 3, and also 1) type ^ (: p-type impurity negative concentration of the film is about 1 × l 〇l9 cm-3. As the impurity concentration is set higher as described above, the withstand voltage of the joint may decrease, and the withstand voltage may disappear and current may flow. Therefore, the empty layer in the joint is almost empty. It does not affect the ON-FF operation of the JFET. According to the structure of the horizontal JFET of the first embodiment described above, a high-mobility electron is used as a carrier in the channel region, and an n-type ye substrate having a low defect density can be used to produce a Nanliang product Rate, high power, and high switching speed. The yield rate of the JFET in the above embodiment at the trial stage is as follows. For comparison, the yield rate of the conventional JFET is also shown. -35 This paper standard applies Chinese national standards (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 I— I nn I ϋ ϋ Μ · — 1 i_l ϋ el -Line ----------------------- 474015 Ministry of Economic Affairs A7 B7 printed by the production bureau employee consumer cooperative V. Description of the invention (33) Examples of the present invention: Fabricated on n-type SiC substrate (Embodiment 1): Yield rate 90% Known example: Fabricated on p-type SiC substrate: Yield rate 10% According to the above result, compared with the conventional example, it can be seen that the yield rate of this embodiment is greatly improved. (Embodiment 2) FIG. 2 is a cross-sectional view of a horizontal jFEt according to Embodiment 2 of the present invention. In the form, the gates 14 are arranged on the inner side of the n-type SiC substrate 1 η, which is very different from the JFET of the first embodiment. The operations or functions related to other parts are the same as those of the first embodiment. The same. In this embodiment, the gate electrode 14 is arranged in the n-type SiC substrate, and the channel region 11 can be seen straight and wide from the gate electrode 14 from the front side. Therefore, it is applied to the gate Because the signal of the pole is transmitted to the channel area in a straight line, it can be turned on and off at high speed. That is, a high-speed switching element can be realized. In addition, compared with the gate arrangement of the first embodiment, the size of the plane is implemented. The JFET of Form 2 is small and has a bulk configuration. Therefore (Embodiment 3) FIG. 3 is a cross-sectional view of a horizontal JFET according to a third embodiment of the present invention. FIG. 4 is a cross-sectional view of a JFET for comparison. In this embodiment The end face 31 of the p-type SiC film 2 and the end face 32 of the upper n-type SiC film 3 are not offset, and in plan view, the former is located on the inner side of the latter. In this regard, as shown in FIG. 4 The end face 30 is formed so that both end faces are aligned. In the case of the end face 30, when the RIE is etched, the end face 30 is exposed to ions during the RIE period, and the crystal may be damaged. In this regard, in the case of the end surface structure shown in FIG. 3, although the end surface of the η-type SiC film is etched by the first etching A, but according to the second (please read the precautions on the back before filling this page) * ^ -· Ϋ HI ϋ ϋ I .1 &gt; ϋ ^ ϋ I ϋ I .1 I ϋ ϋ ϋ ϋ nn I ϋ ϋ n ϋ I n I nnn ϋ l I ϋ ϋ _ • 36 ·

474015 A7 B7 V. Description of the invention (34) Secondly, the inner part of B is etched and exposed, and this part is only exposed to ions for a short time. Therefore, the possibility that the crystal near the end face 32 is damaged by ions becomes very low. Therefore, by a simple method, a JFET having excellent transistor characteristics in addition to ensuring a high yield can be obtained. The JFET shown in Fig. 3 has a back-gate structure. However, as shown in Fig. 5, the JFET having a structure in which gates 14 are arranged laterally on a channel is also a powerful structure of this embodiment. That is, by using the structure shown in Fig. 5, a jFET with a high yield can be obtained without damaging the surface crystals at the end portions. (Embodiment 4) FIG. 6 is a cross-sectional view Q of a horizontal jFET according to Embodiment 4. In FIG. 6, a p + -type Sic film 2 is formed on a substrate 1. As shown in FIG. The Sic substrate type 81 (:: film 2 may be 6H or 4H. On the p + type Sic film 2 described above, nS} Sic ^ 3 is formed, which forms a channel region. The channel region u is a type 11 3 film 3 The thickness is made thinner and formed in the central part. The source 丨 2 and the drain 丨 3 are viewed from the channel area, and each is formed at 11+ to (:: the source area of the film 4 and The region of the p + -type SiC film 2 is not covered by the upper layer 11 type 81 (: film 3 is covered, on a wide plane which is not covered, to sandwich the source formed in the middle: above The electrodes 12 and drain 13 form two gates M. That is, the conducting circuit between the source, the drain region, and the gate does not pass through a wide section such as a trench on the way. The n-type impurity concentration in the source region and the no-region is high due to the ohmic contact with Ni and the like. The impurity concentration in each region is preferably as follows. Cm · Binding channel region 11 and n-type SiC film 3 ·· n-type impurity 2χι〇ΐ7 cm-3 source, drain region (n + type SiC film) 4 ·· n-type impurity &gt; 1χι〇19 -37- This paper size applies Chinese National Standard (CNS) A4 regulations; j each 210 X 297 Public-474015 A7 B7 V. Description of the invention (35) P + -type SiC film 2: p-type impurity &gt; lxl019cm-3 In addition, the thickness and length of the transit area a, L ·, perpendicular to the paper surface The width W can be determined according to the size and size of the το element. Source source 2 and source region 2 2, and pole 13 and drain region 23, and gate electrode 14 and gate region 1 &gt; + type with (:: film 2, both Because of the connection between the region where the impurity concentration exceeds the erbium concentration of lx10i9 cm-3 and the metal film, ohmic contact can be formed by using, for example, the material as the metal film. When the state is OFF, the gate electrode 4 is applied. With reverse bias, the empty layer is stretched toward the channel area from the pn junction of 110,000 in the channel area, so that the cross-section of the channel area is closed. Generally, the gate is from the gate to the lower end of the empty layer. The resistance Rg, the capacitance of the empty layer can be regarded as the gate capacitance Cg. To make a 0N state, just remove the reverse bias to remove the empty layer. In the ON state, the carrier passes from the source through the channel region to the drain When turning on and off repeatedly, it can be regarded as the above-mentioned gate resistance rule § and gate capacitance C g The rise (fall) time is directly proportional to the time constant RgCg of the transition phenomenon of this circuit. Therefore, by reducing the gate resistance R g, the rise (fall) time of the switching can be shortened. By using the horizontal JFET of FIG. 6 It will not increase the resistance, which can increase the withstand voltage, shorten the switching response time, and provide a stable JFET. The manufacturing steps of this JFET are simple and easy, and the problem of reduced yield is rare, so it can be cheap. Manufacturing. (Example corresponding to Embodiment 4) A horizontal jFET having a structure shown in FIG. 6 was manufactured. Channel area 1 1 series setting: channel length L is 10 scales, channel thickness &amp; is 3,001,111, and -38-This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) (Please (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * · &gt; -I -------- Order ----- ----- Line --- ------------------- 474015 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (36) The width of the vertical channel on the low side is 700 &quot; m. Figs. Corresponding to Figs. 36 to 39 for explaining a conventional horizontal JFET manufacturing method are shown in Figs. 7 to 9 for explaining the steps of the present invention. First, a p + -type SiC film having a thickness of 1 is formed on a p-type SiC substrate, and then an n-type SiC film is formed. After the n + -type siC is formed thereon, etching is performed according to RIE to pattern the region containing the source and drain regions (FIG. 7). Secondly, a trench is etched in the central portion of the portion containing the source and drain regions by RIE to form a structure that separates the source region 22 and the non-region 23 (Fig. 8). Secondly, a gate electrode is provided on the p + SiC film 2, and a source region 12 and a drain region 13 are provided in the source region 22 and the drain region 23 of the a + impurity region, respectively (FIG. 9). Thereafter, there is no etching step for forming a groove in the p + SiC film 2. As shown in FIG. 3, the horizontal JFET of the comparative example does not increase the impurity concentration in the source region and the drain region, but maintains the original 2 × 1017 cm-3 concentration of the η-type SiC film 3. Also, will Figure 35? A horizontal JFET having a trench depth of 0.7 quotm for a type SiC film and a thickness of 0.3 p remaining p-type Sic at the bottom was also used as a comparative example. For both horizontal JFETs, the rise (fall) time of the switch was measured. The rise time of the comparative example is set to 1, and the normalized measurement results are shown in Table ^. Table 1 Rise (fall) ratio of horizontal JFET structure (1 with grooves) No groove (Example of the present invention) 0.33 Structure (Comparative example) 1 As shown in Table 1, p-type SiC film 2 is made without grooves The smooth plane with gate 14 formed on it can shorten the switching rise (fall) time to 1/3 to 39- (Please read the precautions on the back before filling this page)

474015 A7 B7 V. Description of the invention (37 is a horizontal JFET with high withstand voltage, low ON resistance, (Embodiment 5), and can be switched at a high speed. II. 10: Inventive embodiment, horizontal JFET &amp; Sectional view. The poles of the gate electrode = P are very similar to the horizontal plate τ shown in Fig. 6. In Fig. 10, the characteristic is that the closed electrode 14 is straddled over the inner surface of the p-type SiC substrate i: According to the structure of FIG. 10, the voltage application method can be the same as that shown in FIG. 6, which shows ON-OFF complaints. Furthermore, the idle resistance ^ is made lower, so that the rise (fall) of the switching can be shortened. (Embodiment 6) Fig. 11 is a cross-sectional view of a horizontal JFETw according to Embodiment 6. In Fig. 丨, a p + type Sic film 2 is formed on a SiC substrate i. A low-concentration layer 7 containing n-type impurities having a lower concentration than the channel region is interposed on the type sinker 2 so that the ^ -type SiC film 3 and the P + -type SiC film 2 are connected to each other along the place, The channel region U is formed in the central portion on the aforementioned low-concentration layer 7. The source electrode 12 and the drain electrode 13 are viewed from the channel region and are formed on both sides of the channel. The source and drain regions of the n + SiC film 4. In addition, the ends of the p + -type sic film 2 are not covered by the upper-layer n-type Sic film 3, and the uncovered wide plane is used to The source formed above the center and the square sandwiched by the drain 13 form two gates 14. That is, the source and the conducting circuit between the area and the gate are not narrowed by trenches or the like on the way A wide cross section is used. The impurity concentration in each region is preferably the following. Channel region 11: n-type impurity 2xi017cm-3 source, no region (n-type SiC film) 4: n-type impurity> ixi〇i9cm_3 -40- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, * nn ϋ n ϋ I n I ϋ II ϋ nnnn I ϋ ϋ ϋ I n ϋ ϋ n ϋ ϋ n. 474015 Printed clothing A7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (S8) Low concentration layer 7: η Type impurity &lt; 2χΐ〇ΐ70〇ηη3 P + type SiC film 2: p-type impurity, thickness of channel region a The length L and the width w in the direction perpendicular to the paper surface can be determined according to the size and size of the element. In addition, the surface is covered by a protective film 5 made of SiO2 except for the parts of the electrodes 12, 13, and 14. Source 1 2 and source area 2 2. Drain 1 3 and drain area 2 3. Gate 丨 4 and P + type SiC film 2 in the gate area, all of which have an impurity concentration exceeding! For the connection between the high-concentration area of x 1019 cm-3 and the metal film, for example, Ni is used as the metal film and heat treatment is performed to form an ohmic contact. In FIG. 11, a forward bias is applied to the gate in the ON state to form an empty layer in the channel region 11. Therefore, carriers flow on the path through the source region, the channel region, and the drain region. There is no special #ON resistor in this path, it will not consume power. When a reverse bias is applied to the gate electrode 14, the empty layer extends from the pn junction below the channel region to the channel region, thereby achieving an OFF state that almost completely blocks the channel portion. If the present invention is not provided with a groove in the p-type Sic film 2,

Because the gate resistance is small, in this 0N-0FF, the rise (fall time is shortened. B. By using the structure of the horizontal JFET in Fig. 11, it does not increase the 0N resistance, which can improve the withstand voltage and shorten the switching response. A stable JFET can be provided in time. This JFET has simple manufacturing steps and low yield, and can be manufactured at low cost because it has fewer members. &Amp; (Example 1 corresponding to Embodiment 6) Manufacturing and use The horizontal jFET with the structure shown in Fig. 11. The structure of each area except the channel area ii and the low-concentration layer 7 is as described above. Channel-41-This paper size applies to China Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) · I ------ Order · ----- I--. 474015 A7

V. Description of the invention (39) The area 11 is set as follows: the channel length L is 10 / im, the channel thickness a is 300 nm (0.3 &quot; m), and the channel width perpendicular to the paper surface is a few "melons." Let the impurity concentration of the low-concentration layer (η-heterogeneous layer) be 1 × 10 15 cm-3 and the film thickness be 0 / im. The present invention corresponds to FIG. 36 to FIG. 39 illustrating a method for manufacturing a conventional horizontal JFET. The manufacturing method of the inspection type JFET is shown in Fig. 12 to Fig. 14. First, a p + -type SiC film 2 is formed on a p-type SiC substrate 1, and then a low-concentration type 11 is formed with (: film 7 and an n-type is formed thereon). sic film 3. After the n + -type siC film 4 is formed thereon, the area containing the source and drain regions is patterned by RIE (Figure 12). Second, the central portion of the part containing the source and drain regions is patterned. According to RIE, a trench is etched to form a structure that separates the source region 22 from the drain region 23 (FIG. 13). Secondly, a gate electrode is provided on the p + sic film 2 and each source region is an impurity region. 2 2 and the region 2 3 are provided with the source 12 and the region 1 3 (FIG. 14). After that, there is no step of setting a groove in the p + Sic film 2. For comparison, FIG. 3 is also made. Horizontal jfet showing structure The source region and the drain region of the horizontal JFET of the comparative example did not particularly increase the impurity concentration, and maintained the η-type sic film 3 concentration of 2 X 1017 cm · 3 as it is. The voltage resistance and 0 N were measured for the two horizontal JFETs. The resistance is shown in Table 2. Table 2 (Please read the precautions on the back before filling this page) ·.

· Line 11 II- * Printed horizontal JFET with the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, withstand voltage (V), ON resistance (m Ω -cm2) with low concentration layer (example of the present invention) 250 8.7 without low concentration layer (comparative example) ) 250 10.0 As shown in Table 2, the withstand voltage is maintained at 25V high withstand voltage, and the ON resistance can be reduced from 10 ηΩ · cm2 to 8.7 ηΩ · cm2. -42- The size of the winter paper applies the Chinese National Standard (CNS) A4 (210 x 297 mm) 474015 A7 B7 V. Description of the invention (40) (Embodiment 2 corresponding to Embodiment 6) The 4M ^ ^ ^ ^ ^ ^ structure is used to change the ρ-type SiC film and the P-negative trace. The rise (fall) time when the voltage is applied is measured. It is used as an indicator of the response speed of the switching element. In addition, a ^ film was used for the electrode: 'P-type impurity region during ohmic contact period' to form ohmic contact. Table 3 shows the measurement results. Table 3 The rise (fall) time printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (ns ^ 2000 200 20 --2__ As shown in Table 3, the concentration of p-type impurities increases in inverse proportion to the above rise time, The rising (falling) time tends to be shortened. (Embodiment 7) FIG. 15 is a horizontal JFE1 ^ 々 cross-sectional view of Embodiment 7 of the present invention. In FIG. : It is formed on the inner surface of the substrate. According to the structure of FIG. 15, the gate resistance scale can be reduced, so that the rise (fall) time of switching can be shortened. Moreover, the manufacturing method is simple and easy, and the yield can be improved. (Embodiment 8 FIG. 16 is a cross-sectional view of a horizontal JFET according to Embodiment 8 of the present invention. In FIG. 16, a 6Η-ρ + type Sic film 2 is formed on a 6H-SiC substrate 1. Of course, other than a 6H type substrate, it is also possible Use 4 Η type substrates. "6H-" or "4 Η-" will be omitted hereafter. In Figure 丨 6, the channel area 丨 丨 contains sic -43 on both sides of this type. This paper size applies Chinese National Standard (CNS) A4 Specifications (21〇χ 297 mm (Please read the notes on the back first (Fill in this page) I .1 »* I ----- r --- ^ --------- ^ I ------------------- ---- 474015 A7 V. Description of the invention (41) Membrane 3 shovel &lt; High concentration n-type impurity with high concentration of osmium. Source 12 and drain 13 are viewed from the channel region u. The n + SiC film 4 <source area and no area above both sides of the channel. Also, the ends of the ^ + type sinker are not covered by the upper η-type SiC film 3, on a wider plane that is not covered. In order to sandwich the source electrode 12 and the drain electrode 13 formed above the center, two gate electrodes 14 are formed. Gp, the conducting circuit between the source, the region, and the intermediate electrode is not narrowed by a trench or the like on the way It is through a wide cross section. The impurity concentration of each region is as follows. Channel region 1 1: n-type impurity 1 X 1018 cm-3 n-type SiC film 3 on both sides of the channel region: n-type Impurities 2xl0ucm-3 source, no region (n + -type SiC film) 4 ·· n-type impurities> lxl1019cm-3 ρ-type SiC film 2: n-type impurities> ixi〇i9cm-3 The thickness a, the length L, and the width w 'perpendicular to the paper surface can be determined according to the size of the element. The electrode i 2 and the source region 22 ^ the drain electrode 13 and the drain region 23 are for the reason that the impurity concentration exceeds 1 × 10 × 9 cm · 3 and the connection between the region and the metal film. For example, by using N丨 is a metal film, which can form an ohmic contact. In addition, the contact between the gate electrode 4 and the p-type film 2 in the gate region is also due to the connection of the high-concentration region with an impurity concentration exceeding 1 × 19 cm · 3 to the metal film. For example, Ni is used as a metal film, and heat treatment is performed to form an ohmic contact. In the ON state of this k-type JFET, carriers flow on a path from the source 12 through the source region 22, the channel region 丨 to the drain region 23. Even if the cross-sectional area of the channel area is small in this path, the impurity concentration is high, which can reduce the resistance, reduce the ON resistance, and reduce the power consumption. Therefore, even if there is a large (please read the precautions on the back before filling out this page) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs · —— 丨 — Order --------- line— -0 ^- --------------------- -44- 474015 A7 B7 Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention (42) Current flow, power loss also Small and can suppress fever. On the other hand, in the OFF state, a reverse bias is applied to the gate electrode 14 to form an empty layer on the n-type SiC film side of the pn junction. This empty layer is more developed on both sides of the channel region 11 and grows into the channel in a manner that occludes the path cross section of the channel region as the reverse bias increases. When the path section of the passage area is blocked by an empty layer, it becomes OFF. By using this horizontal JFET structure, it is possible to increase the withstand voltage and shorten the switching response time without increasing the on-resistance, and to provide a functionally stable JFET. Therefore, it can be used as a high-speed switching element with low loss and large power. This horizontal JFET has simple manufacturing steps and has few problems such as a decrease in yield, and it can be manufactured at low cost. (Example corresponding to the eighth embodiment) A horizontal JFET having a structure shown in FIG. 16 was manufactured. Figures corresponding to Figures 36 to 36 illustrating the method of manufacturing a conventional horizontal JFET are shown in Figures 17 to 19 below. First, a p + -type siC film is formed on a p-type SiC substrate, and then, an n-type SiC film is formed. The n-type SiC film 3 has an impurity concentration of 166 x 1017 cm · 3. After forming an η + -type SiC film thereon, etching is performed by RIE, and a central portion of the portion containing the source and drain regions is etched by RIE to form a trench to separate the source region 22 from the drain region 23. structure. A &lt; channel region 11 is formed below the bottom of the trench, and is doped by ion implantation of n-type impurities (Fig. 18). Let the channel region 丨 in-type impurity concentration be 36 &lt; 1018 cm-3. Let the channel length L be 8 // m, the channel thickness &amp; be 21411111 (〇 214 // m), and the width perpendicular to the paper surface be 07211111. Secondly, a gate electrode is provided on the p + SiC film 2 and a source region 2 2 and a drain region 2 3 are respectively located on the n + impurity region. The source (please read the note on the back? Matters before filling this page). i • line 丨--45-

474015 A7 V. Description of the invention (43) pole 12 and pole 13 (Figure 19). After that, there is no step of setting / etching the p + ye film 2. The horizontal JFET of the comparative example is shown in Fig. 35. The source region and the region do not particularly increase the impurity concentration, and the concentration of the η-type ye film 3 is maintained at 1.66 X 1017 cm-3 as it is. The channel shape is the same as the horizontal JFET of the example of the present invention described above. The horizontal jFETs of the two were measured for withstand voltage and ON electric power. The measurement results of Yushu are shown in Table 4. Table 4 Channel endurance: (V) ---- one ON resistance (applied IV) (m Ω -cm2) N mixed negative 7-degree channel (example of the present invention) 155 0.93 conventional channel (comparative example) 155 2.20 ( Please read the cautions on the back before filling this page.) ·. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in Table 4. 20 ιηΩ · cm2 reduced to 0.93 ιηΩ · cm2. (Embodiment 9) FIG. 20 is a cross-sectional view of a horizontal JFET according to Embodiment 9 of the present invention. The impurity concentration of parts other than the gate is the same as that of the horizontal JFET of FIG. 16. In FIG. 20, a feature is that the gate electrode 14 is formed across the inner surface of the p-type SiC substrate 1. According to the structure of 20, the ON-OFF state can be realized by applying the gate voltage in the same manner as in FIG. Furthermore, the gate resistance Rg can be made lower, so that the rise (fall) time of switching can be shortened. In addition, the manufacturing method is concise and can provide good yield. (Embodiment 1) FIG. 21 is a cross-sectional view of a horizontal JFET according to Embodiment 10 of the present invention. In Figure 21, the thickness a of the channel area 丨 丨 is proportional to ρ η-the diffusion of the junction -46- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 丨 order i- Line 丨 * 丨 丨 474015 A7

5. Description of the invention The width of the empty layer generated on the η-layer side is small at (44) bits (about 2 V to 3 V). Although the joint portion has a "width", in Fig. 21, the "width" is a thickness. Specifically, when the impurity concentration of the n-layer is ixiou cm · 3, the thickness a of the channel region is less than 500 nm. The impurity concentration n in the channel region is preferably thicker than the concentration η- of the ^ _ layer. In the horizontal JFET of FIG. 21, a positive potential higher than the source potential is applied to the gate in order to achieve a positive potential. If the gate potential is increased to be larger than the diffusion potential, ρη · is connected to the conduction state. Therefore, it is meaningless to increase the gate potential beyond the diffusion potential. That is, in the 0FF state, the gate potential is set to 0 potential, and in the 0 N state, the gate potential may be set to a positive potential of about 3 V. / Personal description The withstand voltage design of the horizontal JFET shown in Figure 21 A withstand voltage design of 2000 V is set, and the thickness Η of the n-type SiC film 3 in FIG. 21 is set to 900 nm. At this time, based on the relationship between Η and the withstand voltage shown in FIG. 22, the withstand voltage is 21 to 22 volts, and indeed exceeds 200 volts. When Η is 900 nm, the thickness of the channel region &amp; can be set to 500 nm. The thickness of the empty layer caused by the diffusion potential is larger than the thickness of the channel region 'and the thickness of the empty layer is given by n. It is 1 x 1016 cm · 3 or less. The impurity concentration η of the channel region η can be set to 3 · 8χ 1017 cm · 3 as the impurity concentration of the η-layer south. In this way, the withstand voltage can be ensured, and in addition, the horizontal JFET which is normally off is available. Therefore, it is possible to achieve "normally off, state, power consumption reduction, and without taking brake circuit fault countermeasures such as rotation, etc., you can use this horizontal JFET for control. (Embodiment 1 1) Figure 2 3 is the invention Cross-sectional view of a horizontal jFET of Embodiment 11. In Fig. 23, an n-type SiC film is formed on both sides of the channel region 21 to form a two-layer structure of a lower layer n · layer 3a and an upper layer ~ layer 3b. For pressure resistance and high-speed opening _ -47- This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) (Please read the note on the back? Matters before filling this page) Intellectual Property of the Ministry of Economic Affairs Printed by Bureau Consumers Cooperative

&gt; Liao J Yi-kou, I ϋ II ϋ n ϋ ϋ ϋ n ϋ I ϋ I ϋ ϋ ϋ ϋ ϋ ϋ ϋ n ϋ n ϋ I 474015 A7 B7 V. Description of the invention (45) related actions, etc., and to achieve " In the normally closed state, the concentration n2 of the upper layer n in the channel region 1 1 is desired to be higher than η ·, and it is desirable. The concentration is higher than ni. Even with this structure, high-speed switching operation and high Withstand voltage can be obtained in the same way as in Embodiment 10. The horizontal JFET is normally closed. To obtain a withstand voltage of 200V, set the thickness of the above two layers (η -layer / ^ layer) to 1200 nm. The impurity concentrations are set as follows. The concentration of the η layer in the upper layer 111 = 1 X 1017 cm · 3, the concentration of the η layer in the lower layer η · = 1χΐ16 cm · 3, and the concentration of the channel region η2 = 3 · 8 X 1017 cm. · 3, the thickness of the channel area a = 500 nm, which can ensure the withstand voltage of 200V, and obtain the horizontal JFET of the "normally closed" high-speed switching operation 〇 (Embodiment 1 2) Figure 2 4 is the invention A cross-sectional view of a horizontal jfet according to Embodiment 12. In the same figure, a p-type SiC film 2 is formed on a SiC substrate 1, and an n-type SiC film 3 is formed thereon. Those with reduced thickness of the channel region 1 1. On the N-type SiC film 3 on both sides of the channel region 11, N + -type SiC films 22, 23 are formed as source and drain regions, and source and drain regions are formed on each region. The poles i 2, 丨 3. Also, two gates 1 4 are formed on the p-type SiC film, which is a person who clamps the source and drain regions from a plane view. The biggest feature of this embodiment is the channel region. An aluminum film 17 is formed on the aluminum film. The cross-sectional length of the aluminum film is smaller than the channel length L. From a plan view, the aluminum film is contained in the channel region. That is, the aluminum film 7 is not connected to both side walls of the channel region 11 The second is to explain the operation of this JFET. First, in the ON state, the carrier substrate surface flows in the channel region. At this time, if the aluminum layer 7 is arranged on the channel region, the current system is In the channel area 丨 丨 Consisting with aluminum film 丨 7 = • 48- This paper size is applicable to Zhongguanjia Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back before filling this page ) ·. --- ^ ----------------------------------- 474015 A7 B7 Invention Description (46) Department of low 127, aluminum main film (resistance and Comparison of the resistance in the channel area, for example, the F / lr erH brother, the current flowing through the film 17 is higher than the through = = about lp, so the current flowing in the semiconductor can be omitted, transistor characteristics There is almost no correlation with the impurity concentration of the channel area or the thickness of the channel area. As a result, the resistance in the channel region is reduced, and it is not necessary to infiltrate high-concentration impurities, while maintaining the original high withstand voltage performance and ensuring other transistor characteristics without deviation. On the other hand, in the OFF state, a negative potential is applied to the gate electrode 14 shown in Fig. 25. Therefore, at the junction of the p-type Sic film Wn-type sinker 3, the empty layer is larger. The larger the absolute potential of the negative potential is, the impurity concentration on the lower side of the impurity concentration is inversely proportional, and the width of the empty layer is larger. If the width of the empty layer before the end portion exceeds the thickness a of the channel region 11, the channel region is cut by the empty layer, preventing carriers from passing. As described above, since the aluminum film 7 is not connected to the walls on both sides of the channel region i i, when the front end portion of the empty layer width exceeds the thickness a of the channel region, an 0FF state can be achieved. (Example corresponding to Embodiment 12) (Please read the precautions on the back before filling out this page) Printed on the JFET shown in Figure 12 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to print clothing. Channel resistance when [v is applied. This JFET is a 100V withstand voltage device. The impurity concentration of the 11-type SiC film 3, 4 on the channel-containing region is set to 4 · χχ 1017 cm · 3, the channel length is 10000 nm (10 #m), and the channel region thickness a is 230 nm. Table 5 Unit of classified channel resistance (applied lv): rnflcm2 Example of the present invention 1.6 Conventional example 7.8 -I · III l · III · IIIIIIIII ^^^ 1 — — — — — — — — — — — — — 49 The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 474015 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ----------- B7______ V. Description of the invention (47) According to The results shown in Table 5 show that the channel resistance of the conventional example JFET without a metal film in the channel region (JFET after removing the JFET in FIG. 24 from the aluminum film) was 7.8 miUm2. In contrast, the channel resistance of the JFET of the twelfth embodiment provided with an aluminum film (the present example) is 1.6 m β cm2, which is greatly reduced. Therefore, the present invention shows that the channel resistance can be greatly reduced. Therefore, it is possible to obtain a JFET 'having a small inter-element deviation, which is not affected by the change in the impurity concentration of the channel region or the thickness of the channel region. (Embodiment 1 3) The horizontal JFET of the above-mentioned Embodiment 12 shown in Fig. 24 and Fig. 25 shows a state in which the current flows in the channel area "normally open" when the gate pressure is 0. . In the case where the normally open JFET is used for the control of a rotating machine, etc., if the brake circuit fails, there is a risk that the rotation cannot be stopped. Therefore, a mechanism that can cope with the failure of the brake circuit must be provided. For the sake of trouble, I hope to have a JFET that is normally closed. The second embodiment explains this. As shown in FIG. 26, the biggest feature of this embodiment is as follows. The width of the empty layer caused by the diffusion potential of the junction of the P n 2 junction, that is, the gate potential is 0, is greater than the thickness of the channel region a. Big. For example, by setting (a) the concentration center to ix 1016 cm · 3 and (b) the channel region thickness a to be 500 nm or less, the width of the empty layer caused by the diffusion potential exceeds the thickness a of the channel region. Off "status. By adopting the above-mentioned structure, it is possible to obtain a gift that does not reduce the withstand voltage performance, and does not cause characteristic deviation due to the variation of the channel concentration, and can be realized in normal time. UFET. Therefore, it is not necessary to provide a mechanism for responding to a brake circuit failure in a control device such as a large rotating machine. (Please read the notes on the back before filling this page)

Aw ----- ^ --------- 通 ----------------------- -50-

474015 A7 B7 V. Description of the invention (48) (Embodiment 1 4) Fig. 27 is a cross-sectional view of a horizontal JFET according to Embodiment 4 of the present invention. On the P-type SiC substrate, a p-type epitaxy whose concentration is adjusted in a region is formed. Membrane 2 &amp;, 2b, 2c. A p + Sic layer 2a is formed in a high-concentration impurity region under the channel region 1 and p-Sic layers 2b, 2c of a high-resistance layer are arranged on both sides thereof. An n-type epitaxial SiC film is formed thereon, and the channel region 丨 and the source and drain regions 22 and 23 are connected according to the trench 19. On these parts, high-concentration sources and drain regions 22 and 23 are formed in a manner capable of achieving ohmic contact, and source and drain electrodes 12 and 13 are provided thereon. In addition, a gate electrode 14 is formed on the back surface of the p + type sic substrate with a high concentration to form a back gate structure. Sic with high concentration of impurities: The gate is set on the substrate because of the ohmic contact available. However, it does not have to be a back gate, as long as it is on a Sic substrate containing a high concentration of impurities, and a gate electrode may be provided on the SiC substrate 1 next to the p-SiC layers 2b and 2c in the high resistance region. In the case of a back gate, a high power device can be formed. On the other hand, in the case where a gate electrode is provided on the SiC substrate 1 next to the high-resistance regions p-Sic ^ 2b and 2c, a semiconductor device such as a lsi wafer can be formed on each side on one side. Partly, the advantages of making it complete. Fig. 27 is characterized in that the length of the hafnium SiC layer 2a is shorter than that of the channel region, and the cross-sectional area in the thickness direction of the high impurity concentration region is made small to increase the resistance of the high concentration impurity region. Here, in FIG. 27, the width direction of the horizontal JFET is set to the direction perpendicular to the paper surface, the length direction of the channel is set to the length, and the direction perpendicular to the layered surface is set to the thickness direction. The above-mentioned high-concentration impurity region ρ + SiC layer 2a does not need to be provided in the channel region 5 -51-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before (Fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs · n · ϋ ϋ n · ϋ H 1-port, I n ϋ ϋ I ϋ I ϋ I line ------------- --------- 474015 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (49) It can also be located near the source area 2 2. The high-resistance regions p-SiC layers 2b and 2c on both sides of the p-SiC layers 2b and 2c have a low impurity concentration and high resistance. Therefore, the current leaking from the green channel region and entering the p-SiC layers 2b and 2c is reduced. In the case where the p + SiC layer 2 a is formed by the ion implantation method, the minimum width yield can be set to about 1 &quot; m. Therefore, the resistance of the ρ + SiC layer 2 a also increases. As described above, by making the p + SiC layer 2 smaller so that the concentration on both sides is lower, the channel leakage current when a forward bias voltage is applied can be suppressed more than before. Therefore, it is possible to prevent the reduction of the magnification in the 0 N state from occurring. (Embodiment 15) FIG. 28 is a cross-sectional view of a horizontal JFET according to Embodiment 15 of the present invention. The structure different from the horizontal JFET shown in Figure 27 is only the high-resistance region under the source, channel, and no-region. This high-resistance region is formed on both sides of the p + SiC layer 2a as rTSiC layers 2b, 2c. Of course, the n-type impurity concentration of the layers 2b and 2c on both sides is set to be low. When the above structure is in an open state, the resistances of the high-resistance regions n-SiC layers 2b and 2c on both sides of the p + SiC layer 2a are as large as those of the fourteenth embodiment. Therefore, as in Embodiment 14, the leakage current from the channel area side to the first siC film can be suppressed, and the reduction of the amplification factor can be prevented. (Embodiment 16) FIG. 29 is a cross-sectional view of a horizontal jFET according to Embodiment 6 of the present invention. The structure different from the horizontal JFET shown in Figure 27 is only the high-resistance region under the source, channel, and drain regions. This high-resistance region is formed by two layers on both sides of the p + SiC layer 2a as the p.SiC layer 2 lb and the 21c / p.SiC layers 20b and 20c. A reverse-surface bias is applied to the ρ-η · joining surfaces of the high-resistance regions on both sides in the ON state. Because -52- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) C Please read the note on the back first? Please fill in this page again for the matter} ·· Order --- 丨 Line 丨-474015 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (so) This is indicated by the arrow in Figure 29 ρ · The η · joining surface forms an empty layer. Therefore, the resistance corresponding to the current leaked from the source and channel regions becomes very large, and the above-mentioned leakage current is greatly suppressed. As in this embodiment, in the ON state, the best is to form an empty layer in the surrounding area outside the high-concentration impurity region of the i-th SiC film, so that the resistance of the high-resistance region becomes very high. (Embodiment 1 7) FIG. 30 is a cross-sectional view of a horizontal jFET according to Embodiment 7 of the present invention. The structure of the horizontal JFET shown in FIG. 3 is different from the horizontal JFET of Embodiment 14 shown in FIG. 27 only in that an n + SiC substrate is used as the substrate. In other words, the high-concentration impurity region p + SiC layer 2a is made as short as possible and the joint system is the same as that of the fourteenth embodiment. Since the n + SiC substrate is used as the substrate, in the ON state, a reverse bias is applied to the junction surface between the substrate 1 and the p-SiC layers 2b and 2c, so the empty layer grows in the ρ · SiC layers 2b and 2c. . Therefore, in this embodiment, due to the formation of empty layers on both sides of the high-concentration impurity region p + SiC layer 2a, the resistance is greatly increased, and current leakage from the source and channel regions to the first SiC film can be greatly suppressed. In this embodiment mode 17, the case where an empty layer is formed on the high-resistance layer in the on state is also preferable. (Embodiment 18) FIG. 31 is a cross-sectional view of a horizontal JFET according to Embodiment 18 of the present invention. The structure of the horizontal jFET shown in FIG. 31 and the horizontal JFET of Embodiment 15 shown in FIG. 28 is different only in that an n + SiC substrate is used as the substrate. That is, the high-concentration impurity region p + SiC layer 2a is made as short as possible and is the same as Embodiment 15. In addition, the principle of suppressing the leakage of current to the 1st siC film is also the same as -53- This paper size applies the Chinese National Standard (CNS) A4 specification (21〇x 297 mm) ϋ n I ϋ I ϋ ϋ ϋ ϋ n ϋ ϋ I · ^ 1 ϋ I ϋ ϋ ^ 1 ϋ 1: mouth V a · ϋ IH ϋ 1 I 1 I ϋ n ϋ ii ϋ ϋ ϋ ϋ n ϋ n ϋ ϋ ϋ n ϋ · ϋ -1 n ϋ n _ (Please (Please read the notes on the back before filling this page) 474015 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (51) The horizontal JFET in Figure 2 8 is the same, so the description is omitted. (Embodiment 1 9) FIG. 32 is a cross-sectional view of a horizontal JFET according to Embodiment 19 of the present invention. The structure of the horizontal JFET shown in FIG. 3 and 2 is different from the horizontal JFET of Embodiment 16 shown in FIG. 29 only in that the η + SiC substrate 1 is used as the substrate. That is, the p-SiC layer 2a in the high-concentration impurity region is made as short as possible and the same as in Embodiment 16. The principle of suppressing the current source, the leakage of the channel region to the first ye film, and the principle of forming an empty layer are the same as those of the horizontal JFET shown in FIG. 29, and the description is omitted. (Embodiment 20) FIG. 33 is a cross-sectional view of a horizontal JFET according to Embodiment 20 of the present invention. Any of the above-mentioned embodiments 1 to 19 is assumed to be normally opened and operated. That is, it is assumed that the gate voltage is set to 0 or a little positive potential to the source potential (usually the ground potential), and is set to the ON state. Therefore, in order to set it as 0FF, a specific negative voltage must be applied to the gate. However, yes, the normally open WET needs to be provided with redundant control circuits in accordance with the fault handling to perform the horizontal jFET of the "normally closed" operation. That is, when the gate voltage is 0, in the transportation area, the "卩" layer 2a grows into an empty layer to cut off the channel area, and when the gate voltage is set to a specific positive voltage, it is desirable to achieve an ON state. The concentration of the n + sic layer 2 in the impurity region is increased to reduce the N-type impurity concentration in the channel region 11 and the empty layer 18 cuts off the channel region at the gate voltage of 0, that is, the diffusion threshold. Therefore, When the gate voltage is in the OFF state, there is no need to provide a control circuit to cope with the failure of the gate circuit. The structure of the horizontal JFET in FIG. 33 is the same as that in the figure above. ----- · ----- r --- Order --------- Line—— · ------- (Please read the precautions on the back before filling this page) -54 474015 A7 V. Description of the invention (52) Because the structure of the horizontal ηΕτ is the same, the mechanism that suppresses the leakage of current from the source and the channel area to the 18th is the same as that described in the embodiment. The embodiments and examples are described. The embodiments and examples of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to the embodiments and implementations of these inventions. The description of the second and the second round is shown in the scope of the patent application and also includes all changes and implementations within the meaning and scope of the patent application. <&Quot; According to the present invention, a JFET made by Sic can be obtained. It uses high-quality SiC substrates and has a channel area that uses highly mobile electrons. It can also provide horizontal JFETs with consistent quality, which can be used for high power applications with low power loss, excellent voltage resistance and high speed. Semiconductor switching element. ^, 丨, you can get a horizontal JFET, which can suppress the leakage of current from the source channel area to the SiC film, to prevent the reduction of magnification. (Please read the note on the back? Matters before filling this Page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-55- This paper size is applicable to China National Standard (CNS) A4 (21〇X 297 mm) »4 --------- Order --- ----- • Line 丨 -----------------------

Claims (1)

474015 A8B8C8D8 Patent application scope 1.::Horizontal junction type field effect transistor, which is characterized by: having a torn n-type SiC substrate; a P-type SlC film, which is formed on the surface of the aforementioned n-type SiC substrate; ηdS 'C film' is formed on the aforementioned "sic film, which contains the channel domain; two 甬: and =, which are formed on the aforementioned _Sic film, which are formed on both sides of the 刖 通 forcing region; and the gate, It is installed in connection with the aforementioned 11 type 3 沱 substrate. 2 · The horizontal joint type field effect transistor in item 丨 of the Shenyang Patent Fanyuan, of which, in plan view, it is based on the above 1) type and (: The area of the film includes the area of the aforementioned η SiC film. 3. The horizontal junction type field effect transistor according to item 丨 of the patent application, wherein the gate is located on the surface of the nSSic substrate and is arranged close to the foregoing. The end of p-type SiC film. 4 · For example, the horizontal junction type field-effect transistor of the scope of application for patent, in which the aforementioned gate is formed in the aforementioned 11-type substrate: the inside of the substrate is the back gate ... gate) configuration. 5 · Horizontal joint type field as in the first patent application In the transistor, the thickness of the aforementioned channel region is smaller than the width of the empty layer in the n-type Sic film; the empty layer in the n-type SiC film is based on the p-type Sic ^ and the p-type SiC film. The diffusion potential of the junction of the aforementioned 11-type sic film. '6 · For example, the horizontal junction type field effect transistor of the scope of patent application, in which 56- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) i ------- Order --------- Line! Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Industry and Economics 474015 C8 ----- D8 __ _ Sixth, the scope of patent application is even more low-concentration η-type SiC film, which is connected and sandwiched by the p-type SiC film and η Between SiC films, η-type impurities with a lower concentration than the n-type impurities in the aforementioned channel region. 7 · If the horizontal junction type field-effect transistor of item 丨 of the patent application range, wherein the aforementioned channel region contains a concentration higher than two An n-type impurity having a high impurity concentration on the side of the 11-type sic film portion. Please apply for the horizontal junction field-effect transistor of item 丨 in the patent, which has a conductive film, which is connected to the aforementioned channel area. 9. For example, the horizontal junction field-effect transistor of item 8 of the scope of patent application Where the length of the conductive film along the length of the channel is shorter than the length of the channel. 10. If the horizontal joint type field effect transistor of item 8 of the patent application garden, the thickness of the aforementioned channel region is greater than the η The width of the empty layer in the n-type SiC film is small; the empty layer in the n-type SiC film is based on the diffusion potential of the p-type Sic film and the junction of the n-type sic film formed on the p-type SiC film. . '11. The horizontal junction type field effect transistor according to item 8 of the Shenyang Patent Fanyuan, wherein the conductive film is any one of a semiconductor film including a metal film and a high concentration of impurities. 12. According to the horizontal junction type field effect transistor of the first item of the patent application, wherein the SiC substrate is a 6H-SiC substrate, the p-type sic film and the 11-type SiC film are both 6H-SiC substrates. 13. As in the horizontal junction field-effect transistor of the first item of the patent application, wherein the p-type SiC film and the n-type SiC film are both 4H-SiC, the p-type SiC film made of 4H-SiC is as described above. '-57 on 6H-SiC substrate via 4H-SiC- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) --I ------ III-- ---- -^ --- I ----· Line-(Please read the notes on the back before filling this page) 474015 Α8 Β8 C8 6. Scope of patent application Formed by the buffer layer printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 14. For the horizontal junction field effect transistor of item i in the patent application, where the SiC substrate is a 4H-SiC substrate, the p-type Sic film and the 11-type Sic film are both 4H-SiC substrates. 15. For the horizontal junction field-effect transistor of item 1 of the patent application, wherein the aforementioned P-type Sic film and the aforementioned η-type SiC film are both 6H_Sic, and the p-type SiC film formed by 6H_Sic is described as 4H -SiC substrate formed by 6H-SiC buffer layer. 16 · —A horizontal junction type field effect transistor, comprising: a SiC substrate; a second conductive siC film formed on the sic substrate; and a first conductive SiC film formed on the foregoing The second conductive type sic film; the channel area is formed in the aforementioned conductive type sic film, and its film thickness is made thin; the source region and the drain area are formed in the aforementioned conductive type The first conductive SiC film formed on the sic film is formed on both sides of the channel region; and the gate electrode; the gate electrode is formed as a flat region of the second conductive type Sic. 17. The horizontal junction type field-effect transistor of item 16 in the application of patent μ, the aforementioned second conductive SiC film has a groove-free surface; the aforementioned interrogation electrode is formed by two interrogation electrodes. The second conductive type Si. The flat region is formed on the flat surface of the second conductive sic film. ____ -58- Dimensions of this paper ^ Use standard (cns) A4 ^^ iq χ 297 public love) ---- I ---------------- Order ------ --- Line--AWI (Please read the note on the back? Matters before filling out this page) 474015 A8 B8 C8 D8 Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The scope of patent application 18. ^ The scope of patent application 16 In the horizontal junction field-effect transistor of the above item, the Sic substrate is a second conductive Sic substrate containing a second conductive impurity; the gate is a back-gate structure, which is provided in the second conductive sic. The flat area is a surface provided on the back side of the second conductive Sic substrate. 19. For example, the horizontal junction field-effect transistor of item 16 of the patent application, which further includes a low-concentration i-conducting SiC film, which contains the second conductive SiC film and the first conductive type Between the Sic films, the conductive type impurity having a lower concentration than the conductive type impurity of the aforementioned channel region is 0 2 0. For example, the horizontal junction type field effect transistor of the 16th area of the patent application, wherein the aforementioned channel region Containing high-concentration first-conductivity-type impurities, the concentration of which is higher than that of the first-conductivity-type sic film portion on both sides. 21. For example, the horizontal junction type field effect transistor of item 19 of the patent application scope, wherein the aforementioned channel region contains a high concentration of the first conductivity type impurity, the concentration of which is higher than that of the first conductivity type sic film portion on both sides thereof. Those with high impurity concentration. 22 · = Horizontal junction field-effect crystal of the 16th in the scope of patent application, wherein the thickness of the aforementioned channel region is smaller than the width of the empty layer in the conductive Sic film; the conductive i-SiC The empty layer in the film is based on the diffusion potential of the second conductive type SiC film and the junction of the second conductive type SiC film (the first conductive type SiC film formed on the film). The horizontal junction field-effect transistor in the range of item 20, wherein the thickness of the aforementioned channel region is smaller than the width of the empty layer in the first conductive SiC film; the empty layer in the first conductive sic film , Based on I 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 Order 丨 丨-丨 丨 I--I (Please read the precautions on the back before filling this page) -59- 474015 Printed C8 by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^^ _____ Sixth, the scope of the patent application for the aforementioned second conductive SiC film and the junction of the first conductive sic film formed on the second conductive sic film Diffusion potential. 24. For example, the horizontal junction type field effect transistor of the 16th in the scope of patent application, which has a conductive film, It is connected to the surface of the aforementioned channel region and is arranged in a horizontal manner. 25. For example, the horizontal joint type field effect transistor of item 24 of the patent application scope, wherein the length of the aforementioned conductive film along the length of the channel is better than the length of the channel. 126. For example, the horizontal junction type field effect transistor of the 24th in the scope of patent application, wherein the thickness of the aforementioned channel region is smaller than that of the empty layer in the conductive type Sic film; the first conductive type The empty layer in the SiC film is based on the diffusion potential of the junction between the second conductive SiC film and the first conductive Sic film formed on the second conductive Sic film. The horizontal junction field-effect transistor of 24 items, wherein the aforementioned conductive film is any one of a semiconductor film containing a metal film and a high concentration of impurities. 28. The horizontal junction type field according to item 6 of the application for a patent The effect transistor, wherein the source region and the non-contained region contain high-concentration first-conduction-type impurities, the concentration of which is higher than that of the first-conduction-type SiC film on both sides of the channel region. Item 丨 6 horizontal joint type Effect transistor, wherein the impurity concentration of the aforementioned second conductive SiC film is more than 1019 cm-3. 30. For example, the horizontal junction type field effect transistor of the patent application No. 丨 6, wherein the aforementioned source region The source formed on the substrate, the drain formed on the aforementioned drain region, and the aforementioned second conductive type SiC film or the aforementioned second conductive type si (: on the substrate-60) This paper is in accordance with China National Standard (CNS) A4 Specifications (210 X 297 public love) (Please read the precautions on the back before filling out this page) II Γ I * Withdraw I — — — Line 34. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 36. The closed electrode formed is composed of metal, and the metal is an ohmic contact to the SiC containing impurities in contact with each electrode. For example, the horizontal junction type field-effect transistor of item 16 of the patent application, in which the surface other than the source electrode, the non-electrode, and the gate electrode is an insulating film. In the effect transistor, the Sic substrate is a 6H-SiC substrate, and the second conductive Sic film and the first conductive Sic film are both 6H-SiC. For example, the horizontal junction field-effect transistor of item 16 of the patent application, wherein the aforementioned second conductive SiC film and the aforementioned i conductive Sic film are both 4h_SiC, and the aforementioned second conductive made of 4H-SiC A type Sic film is formed on a 6H_ SiC substrate through a 4H-Sic buffer layer. For example, if the application is called a patented field-effect transistor of 16 items, the Sic substrate is a 4H-SiC substrate, the second conductive Sic film and the first conductive SiC film are 4H-SiC. By. For example, the inspection type junction field-effect transistor of item 16 of the patent scope is declared, in which the aforementioned second conductive SiC film and the aforementioned first conductive Sic film are both 6H_SiC 'the aforementioned second conductive made of 6H-SiC Type Sic film, which is formed on a 4H_ SiC substrate, through a 6H-SiC buffer layer. The type-type field effect transistor is characterized by including a SiC substrate having a gate electrode, a first S iC film formed on the aforementioned SiC substrate, and a second Sic film of a first conductivity type. It is formed on the aforementioned 1st Sic film, 'including β will be made into a thin channel area, and the channel (please read the precautions on the back before filling this page) ϋ t · 订 order --- ! Line 丨 -61-This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 474015 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The first Sic film is located in the lower part of the channel area, and has a width that is approximately the same as that of the child channel area and a length shorter than that of the channel area. It is composed of the following areas: high In the concentration impurity region, the second conductivity type impurity has a higher concentration than the channel type first conductivity type impurity> and the high-resistance region has a high resistance outside the high-concentration impurity region. 37. The horizontal junction type field effect transistor according to item 36 of the patent application, wherein the high-resistance region contains the first conductivity type impurity, the concentration of which is higher than that of the second conductivity type impurity concentration of the second SiC film. The low one. 38. ^ The horizontal junction type field effect transistor of the 36th aspect of the application for a patent, wherein the high-resistance region contains a second conductivity type impurity whose concentration is higher than that of the first conductivity type impurity concentration of the second SiC film. The low one. 39 · = Horizontal junction field-effect transistor of item 36 of the patent application, among which the resistance area is described by The second layer and the second layer are structured; the first ^ f contains the first conductivity type impurity, whose concentration is lower than the concentration of the first conductivity type impurity of the second sic film; the second layer includes the first丨 Conductive impurities whose concentration 値 is lower than the 丨 conductive type concentration of the aforementioned 2Sic film. 40. The horizontal junction field-effect transistor of the 36th aspect of the patent application, in which the aforementioned high-concentration impurity region and the aforementioned channel region are connected to each other. Formed in such a manner that the aforementioned channel region is cut off. 41. For example, the 撗 -type junction field effect transistor in the 36th scope of the patent application, of which (please read the precautions on the back before filling out this page) —— order the line reference. -62 474015 Employees ’Consumption of Intellectual Property, Ministry of Economic Affairs Cooperative printed A8 B8 C8 D8 VI. Patent application scope The aforementioned channel area contains a high concentration of the first conductive type impurities, the concentration of which is higher than the impurity concentration of the first conductive type Sic film part on both sides of 眞. / Another 42, as described in the patent application No. 36 of the horizontal joint type field-effect body, which has a conductive film, which is connected to the surface of the channel area. 43. For example, the horizontal joint type field effect transistor of the 42nd patent application range, in which the length of the aforementioned conductive film along the channel length is shorter than the channel length. The junction type field effect transistor, wherein the thickness of the aforementioned channel region is smaller than the width of the empty layer in the i-type conductive Sic film; the empty layer in the first-conductive type SiC film is according to the second conductive type Diffusion potential of the junction portion between the SiC film and the second conductivity type Sic film before the first conductivity type SiC film. 45. The horizontal junction type field effect transistor according to item 42 of the application, wherein the conductive film is any one of a metal film and a semiconductor film having a high concentration of impurities. '63- Fire degree applies Chinese National Standard (CNS) A4 specification (210 X 297 mm ---------------- · ----- order ----------- --Line (Please read the notes on the back before filling this page)