JP3941335B2 - Junction field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a junction field effect transistor using SiC as a semiconductor, and more particularly to a junction field effect transistor using an n-type SiC substrate having a low defect density as a SiC substrate.
[0002]
[Prior art]
A junction field effect transistor (JFET) is a depletion from a pn junction by applying a reverse bias voltage from a gate electrode to a pn junction provided on a side of a channel region through which carriers pass. An operation such as switching is performed by spreading the layer over the channel region and controlling the conductance of the channel region. The carrier of the channel may be an electron (n-type) or a hole (p-type). However, in the SiC targeted by the present invention, the mobility of electrons is about an order of magnitude higher than that of holes. An n-type impurity region is used.
[0003]
In recent years, JFETs using silicon carbide (SiC) have attracted attention for applications such as high-power high-speed switching elements. Since SiC has (a) carrier mobility as high as Si, (b) electron saturation drift velocity as high as GaAs, and (c) high breakdown voltage, it is considered to be used for high-speed switching devices and high power devices. Is underway.
[0004]
FIG. 6 is a cross-sectional view showing an example of a JFET using SiC (US Patent No. 5, 264, 713). In the figure, the conductivity type of the SiC substrate 101 is preferably a p-type, which is a p-type SiC substrate. The conductivity type of SiC film 102 formed on a region of SiC substrate 101 is also preferably p-type, and is a p-type SiC film. Further, an n-type SiC film 103 is formed on the p-type SiC film 102 including a thinned portion 104 corresponding to the channel region. On this n-type SiC film 103, an n + -type impurity layer 105 in ohmic contact with the source electrode 111 and an n + -type impurity layer 106 in ohmic contact with the drain electrode 112 are formed. The gate electrode 113 is formed as a back gate 113 on the back side of the p-type SiC substrate 101.
[0005]
In the prior art (FIG. 6), the reason why the conductivity type of the SiC substrate is preferably p-type is as follows. As described above, carriers in the channel region are electrons (n-type) because high mobility can be obtained. For this reason, the layer including the channel region is an n-type SiC film. Therefore, a p-type SiC film is used as a layer for limiting the carriers in the n-type SiC film at the periphery. When an n-type SiC substrate is used as the SiC substrate on which the p-type SiC film is formed, a reverse bias voltage is applied to the junction between the n-type SiC substrate and the p-type SiC film when a positive potential is applied to the gate electrode. A depletion layer is generated. For this reason, it is necessary to evaluate and judge the influence of this depletion layer. On the other hand, by using a p-type SiC substrate, it is not necessary to evaluate the influence of this depletion layer, and it is not necessary to consider the reverse bias voltage at the junction of the stacked portion in the middle of the channel region in the on / off operation. Therefore, by using the above-described conductivity type SiC substrate, a depletion layer can be grown only in the channel region as necessary, and a high-power high-speed switching element or the like can be obtained using carriers with high mobility. .
[0006]
[Problems to be solved by the invention]
However, the p-type SiC substrate has a higher density of defects such as micropipes than the n-type SiC substrate. For this reason, the defect density also increases in the crystal growth layer on the SiC substrate which is indispensable in the production of semiconductor elements such as JFETs. Reflecting such a high defect density, a JFET formed on a p-type SiC substrate has a low yield of becoming a perfect quality JFET, and a completed JFET also has a large leakage current.
[0007]
Accordingly, an object of the present invention is to obtain a SiC JFET that uses an n-type SiC substrate and has a channel region having a carrier with high mobility and that provides a high yield.
[0008]
[Means for Solving the Problems]
The JFET according to one aspect of the present invention is formed on an n-type SiC substrate, a p-type SiC film formed on the front surface of the n-type SiC substrate, and a p-type SiC film. An n-type SiC film including a channel region, a source / drain region formed separately on both sides of the channel region on the n-type SiC film, and a gate electrode provided in contact with the n-type SiC substrate With. As current flows exits the depletion layer by the tunnel effect between the n-type SiC substrate and the p-type SiC layer, a p-type impurity concentration of the n-type impurity concentration and the p-type SiC layer of n-type SiC substrate is determined Yes. A JFET according to another aspect of the present invention is formed on an n-type SiC substrate, a p-type SiC film formed on the front surface of the n-type SiC substrate, and a p-type SiC film. In addition, the n-type SiC film including the channel region, the source and drain regions formed separately on both sides of the channel region on the n-type SiC film, and the n-type SiC substrate are provided. A gate electrode. The gate electrode is disposed on the front surface of the n-type SiC substrate and near the end of the p-type SiC film .
[0009]
With the above configuration, an n-type SiC substrate having a low defect density can be used to manufacture a JFET that drives carriers with high mobility with high yield. At this time, whether or not there is a problem occurs depending on whether the JFET is on or off.
[0010]
In the off state of the normally-on JFET, a negative gate voltage is applied, so no problem occurs. That is, in the off state, since a forward bias voltage is applied to the junction between the n-type SiC substrate and the p-type SiC film, no depletion layer is generated at this junction. In the off state, a reverse bias voltage is applied only to the junction between the p-type SiC film and the n-type SiC film, and a depletion layer spreads in the channel region having a low impurity concentration to block the carrier path.
[0011]
When the normally-off type JFET is in an off state, a diffusion potential is generated at the junction between the n-type SiC substrate and the p-type SiC film and at the junction between the p-type SiC film and the n-type SiC film, and a depletion layer is generated. Because each spreads independently, no problem arises.
[0012]
In the normally-on type on-state, the gate voltage may be 0 V, but a depletion layer due to the diffusion potential spreads. In order to flow more current, it is necessary to apply a positive potential to the gate in order to erase the depletion layer due to the diffusion potential. For this reason, it is necessary to examine a depletion layer that occurs accompanying application of a positive potential to the gate. When the potential of the gate electrode becomes positive, a reverse bias voltage is applied to the junction between the n-type SiC substrate and the p-type SiC film. However, the width of the depletion layer is reduced by increasing both the impurity concentration of the n-type SiC substrate and the impurity concentration of the p-type SiC film. For this reason, current flows through the depletion layer due to the tunnel effect. Further, there is a case where the withstand voltage of the junction portion is lost due to the increased impurity concentration and current flows. For this reason, the depletion layer at the junction hardly affects the operation. In order to obtain the junction as described above, the n-type impurity concentration of the n-type SiC substrate is set to about 1 × 10 ¹⁹ cm ^−3, and the p-type impurity concentration of the p-type SiC film is set to 1 × 10 ¹⁹ cm ^−3. It should be about. As a result, it is possible to improve the yield from the production of the SiC substrate to the completion of the product, and to produce a SiC JFET capable of high-speed operation such as high-speed switching.
[0013]
When the normally-off type JFET is in the on state, the same phenomenon as in the above-described case of the normally-on type JFET occurs. Therefore, as described above, no particular problem occurs.
[0014]
In the above description, whether the JFET is a normally-on type or a normally-off type has been described focusing on only the following matters. That is, in the on / off operation, it is only normally on that the gate voltage is changed in the range of minus (off) to plus (on) or normally off that is changed in the range of zero (off) to plus (on). Explain the impact of. As will be described later, the normally-off type JFET is realized by satisfying predetermined requirements for impurity concentration and structure.
[0015]
In the JFET according to the one aspect or the other aspect, the region of the n-type SiC film is included in the region of the p-type SiC film as viewed in a plan view.
[0016]
According to this configuration, the end surface of the n-type SiC film is positioned inward of the end surface of the underlying p-type SiC film as viewed in a plan view. That is, there is a structure in which there is a step between the p-type SiC film and the upper n-type SiC film. The end faces of these SiC films are usually formed by RIE (Reactive Ion Etching). In the conventional structure in which the end face of the n-type SiC film and the end face of the p-type SiC film are aligned, the end face of the n-type SiC film is etched together with the n-type SiC film and the underlying p-type SiC film. In the meantime, the above end face continues to be exposed to ions. On the other hand, in the above structure, the end face of the n-type SiC film is the end face formed by the second etching after the etching of the end face of the p-type SiC film. Exposed to. As a result, the time during which the end face of the n-type SiC film including the channel and the source and drain regions is exposed to ions is shortened, and the surface crystal layer that greatly affects the transistor characteristics is less likely to deteriorate.
[0017]
Further, as described above, in the JFET according to the other aspect described above, the gate electrode is disposed on the front surface of the n-type SiC substrate and near the end of the p-type SiC film.
[0018]
With this configuration, the depletion layer can be formed by applying a reverse bias voltage to the junction between the p-type SiC film and the channel region (n-type SiC film) without fail, and can be manufactured by an easy manufacturing method. A state can be realized.
[0019]
In the JFET in the above aspect, the gate electrode is formed on the back surface of the n-type SiC substrate, and the back gate structure is arranged.
[0020]
By adopting the back gate structure, a signal for applying a gate voltage is transmitted linearly to the channel region over a wide range from the front of the channel region, so that an improvement in switching speed can be obtained. In addition, since the gate electrode is not arranged at a position extending from the channel region but is three-dimensionally overlapped with the channel region, it is possible to increase the integration degree of the JFET. Even in the back gate structure, a depletion layer is formed at the junction between the n-type SiC substrate and the p-type SiC film by applying a positive voltage to the gate. However, as described above, by increasing the impurity concentration on both sides, it is possible to avoid the depletion layer from affecting the operation of the present JFET.
[0021]
In JFET in the above one aspect or another aspect, the thickness of the channel region, the n-type due to the diffusion potential at the junction of the p-type SiC layer, an n-type SiC film formed on of the p-type SiC film The width is smaller than the depletion layer width in the SiC film.
[0022]
With this configuration, when the gate potential is zero, a depletion layer is formed at the junction between the p-type SiC film and the n-type SiC film, and the leading end of the depletion layer width exceeds the thickness of the channel region. For this reason, the channel region is cut off, and the off state is realized when the gate voltage is zero.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0024]
(Embodiment 1)
FIG. 1 is a cross-sectional view of a JFET using SiC in the first embodiment. A p-type SiC film 2 is formed on the n-type SiC substrate 1, and an n-type SiC film 3 in which the channel region 4 is reduced in thickness is formed thereon. In addition, an n + -type impurity layer that becomes the source region 5 and the drain region 6 is formed on the n-type SiC film across the channel region 4. Furthermore, the source electrode 11 is in contact with the source region 5, and the drain electrode 12 is in contact with the drain region 6 to form ohmic contact. In the present embodiment, the gate electrode 13 is formed across the source and drain regions 5 and 6 in plan view. The above-described structure is characterized by a laminated structure of n-type SiC substrate / (L) laminated junction / p-type SiC film / (G) gate junction / channel region n-type SiC film.
[0025]
(A) In a normally-on JFET, high-speed high-speed switching can be performed at a high yield by adopting the above structure. On the other hand, in the (B) normally-off JFET, the channel thickness a is exceeded by the depletion layer due to the spread of the depletion layer width toward the n-type SiC film due to the diffusion potential of the pn junction. For this purpose, for example, the n-type SiC film 3 including the channel region has an n-type impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a channel region thickness a of 500 nm or less. The operation of this normally-off JFET is performed as follows.
(B-1): When off, that is, when the potential of the gate electrode is zero, a diffusion voltage is applied at the gate junction, and a depletion layer is generated. In this junction, the impurity concentration of the p-type SiC film is increased to suppress the depletion layer when the reverse bias voltage is applied to the (L) stacked junction. For this reason, as a matter of course, since the n-type impurity concentration in the channel region is higher than that of the channel region, the depletion layer extends widely toward the channel region, and the width extending toward the p-type SiC film is small. For this reason, only the channel region can be blocked by the depletion layer by adjusting the impurity concentration. As a result, an off state is realized.
(B-2): When ON, that is, when the gate voltage is positive, a forward bias voltage is applied to the (G) gate junction, a depletion layer is not generated, and an ON state is realized. When the potential of the gate electrode becomes positive, a reverse bias voltage is applied to the (L) laminated junction. However, by increasing both the p-type impurity concentration of the p-type SiC film and the n-type impurity concentration of the n-type SiC substrate, the width of the depletion layer is reduced and a current flows due to the tunnel effect. As the above-mentioned high impurity concentration, for example, the n-type SiC substrate has an n-type impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ , and the p-type SiC film has a p-type impurity concentration of 1 × 10 ¹⁹ cm ^−3. To the extent. In addition, since the impurity concentration is increased as described above, the breakdown voltage of the junction portion may be reduced, the breakdown voltage may be lost, and a current may flow. For this reason, the depletion layer at the junction hardly affects the on / off operation of the JFET.
[0026]
With the configuration of the JFET in the first embodiment, an electron with high mobility is used as a carrier in the channel region, and an n-type SiC substrate with a low defect density is used. With a high yield, high power and high switching speed. A JFET can be fabricated. The yield of the JFET in the present embodiment at the prototype stage was as follows. For comparison, the yield of a conventional JFET is also shown.
Example of the present invention: Fabrication on an n-type SiC substrate (Embodiment 1): Yield 90%
Conventional example: Fabrication on a p-type SiC substrate: 10% yield
From the above results, it can be seen that the yield of the JFET in the present embodiment is dramatically improved as compared with the conventional example.
[0027]
(Embodiment 2)
FIG. 2 is a cross-sectional view showing a JFET according to the second embodiment. In the present embodiment, the gate electrode 13 is arranged on the back side of the n-type SiC substrate 1, which is largely different from the JFET of the first embodiment. The operations and functions related to the other parts are the same as the operations and functions shown in the first embodiment. In the present embodiment, since the gate electrode 13 is disposed on the back surface of the n-type SiC substrate, the channel region 4 can be seen from the gate electrode 13 linearly and widely from the front. For this reason, since the signal applied to the gate electrode is transmitted linearly and widely to the channel region, the on / off operation can be performed at high speed. That is, a high-speed switching element can be realized. Compared with the arrangement of the gate electrode in the first embodiment, the planar size is smaller in the JFET of the second embodiment, and the arrangement is three-dimensional. For this reason, it becomes possible to improve the integration degree of JFET.
[0028]
(Embodiment 3)
FIG. 3 is a cross-sectional view showing a JFET according to the third embodiment. FIG. 4 is a cross-sectional view of a JFET for comparison. In the present embodiment, the end face 21 of the p-type SiC film 2 and the end face 22 of the n-type SiC film 3 that is an upper layer thereof are shifted, and the former is positioned inward of the latter in plan view. . On the other hand, in FIG. 4, both end faces are formed as a uniform end face 20. In the case of the end face 20, when etching is performed by RIE, the end face 20 may be exposed to ions during the RIE period, and the crystal may be damaged. In contrast, in the case of the end face structure shown in FIG. 3, the end face of the n-type SiC film is etched by the first etching A, but the inner portion is etched and exposed by the second etching B. As such, the portion is exposed to the ionic atmosphere for only a short period of time. For this reason, the possibility that the crystal near the end face 22 is damaged by ions is very low. For this reason, it is possible to obtain a JFET having excellent transistor characteristics while ensuring a high yield by a simple method.
[0029]
Although the JFET shown in FIG. 3 has a back gate structure, a JFET having a structure in which the gate is arranged beside the channel as shown in FIG. 5 is also a powerful structure of this embodiment. That is, by adopting the structure shown in FIG. 5, it is possible to obtain a high-yield JFET without damaging the surface crystal at the end.
[0030]
While the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.
[0031]
【The invention's effect】
According to the present invention, an SiC JFET having a channel region using electrons with high mobility can be obtained using an n-type SiC substrate that provides high yield. This JFET can be used for high-power high-speed switching elements and the like, and is expected to contribute to power saving and the like.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a JFET according to a first embodiment.
FIG. 2 is a cross-sectional view of a JFET according to a second embodiment.
FIG. 3 is a cross-sectional view of a JFET according to a third embodiment.
4 is a cross-sectional view of a JFET for comparison with a JFET in Embodiment 3. FIG.
FIG. 5 is a cross-sectional view of another JFET according to the third embodiment.
FIG. 6 is a cross-sectional view of a conventional JFET.
[Explanation of symbols]
1 n-type SiC substrate, 2 p-type SiC film, 3 n-type SiC film, 4 channel region, 5 source region (n + -type impurity region), 6 drain region (n + -type impurity region), 11 source electrode, 12 drain Region, 13 gate electrode, 20 end surface where the ends of the p-type SiC film and n-type SiC film are aligned, 21 end surface of the p-type SiC film, 22 end surface of the n-type SiC film, a channel region thickness, A first RIE Position, B Second RIE position.

Claims (5)

an n-type SiC substrate;
A p-type SiC film formed on the front surface of the n-type SiC substrate;
An n-type SiC film including a channel region formed on the p-type SiC film;
Source and drain regions formed on the n-type SiC film and separately formed on both sides of the channel region,
A gate electrode provided in contact with the n-type SiC substrate,
P-type impurity concentration of such current flow exits the depletion layer by the tunnel effect, n-type impurity concentration of the n-type SiC substrate and the p-type SiC layer between the n-type SiC substrate and the p-type SiC film A junction field effect transistor. The junction field effect transistor according to claim 1, wherein the gate electrode is formed on a back surface of the n-type SiC substrate and has a back gate structure. an n-type SiC substrate;
A p-type SiC film formed on the front surface of the n-type SiC substrate;
An n-type SiC film including a channel region formed on the p-type SiC film;
Source and drain regions formed on the n-type SiC film and separately formed on both sides of the channel region,
A gate electrode provided in contact with the n-type SiC substrate,
A junction field effect transistor, wherein the gate electrode is disposed on a front surface of the n-type SiC substrate and close to an end of the p-type SiC film. In plan view, the p-type includes a region of the n-type SiC layer in the region of the SiC film, junction field effect transistor according to any one of claims 1-3. The thickness of the channel region, and the p-type SiC film, than the width of the depletion layer in the n-type SiC layer by diffusion potential at the junction between the n-type SiC film formed on of the p-type SiC film small, junction field effect transistor according to any one of claims 1-4.

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