JPH1092845A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a field effect transistor having a low loss, low distortion and gentle change of the resistance or mutual conductance to the gate voltage variation by providing a gate region composed of parts different in threshold voltage. SOLUTION: The field effect transistor comprises a gate electrode 3 for controlling a main current flowing between a source and drain regions 41, 42. The Schottky gate electrode 3 has a part not contacted to the surface of a channel region 4 between the source and drain regions 41, 42 and a gap having a narrow width enough to be a cut off state by extending a depletion layer. The gate region is composed of parts different in threshold voltage. This reduces the parasitic capacitance with the gate electrode 3, unlike the case of changing the gate length to control the threshold voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor, and more particularly, to a transistor having a gradual change in differential resistance of a current flowing between a source and a drain with respect to a change in a gate-source voltage. Related to effective technology to do.

[0002]

2. Description of the Related Art There is an increasing demand for an inexpensive and highly controllable variable attenuator used for controlling the output power of terminal equipment in mobile communication such as a cellular phone. Conventional S
Compared with a variable attenuator using an i-pin diode, a variable attenuator using a compound semiconductor field-effect transistor (FET) such as GaAs as a variable resistor has advantages that power consumption is small and further miniaturization is possible. I have.

However, since it is necessary to reduce the on-resistance as much as possible in order to obtain a low insertion loss, a drain (Id) current-gate voltage (Vgs) characteristic (hereinafter, referred to as an "I _d -V _gs characteristic") of an FET used as a variable resistor. ") Is required to have a characteristic having a steep slope as shown in FIG. 13A, and the cutoff characteristic also shows a steep characteristic. Therefore, when the control value is set near the threshold voltage shown in FIGS. 13A and 13B, not only does the controllability deteriorate, but also the gate voltage fluctuates due to the feedback capacitance between the gate and the drain, causing large distortion. There was a problem that occurs.

[0004] In order to solve such a problem, in the 1996 IEICE General Conference C-492 "Low distortion of GaAs variable attenuator using two-stage gate length FET", if a structure in which FETs with different threshold voltages are connected in parallel is adopted. It has been reported that low distortion can be achieved. As a method of realizing FETs having different threshold voltages, a multi-stage gate length field effect transistor in which FETs having different gate lengths are connected in parallel as shown in FIG. 14 has been proposed. However, in the case of such a configuration in which the threshold voltage is controlled by changing the gate length, the FET having the shortest gate length becomes dominant in the main current region. The long part is inevitably provided in the FET,
This results in an increase in parasitic capacitance caused by the gate electrode area. Such a parasitic capacitance lowers the performance of the FET in a high-frequency region, and also acts as a large feedback, thereby reducing the effect of reducing distortion.

[0005]

In the method of realizing a variable attenuator or the like using a field effect transistor (FET) as a variable resistor as described above, the I _d -V _gs characteristics are steep due to the need to reduce the on-resistance. There is a problem that a large cutoff characteristic appears and a large distortion occurs. In order to achieve low distortion, it has been proposed to adopt a configuration in which FETs having a plurality of gate lengths are connected in parallel. However, in order to change the gate length, a gate capacitance is inevitably large (e.g., having a long gate length). In addition, since the FET is provided in the element, problems such as deterioration of the frequency characteristics and a reduction in the effect of suppressing distortion occur.

[0006] The present invention is a low loss without deterioration of such a high-frequency characteristic, moreover, low distortion, resistance to changes in the gate voltage, or to provide a gradual FET changes transconductance g _m Aim.

[0007]

To achieve the above object, a field effect transistor (FET) according to the present invention comprises a source region, a drain region, and a gate region for controlling a main current flowing between the source region and the drain region. Wherein the gate region comprises a plurality of portions having different threshold voltages. Here, the FET may be a junction gate type, an insulated gate type such as a MOSFET as shown in FIG. 11, or a Schottky gate FET such as a MESFET as illustrated in FIGS. Further, the HEMT as shown in FIG. 12 is also included in the FET according to the present invention.

In the case of the MESFET, the FE of the present invention
T may have a structure in which the Schottky gate electrode 3 has a portion (gap portion) between the source region 41 and the drain region 42 that does not partially contact the surface of the channel region 4 as shown in FIG.

The width W _d of the depletion layer formed at the metal / semiconductor interface in the Schottky junction is

(Equation 1) Is known to be given by Here, V is the maximum voltage applied to the Schottky junction (that is, the gate breakdown voltage), φ ₀ is the difference in work function between the metal and the semiconductor, N is the impurity density of the channel region, and ε is the dielectric constant of the semiconductor in the channel region. It is. Therefore, in order to exhibit the features of the present invention in the structure of FIG. 1, the depletion layer in the gap portion may be pinched off in order by different gate applied voltages as shown in FIGS. Specifically S ₁ portions n ₁ point size of the gap portion, the dimension S ₂ portions of the gap portion n
_Two places, n ₃ places where the dimension of the gap is S ₃ , ...
... If the size of the gap portion is the portion n _n locations S _n, the total length of the portion where the gate electrode (Schottky metal) is in contact with the channel is g

(Equation 2) And it is preferable to satisfy the following condition: 2W _d > S _n > S _n-1 >...> S ₁ (3)

[0010] That is, the width S ₁ of the gap formed in the gate electrode, S _2, ...... since S _n is may be set narrow to a degree sufficient to become a cut-off state by the depletion layer extending is there. In addition, it is preferable that the space is designed so that the total length of the wide portion does not exceed the total length of the narrow portion. This is derived from the fact that the I _d -V _gs characteristic of the transistor or the air gap having the higher g _m becomes dominant at an arbitrary gate bias.

In a normal FET, the width of the gate electrode provided between the source and drain electrodes is set so as to be equal to or greater than the so-called channel width W. The channel width is a dimension of the channel measured in a direction perpendicular to the direction of the main current flowing between the source and the drain. In the structure illustrated in FIG. 1, a structure is adopted in which a part of the gate electrode 3 is provided so as not to contact the surface of the semiconductor layer 4. In such a portion where the Schottky gate electrode 3 is not in contact with the semiconductor surface, a current should naturally flow regardless of the gate voltage. However, the current path formed in the portion where the gate electrode 3 does not contact is such that the gate voltage exceeds a predetermined value by pinch-off of the depletion layer 6 extending from the portion where the gate electrodes 3 on both sides contact as shown in FIG. When a large voltage is applied, the resistance increases,
The current stops flowing. Due to the effect of the gate bias, the semiconductor layer 4 on which the gate electrode 3 is not provided also functions as a channel region of the FET under a constant gate voltage. Therefore, a parallel arrangement structure of transistors having different threshold voltages equivalently can be realized by the structure shown in FIG. In this case, the threshold voltage depends on the length of the gap where the gate electrode is not in contact with the semiconductor surface, but the area occupied by the gate electrode contributing to the gate capacitance is the conventional MESFET formed by contacting the entire surface of the gate electrode. It has a structure that is reduced as compared with. Thus the structure illustrated in FIG. 1 is different from the case but is intended to slightly reduce the mutual conductance g _m of controlling the threshold voltage of the gate length is varied as shown in FIG. 14, the parasitic capacitance C _g by the gate electrode It is possible to make it smaller. As a result g
can suppress a decrease in _{m /} C _g, the low loss without deteriorating the outstanding high-frequency characteristics can be realized a variable attenuator low distortion.

Further, when such a configuration is used, as shown in FIG. 3A, currents S ₁ , S ₂ ,... Flowing through portions where the gate electrodes are not in contact are in contact with the gate electrodes. Since the cut-off characteristic is more gradual than the I _d -V _gs characteristic of the current g flowing immediately below the portion, the change in the resistance value with respect to the gate voltage also becomes more gradual. Therefore, FIG.
As shown in (a), I _d -V _gs characteristics as a whole also becomes gentle. Therefore, if this MESFET is used as a variable attenuator, its controllability can be further improved.

Needless to say, the FET realized in this manner requires a wide range of resistance value change. In that case, it is necessary to maintain a high transconductance (g _m ). However, if the configuration is made so as to satisfy the equations (2) and (3), a higher g _m at a given bias point can be obtained. This is preferable because the channel portion having the same becomes dominant. Because the width S ₁ of the portion where the gate electrode is not formed in contact, S _2, it is g _m as a whole ...... is the wider is lowered. Also, as the widths S ₁ , S ₂ ,... Of the portions where the gate electrodes are not formed in contact with each other are wider, the drain conductance (g _D ) as a whole also increases, thereby deteriorating high frequency characteristics. is there.

The specific method for achieving the features of the present invention is not limited to the structure shown in FIG. 1, but may be, for example, a structure shown in FIGS. That is, a method of changing the metal material forming the gate electrode as shown in FIG. 7, a method of changing the depth of the recess etching applied to the portion where the gate electrode is formed as shown in FIG. 8, and a method shown in FIG. A method of changing the impurity concentration in the semiconductor layer immediately below the gate electrode may be used. Either method can provide a field effect transistor whose resistance value changes slowly with respect to a change in gate bias without a significant increase in parasitic capacitance due to the gate electrode. Similarly, in the MOSFET as shown in FIG. 11 and the HEMT as shown in FIG. 12, moderate I _{d to} V _gs characteristics can be obtained.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a bird's-eye view showing a basic structure of the FET according to the first embodiment of the present invention. On the active layer 4 formed on the semi-insulating GaAs substrate 5 into which the n-type impurity has been introduced, an n ⁺ source region 41 and a drain region in which the n-type impurity has been introduced at a higher impurity density than the active layer 4 42 are formed. The source electrode 11 is located above the source region 41, and the drain electrode 12 is located above the drain electrode 42.
Is formed at the top. As shown in FIG. 1, a part of the gate electrode 3 is formed apart from the active layer 4, and the width of this part determines the threshold value. 2 (a) to FIG.
(C) shows the cross-sectional structure of the gate portion cut in a direction perpendicular to the direction in which the current flows, for various gate voltages. When the gate voltage shown in FIG. 2A is not applied, the depletion layer 6 does not protrude greatly into the channel region 4 immediately below the portion where the gate electrode 3 is not in contact with the gate electrode 3, and the gate current is in contact therewith. It is in a state where a large current flows as compared with the portion where the current flows. In contrast, FIG.
When the gate voltage gradually increases to a negative value as shown in (b) and (c), the depletion layer 6 reaches the semi-insulating GaAs substrate 5, and thereafter the depletion layer further contacts the gate electrode. The depletion layers are pinched off at a voltage corresponding to the width of each gap, and the resistance is increased, so that the current is cut off. I _d such overall I _d -V _gs characteristics of the field effect transistor having different slopes, as shown in FIG. 3 (a)
.. -V _gs characteristics g, S ₁ , S ₂ ..., And the on-resistance is reduced and the differential resistance is gradually changed. Yet, it is possible to reduce the gate parasitic capacitance C _g, g _m is a decrease in the g _{m /} C _g although slightly lowered can be suppressed to a sufficiently small value as a whole,
A variable resistor exhibiting excellent high-frequency characteristics can be realized.

The MESFET shown in FIG. 1 can be manufactured as follows.

(A) As shown in FIG.
An n-type GaAs layer 4 is formed on an aAs substrate 5 by epitaxial growth. The n-type GaAs layer 4 is formed by MOCV
D method MBE method, CBE method (Chemical Beam)
Eitaxy method), ALE method (Atomic Ray)
er Epitaxy method) or MLE method (Mole
A well-known epitaxial growth technique such as a color layer epitaxy method may be used. n-type GaAs
The impurity density of the s layer 4 is, for example, 5 × 10 ^{16 to} 5 × 10 ¹⁷
cm ⁻³ and a thickness of 0.3 μm to 5 μm.

(B) Next, using an electron beam (EB) lightning device, as shown in FIG.
A pattern of a photoresist 31 having a thickness of 5 μm and a length of 1 to 3 μm is formed.

(C) Next, the photoresist shown in FIG. 4 (b) is cured at a high temperature to cause sagging so as to form a semi-cylindrical shape as shown in FIG. 5 (c).

(D) Next, as shown in FIG. 5D, a pattern of the gate electrode 3 of platinum (Pt) or the like is formed. The gate electrode 3 may be patterned by a lift-off method or by an RIE method using a resist mask pattern as an etching mask. Since the photoresist 32 is cured at a high temperature, it remains in the resist stripping step after patterning in FIG. 5D.

(E) Next, the photoresist 32 is removed by ozone (O ₃ ) ashing, and using the gate electrode 3 from which the photoresist 32 has been removed as a mask, ⁷⁹ Se ⁺ or ²⁸ Se as shown in FIG. An n-type impurity such as Si ⁺ is ion-implanted. For example, it may be performed at an acceleration voltage of 35 to 50 KeV and a dose of 3 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ⁻² .

(F) Thereafter, annealing is performed while applying an As pressure to activate the implanted ions such as ⁷⁹ Se ⁺ to form n ⁺ source region 41 and n ⁺ drain region 42. Then, AuGe / Ni /
By patterning the source electrode 11 and the drain electrode 12 such as a Ti / Au film, the MESFET of the first embodiment of the present invention shown in FIG. 1 is completed.

Incidentally, as shown in FIG.
2 may be left without removing the shape shown in FIG. FIG. 5E shows the shape shown in FIG.
Is performed, the effective channel length l _{eff in} the gap between the gate electrodes becomes longer, which is more effective.

Further, the shape of the gate gap is not limited to the kamaboko type as shown in FIG. It may be a rectangle as shown in FIG.
In FIG. 6, SiO ₂ , PSG, BP
The shape in which an insulator 36 such as SG or Si ₃ N ₄ is left is shown. However, the insulator 36 is removed and a gap (ai) is formed.
r gap) may of course be used. P
In the case of using SG or BPSG, after patterning as shown in FIG.
It is also possible to make the shape as shown in FIG. Therefore, the shape shown in FIG. 1 may be a shape in which PSG or BPSG is embedded in the gap.

In FIG. 1, the n ⁺ source region 41 and the n ⁺ drain region 42 may be omitted, and the source electrode 11 and the drain electrode 12 may be in direct contact with the n-type GaAs layer 4. However, it is needless to say that it is preferable to form the n ⁺ source region 41 and the n ⁺ drain region 42 in order to reduce the ON resistance of the MESFET.

FIG. 7 shows an MES having a plurality of channel regions having different threshold voltages according to a second embodiment of the present invention.
FIG. 8 is a cross-sectional view when the FET is realized with different gate electrode materials (FIG. 7 is a cross-sectional view cut in a direction perpendicular to the current direction). Source / drain electrodes are formed on the n-type active layer 4 on the semi-insulating GaAs substrate 5, and as shown in FIG. 7, a platinum (Pt) layer 9b, a molybdenum (Mo) layer 9c, and a titanium (Ti) layer 9d. The gate electrode is made of a metal material having a work function different from that of the gate electrode. Pt layer 9b, Mo layer 9c,
The Ti layer 9d is connected by a gold (Au) layer 9a.
Thus, the materials having different work functions have different Schottky barrier heights, so that different threshold voltages can be realized.

FIG. 8 shows a recess (groove) in which different threshold voltages are applied immediately below the gate electrode 3 according to the third embodiment of the present invention.
FIG. 4 is a cross-sectional view (a cross-sectional view cut in a direction perpendicular to the current direction) of a gate portion of the FET realized by changing the depth of the FET. In FIG. 8, a transistor is formed using n-type active layer 4 on semi-insulating GaAs substrate 5 as a channel region. In the figure, in the step of recess etching the location where the gate electrode 3 is formed, lithography technology is used in combination to repeatedly implement stepwise recess etching of different depths by RIE, ECR ion etching, wet etching, or the like. . Since the threshold voltage changes in the positive direction as the depth of the recess etching increases, different threshold voltages can be realized.

FIG. 9 shows an MES having a plurality of channel regions having different threshold voltages according to a fourth embodiment of the present invention.
FIG. 4 is a structural diagram (plan view) in a case where the FET is realized by changing the impurity density (channel impurity density) introduced into the active layer. An n-type active layer is formed on a semi-insulating GaAs substrate by implanting impurity ions. The impurity density of a portion 62 where a gate electrode 3 serving as a channel region is formed is indicated by 62a, 62b,. And stepwise. The threshold voltage changes depending on the difference in channel impurity density, and a plurality of channel regions having different threshold voltages are realized.

FIG. 10 shows a basic structure of a dual-gate field-effect transistor according to a fifth embodiment of the present invention. A case of applying a MESFET having a change of gradual g _m shown in the first to fourth embodiments a dual gate field effect transistor. The dual-gate field-effect transistor is an electric MESFET in which two gate electrodes are formed between the source electrode 11 and the drain electrode 12, and the gain of the MESFET obtained by changing the bias of one gate electrode is used to change the gain of the other MESFET. It is a transistor that can be controlled by A dual-gate MESFET can be equivalently represented by a series connection of two MESFETs.
It is known that the gain obtained by T is approximately given in a form proportional to the product of g _m of the two transistors. That is, as shown in FIG. 10, at least one of the gates of the dual-gate transistor has the structure as shown in the first to fourth embodiments of the present invention, so that the g The change of _m is realized, and the controllability of the gain can be improved. FIG.
At 0, the source electrode 11 and the drain electrode 12 are in direct contact with the n-type GaAs layer 4, but as shown in FIG. 1, an n ⁺ source region and an n ⁺ drain region are formed immediately below the source electrode 11 and the drain electrode 12. Of course, it is preferable to provide them.

FIG. 11 is a bird's-eye view showing a basic structure of a MOSFET according to a sixth embodiment of the present invention. P layer formed on the p ⁺ silicon substrate 55 in FIG. 11 n ⁺ source region 41 and n ⁺ drain region 42 on top of the (p-type silicon layer) 42 is formed, n ⁺ source region 41 and the n ⁺ P layer 42 between drain regions 42 as a channel region, and a thickness of 30 nm
A gate oxide film 38 having a thickness of about 100 nm is formed. On the gate oxide film 38, insulating films 36a and 36b different from the gate oxide film are formed, and the insulating films 36a and 36b are formed.
b, doped polysilicon, W, WSi
Gate electrodes 3 such as ₂ are formed. Al, Al—S is formed on the n ⁺ source region 41 and the n ⁺ drain region 42.
A source electrode 11 and a drain electrode 12 made of a metal such as i are formed.

With the structure shown in FIG. 11, a plurality of MOSFETs having substantially different gate oxide films (36a, 36b, 38) are formed between the source electrode 11 and the drain electrode 12. That is, MOSFETs having different threshold values V _th are connected in parallel, and the overall I _d -V _gs characteristics can be obtained as gradual characteristics as the characteristics shown in FIG. In the sixth embodiment of the present invention, the thicknesses of the insulating films 36a and 36b, the dielectric constants of the insulating films 36a and 36b, and the insulating films 36a and 36b shown in FIG.
36b, that is, by changing any of the pattern widths measured in the direction perpendicular to the channel direction, the desired I
_d- V _gs characteristics can be obtained. Also, as shown in FIG. 8, as a recess gate MOSFET similar to the recess structure, by changing the depth of the recess, or by selecting an electrode material so as to change the impurity density of the channel region as a MOSFET similar to the structure shown in FIG. The threshold can also be changed. Also, the threshold value may be changed by selecting a structure in which the gate electrode 3 is partially made of n ⁺ doped polysilicon and making the remaining p ⁺ doped polysilicon, or by selecting an electrode material so as to change the work function of the gate electrode. Can be. Further, a dual-gate MOSFET similar to FIG. 10 may be used.

FIG. 12 shows an HE according to a seventh embodiment of the present invention.
It is a bird's-eye view of MT. In FIG. 12, semi-insulating GaAs
An undoped GaAs layer or an n-type GaAs layer 4 is formed on a substrate 5, and an n ⁺ Al _0.3 Ga _0.7 As layer 44 is formed thereon. n-type GaAs layer 4 and n ⁺ Al
_A hetero junction is formed with the _0.3 Ga _0.7 As layer 44, and a two-dimensional electron cloud is formed in the n-type GaAs layer 4 at the hetero junction interface. n ⁺ Al _0.3 Ga _0.7 from the surface of the As layer 44 to reach the nGaAs layer 4 deep n ⁺⁺ source regions 4
A 1, n ⁺⁺ drain region 42 is formed. AuGe is formed above the n ⁺⁺ source region 41 and the n ⁺⁺ drain region 42.
A source electrode 11 and a drain electrode 12 of / Ni / Au or the like are formed. On the surface of the n ⁺ Al _0.3 Ga _0.7 As layer 44, an insulating film 36 such as Si ₃ N ₄ , SiO ₂ , polyimide film or the like is partially formed, and further thereon, Pt or WSi
Gate electrodes 3 such as ₂ are formed. The presence of the insulating film 36 is equivalent to connecting a plurality of HEMTs having different threshold values in parallel between the source electrode 11 and the drain electrode 12, and a gradual I _d -V _gs characteristic can be obtained.

The HEMT shown in FIG.
A HEMT using another hero junction such as GaP / InGaAs HEMT may be used. Further, it goes without saying that a complicated structure including a buffer layer / dislocation suppression layer / channel layer / spacer layer / electron supply layer / ohmic contact layer and the like may be used instead of the simple layer structure shown in FIG. The threshold value can also be changed by changing the thickness of any one of the channel layer, the spacer layer, the electron supply layer, and the like. Further, a HEMT to which a gate structure similar to the gate structure described in the second to fourth embodiments is applied may be used. It is also possible to use a dual gate HEMT.

[0034]

As described above, according to the present invention,
It is possible to realize a characteristic in which the resistance value changes gradually with respect to the gate bias without deteriorating the frequency characteristic, and it is possible to improve the controllability. Such a gradual change can also reduce distortion due to feedback due to parasitic capacitance.

Further, by applying a similar structure to a dual gate transistor, a change in gain with respect to a gate control voltage can be made gentle, and high controllability can be realized.

Field effect transistor (FET) of the present invention
When used as a variable resistor, a variable attenuator with low loss and low distortion can be realized.

[Brief description of the drawings]

FIG. 1 is a MESFET according to a first embodiment of the present invention.
FIG. 2 is a bird's-eye view showing a structural diagram of the first embodiment.

FIG. 2 is a cross-sectional view showing a change in a depletion layer near a gate electrode due to a gate bias.

FIG. 3 is a MESFET according to a first embodiment of the present invention.
This is an example of the characteristics.

FIG. 4 is a MESFET according to the first embodiment of the present invention.
FIG. 6 is a process chart (part 1) for explaining the manufacturing method of FIG.

FIG. 5 is a MESFET according to the first embodiment of the present invention.
FIG. 7 is a process diagram (part 2) for explaining the manufacturing method shown in FIG.

FIG. 6 is a MESFET according to the first embodiment of the present invention.
3 is another structural example.

FIG. 7 shows a MESFET according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view of the gate portion of FIG.

FIG. 8 shows a MESFET according to a third embodiment of the present invention.
FIG. 4 is a cross-sectional view of the gate portion of FIG.

FIG. 9 shows a MESFET according to a fourth embodiment of the present invention.
3 is a plan view of a gate portion of FIG.

FIG. 10 is a bird's-eye view of a dual-gate field-effect transistor according to a fifth embodiment of the present invention.

FIG. 11 shows a MOSFE according to a sixth embodiment of the present invention.
It is a bird's-eye view of T.

FIG. 12 is a bird's-eye view of a HEMT according to a seventh embodiment of the present invention.

FIG. 13 shows characteristics of a conventional MESFET.

FIG. 14 is a configuration diagram (plan view) of a conventional multi-stage gate length MESFET.

[Explanation of symbols]

Reference Signs List 3 gate electrode 4 n-type active layer 5 semi-insulating GaAs substrate 6 depletion layer 7 first gate electrode 8 gate electrode for gain control (second gate electrode) 9 gate electrode 9a gold electrode 9b platinum electrode 9c molybdenum electrode 9d titanium electrode 10 Multi-stage recess structure 10a One-stage recess portion 10b Two-stage recess portion 11 Source electrode 12 Drain electrode 13 Multi-stage gate length portion 31 Photoresist (before cure) 32 Photoresist (after cure) 36, 36a, 36b Insulating film 38 Gate oxide film 41 n ⁺ Source region 42 n ⁺ drain region 44 n ⁺ AlGaAs layer 54 p layer (p-type silicon layer) 55 p ⁺ silicon substrate 61 n-type active layer 62 high-concentration ion-implanted portion 62 a, b impurity density change region

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/808

Claims (1)

[Claims] 1. A field effect transistor comprising at least a source region and a drain region, and a gate region for controlling a main current flowing between the source region and the drain region, wherein the gate regions have different threshold voltages. A field effect transistor comprising a plurality of parts.