JP2001168491A - Printed wiring board, and manufacturing method therefor - Google Patents

Printed wiring board, and manufacturing method therefor

Info

Publication number
JP2001168491A
JP2001168491A JP35050099A JP35050099A JP2001168491A JP 2001168491 A JP2001168491 A JP 2001168491A JP 35050099 A JP35050099 A JP 35050099A JP 35050099 A JP35050099 A JP 35050099A JP 2001168491 A JP2001168491 A JP 2001168491A
Authority
JP
Japan
Prior art keywords
conductive
wiring layer
passive element
conductor
base material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP35050099A
Other languages
Japanese (ja)
Other versions
JP3964085B2 (en
Inventor
Hideki Kato
秀樹 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP35050099A priority Critical patent/JP3964085B2/en
Publication of JP2001168491A publication Critical patent/JP2001168491A/en
Application granted granted Critical
Publication of JP3964085B2 publication Critical patent/JP3964085B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board for manufacturing a multilayer board with a high degree of integration in less manufacturing processes and wide design width when mounting parts, and the printed wiring board. SOLUTION: In this method for manufacturing a multilayer plate by the conductor bump penetration method, interlayer connection between a wiring layer 1a and a wiring layer 5a on the upper and lower surfaces of a multilayer board 7a is formed by forcing a group of conductor bumps 2, 2, etc., nearly in a conical shape formed by a conductive composition in the direction of the thickness of the multilayer board 7a, a dielectric composition or a resistive composition is applied onto a conductor plate 5 at a side for applying the group of conductor bumps 2, 2, etc., before drying, and a passive element member 6 is formed, and the passive element member is inserted into the gap between specific, adjacent conductor bumps 2a and 2b when applying the groups of conductive bumps 2, 2, etc. By bringing the conductor bumps 2a and 2b into contact each other, near both the ends of the passive element member 6, a passive element such as a capacitor C and a resistor R is formed in the multilayer board 7a.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、プリント配線基板
に係り、更に詳細には、複数の配線層間の電気的な導通
が形成された多層板、及びそのような多層板の製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly, to a multilayer board having electrical conduction between a plurality of wiring layers and a method for manufacturing such a multilayer board.

【0002】[0002]

【従来の技術】従来より、複数の絶縁性基材が積層され
た基板間に複数の配線層が介挿された、いわゆる多層板
では、層間接続する方法として導電性ビアやスルホール
メッキ層などの導電性部材を基板の厚さ方向に埋設する
方法が知られている。
2. Description of the Related Art Conventionally, in a so-called multi-layer board in which a plurality of wiring layers are interposed between substrates on which a plurality of insulating base materials are laminated, as a method of interlayer connection, a conductive via or a through-hole plating layer is used. There is known a method of burying a conductive member in a thickness direction of a substrate.

【0003】その中でも、印刷技術を用いる導体バンプ
貫通法は製造工程の点から着目されている。図39は導
体バンプ貫通法の製造工程を示した垂直断面図である。
この導体バンプ貫通法では、銅箔などの導体板101の
上に印刷技術により銀ペーストなどの導電性組成物を用
いて略円錐形の導体バンプ群102,102,…を形成
し、この導体バンプ群102,102,…の上に絶縁性
基材プリプレグ103と、更にその上に別の導体板10
4を重ね、この状態でローラープレスなどによりプレス
して導体バンプ群102,102,…を絶縁性基材プリ
プレグ103に貫通させると同時に導体バンプ群10
2,102,…の先端側を導体板104に当接させるこ
とにより前記導体板101と導体板104との間で層間
接続を形成する。
[0003] Among them, the conductor bump penetration method using a printing technique has attracted attention from the viewpoint of a manufacturing process. FIG. 39 is a vertical sectional view showing the manufacturing process of the conductor bump penetration method.
In this conductor bump penetration method, substantially conical conductor bump groups 102, 102,... Are formed on a conductor plate 101 such as a copper foil by a printing technique using a conductive composition such as a silver paste. The insulating base material prepreg 103 is provided on the groups 102, 102,.
4 are pressed by a roller press or the like in this state to allow the conductive bump groups 102, 102,.
By contacting the tip sides of 2, 102,... With the conductor plate 104, an interlayer connection is formed between the conductor plate 101 and the conductor plate 104.

【0004】この多層板に各種素子を実装するには多層
板の最外層である導体板101又は104上に最外層と
しての配線層101a,104aをそれぞれ形成し、こ
の最外側の配線層に素子を固定したり、結線する。
In order to mount various elements on this multilayer board, wiring layers 101a and 104a as outermost layers are respectively formed on the conductor plate 101 or 104 which is the outermost layer of the multilayer board, and the element is formed on the outermost wiring layer. Fix or connect.

【0005】そのため、多層板の最外側の表面は平坦で
あることが望ましく、表面が平坦な多層板が形成できる
点で導体バンプ貫通法は導電性ビアを形成する方法やス
ルーホールメッキ層などを形成する方法に比べて有利で
ある。
[0005] Therefore, it is desirable that the outermost surface of the multilayer board is flat, and in that a multilayer board having a flat surface can be formed, the conductor bump penetration method employs a method of forming conductive vias and a through-hole plating layer. This is advantageous as compared with the forming method.

【0006】ところで、携帯電話や各種情報端末装置の
小型軽量化に伴い、ますます半導体部品の小型化が望ま
れており、それには更なる半導体部品の集積度の向上が
必須である。
[0006] By the way, with the reduction in size and weight of mobile phones and various information terminal devices, the miniaturization of semiconductor components is increasingly desired, and it is essential to further improve the degree of integration of semiconductor components.

【0007】[0007]

【発明が解決しようとする課題】しかし、上記従来のよ
うな半導体部品を最外層に実装する多層板では多層板の
面積自体が小型化される傾向にあるため、集積度の向上
にも自ずと限界がある。
However, in the above-described conventional multilayer board in which semiconductor components are mounted on the outermost layer, since the area of the multilayer board itself tends to be reduced, the degree of integration is naturally limited. There is.

【0008】そのため、半導体部品の一部を多層板の内
部に埋め込む方法が提案されている。例えば、特開平5
−343855号公報や特開平9−214090号公報
などには抵抗体などの受動素子を多層板の厚さ方向に穿
孔した貫通孔内に埋め込む方法が開示されている。
Therefore, a method of embedding a part of a semiconductor component in a multilayer board has been proposed. For example, Japanese Unexamined Patent Publication
JP-A-343855 and JP-A-9-214090 disclose a method of embedding a passive element such as a resistor in a through hole formed in a thickness direction of a multilayer board.

【0009】しかし、これらの方法では、受動素子を埋
め込むための貫通孔を穿孔する工程とその貫通孔内に受
動素子前駆体を充填する工程が必要となるため、全体の
工数が多く、かえって手間がかかるために製造コスト的
に採算が取れない、という問題がある。
However, these methods require a step of forming a through-hole for embedding a passive element and a step of filling the through-hole with a passive element precursor. However, there is a problem that it is not profitable in terms of manufacturing cost.

【0010】本発明は上記従来の問題を解決するために
なされた発明である。即ち、本発明は、できるだけ少な
い製造工程で集積度が高く、部品実装時のデザインの幅
が広くとれる多層板を製造することのできるプリント配
線基板の製造方法およびそのようなプリント配線基板を
提供することを目的とする。
The present invention has been made to solve the above-mentioned conventional problems. That is, the present invention provides a method for manufacturing a printed wiring board capable of manufacturing a multi-layer board having a high degree of integration with a minimum number of manufacturing steps and a wide design when mounting components, and such a printed wiring board. The purpose is to:

【0011】[0011]

【課題を解決するための手段】本発明のプリント配線基
板の製造方法は、絶縁性基材と、前記絶縁性基材の両面
にそれぞれ配設された第1の配線層及び第2の配線層
と、前記絶縁性基材の厚さ方向に貫通して形成され、前
記第1の配線層と第2の配線層とを接続する導体バンプ
群と、前記第1の配線層と前記第2の配線層との間に複
数の前記導体バンプと接して埋設され、前記複数の導体
バンプの間で受動素子を形成する誘電性組成物又は抵抗
性組成物からなる受動素子部材と、を具備する。
According to the present invention, there is provided a method for manufacturing a printed wiring board, comprising: an insulating base material; and a first wiring layer and a second wiring layer provided on both surfaces of the insulating base material. A conductive bump group formed through the insulating base material in the thickness direction and connecting the first wiring layer and the second wiring layer; and the first wiring layer and the second A passive element member made of a dielectric composition or a resistive composition that is buried in contact with the plurality of conductor bumps between the wiring layers and forms a passive element between the plurality of conductor bumps.

【0012】上記プリント配線基板は以下の方法により
製造される。
The above printed wiring board is manufactured by the following method.

【0013】即ち、本発明のプリン配線基板製造方法
は、第1の導体板上に略円錐形の導体バンプ群を形成す
る工程と、前記導体バンプ群上に絶縁性基材を載置する
工程と、前記第1の導体板と前記絶縁性基材とをプレス
して前記導体バンプ群を前記絶縁性基材に貫通させる工
程と、第2の導体板上に誘電性組成物又は抵抗性組成物
を塗布して受動素子部材を形成する工程と、前記第1の
導体板と前記第2の導体板とを、前記導体バンプ群と前
記受動素子部材とを対向させて載置する工程と、前記第
1の導体板と前記第2の導体板とを前記導体バンプ群の
うちの少なくとも二つが前記受動素子部材と接するよう
にプレスして前記導体バンプ群のうちの少なくとも二つ
の間で受動素子を形成する工程と、前記第1の導体板と
前記第2の導体板とをパターニングしてそれぞれ第1の
配線層と第2の配線層とを形成する工程と、を具備す
る。
That is, in the method for manufacturing a pudding wiring board according to the present invention, a step of forming a substantially conical conductive bump group on a first conductive plate and a step of placing an insulating base material on the conductive bump group Pressing the first conductive plate and the insulating base material to penetrate the conductive bump group through the insulating base material; and forming a dielectric composition or a resistive composition on the second conductive plate. Applying an object to form a passive element member, and placing the first conductor plate and the second conductor plate with the conductor bump group and the passive element member facing each other; The first conductive plate and the second conductive plate are pressed such that at least two of the conductive bump groups are in contact with the passive element member, and a passive element is formed between at least two of the conductive bump groups. Forming the first conductive plate and the second conductive plate Comprising a step of forming the respective first wiring layer and the second wiring layer is patterned, the.

【0014】上記プリント配線基板及びその製造方法に
おいて、前記受動素子部材は前記導体バンプと導体バン
プとの間に配設されていてもよく、前記導体バンプと前
記導体板との間に配設されていてもよく、更に導体バン
プの先端側と前記導体板との間に配設されていてもよ
く、また、導体バンプの底面側と前記導体板との間に配
設されていてもよい。
In the printed wiring board and the method of manufacturing the same, the passive element member may be provided between the conductor bumps, and may be provided between the conductor bumps and the conductor plate. May be further disposed between the tip side of the conductor bump and the conductor plate, or may be disposed between the bottom side of the conductor bump and the conductor plate.

【0015】本発明の他のプリント配線基板製造方法
は、第1の導体板上に略円錐形の導体バンプ群を形成す
る工程と、前記導体バンプ群上に絶縁性基材を載置する
工程と、前記第1の導体板と前記絶縁性基材とをプレス
して前記導体バンプ群を前記絶縁性基材に貫通させる工
程と、第2の導体板上の、前記導体バンプが当接する部
分と前記導体バンプが当接する部分との間に誘電性組成
物又は抵抗性組成物を塗布して受動素子部材を形成する
工程と、前記第1の導体板と前記第2の導体板とを、前
記導体バンプ群と前記受動素子部材とが対向する向きに
載置する工程と、前記第1の導体板と前記第2の導体板
とをプレスして前記導体バンプ群を前記第2の導体板に
当接させ、それにより前記導体バンプと前記受動素子部
材との間で受動素子を形成する工程と、前記第1の導体
板及び第2の導体板とをパターニングしてそれぞれ第1
の配線層と第2の配線層とを形成する工程と、を具備す
る。
According to another method of manufacturing a printed wiring board of the present invention, a step of forming a substantially conical conductive bump group on a first conductive plate and a step of placing an insulating base material on the conductive bump group Pressing the first conductive plate and the insulating base material to penetrate the conductive bump group through the insulating base material; and a portion of the second conductive plate where the conductive bumps abut. And a step of applying a dielectric composition or a resistive composition between a portion where the conductive bumps abut, to form a passive element member, and the first conductive plate and the second conductive plate, Placing the conductive bump group and the passive element member in the facing direction; and pressing the first and second conductive plates to set the conductive bump group to the second conductive plate. A passive element between the conductive bump and the passive element member. And forming, the first of the first respectively by patterning the conductive plate and second conductive plate
Forming a second wiring layer and a second wiring layer.

【0016】このプリント配線基板製造方法により、以
下のプリント配線基板が得られる。即ち本発明の他のプ
リント配線基板は、絶縁性基材と、前記絶縁性基材の両
面にそれぞれ配設された第1の配線層及び第2の配線層
と、前記絶縁性基材の厚さ方向に貫通して形成され、前
記第1の配線層と第2の配線層とを層間接続する導体バ
ンプ群と、前記導体バンプ群の少なくとも二つの導体バ
ンプの間にわたって配設され、前記二つの導体バンプと
の間で受動素子を形成する誘電性組成物又は抵抗性組成
物からなる受動素子部材と、を具備する。
According to the method for manufacturing a printed wiring board, the following printed wiring board is obtained. That is, another printed wiring board according to the present invention includes an insulating base material, a first wiring layer and a second wiring layer respectively provided on both surfaces of the insulating base material, and a thickness of the insulating base material. A conductive bump group formed between the first wiring layer and the second wiring layer for interlayer connection between the first wiring layer and the second wiring layer; A passive element member made of a dielectric composition or a resistive composition forming a passive element between the two conductive bumps.

【0017】本発明の更に別のプリント配線基板製造方
法は、第1の導体板上に略円錐形の第1の導体バンプ群
を形成する工程と、前記第1の導体バンプ群上に第1の
絶縁性基材を載置する工程と、前記第1の導体板と前記
第1の絶縁性基材とをプレスして前記第1の導体バンプ
群を前記第1の絶縁性基材に貫通させる工程と、第2の
導体板上の、前記第1の導体バンプが当接する部分の隙
間に誘電性組成物又は抵抗性組成物を塗布して第1の受
動素子部材を形成する工程と、前記第1の導体板と前記
第2の導体板とを、前記第1の導体バンプ群と前記第1
の受動素子部材とを対向させて載置する工程と、前記第
1の導体板と前記第2の導体板とをプレスして前記第1
の導体バンプ群を前記第2の導体板に当接させ、それに
より前記第1の導体バンプと前記第1の受動素子部材と
の間で第1の受動素子を形成する工程と、前記第1の導
体板及び第2の導体板とをパターニングしてそれぞれ第
1の配線層と第2の配線層とを形成し、第1の積層体を
得る工程と、前記第1の配線層上の、第2の導体バンプ
が当接する部分の隙間に第2の誘電性組成物又は抵抗性
組成物を塗布して第2の受動素子部材を形成する工程
と、第3の導体板上に略円錐形の第2の導体バンプ群を
形成する工程と、前記第2の導体バンプ群上に第2の絶
縁性基材を載置する工程と、前記第3の導体板と前記第
2の絶縁性基材とをプレスして前記第2の導体バンプ群
を前記第2の絶縁性基材に貫通させる工程と、前記第1
の積層体と前記第3の導体板とを、前記第2の受動素子
部材と前記第2の導体バンプ群とを対向させて載置する
工程と、前記第1の積層体と前記第3の導体板とをプレ
スして前記第2の導体バンプ群を前記第1の配線層に当
接させ、それにより前記第2の導体バンプと前記第2の
受動素子部材との間で第2の受動素子を形成する工程
と、前記第3の導体板をパターニングして第3の配線層
を形成する工程と、を具備する。
Still another method of manufacturing a printed wiring board according to the present invention includes a step of forming a first group of substantially conical conductive bumps on a first conductive plate, and a step of forming a first group of conductive bumps on the first group of conductive bumps. Mounting the insulating base material, and pressing the first conductive plate and the first insulating base material to penetrate the first conductive bump group through the first insulating base material. Forming a first passive element member by applying a dielectric composition or a resistive composition to a gap on a portion of the second conductor plate where the first conductor bump abuts, The first conductor plate and the second conductor plate are combined with the first conductor bump group and the first conductor plate.
Placing the first conductive plate and the second conductive plate against each other, and pressing the first conductive plate and the second conductive plate.
Contacting the first conductive bumps with the second conductive plate, thereby forming a first passive element between the first conductive bump and the first passive element member; Patterning the conductive plate and the second conductive plate to form a first wiring layer and a second wiring layer, respectively, to obtain a first stacked body; A step of applying a second dielectric composition or a resistive composition to a gap at a portion where the second conductor bump abuts to form a second passive element member; and forming a substantially conical shape on the third conductor plate. Forming a second conductive bump group, placing a second insulating base material on the second conductive bump group, forming the third conductive plate and the second insulating base on the second conductive bump group. Pressing a material to penetrate the second conductive bump group through the second insulating base material;
Placing the laminated body of the third and the third conductive plate with the second passive element member and the second conductive bump group facing each other; and placing the first laminated body and the third conductive plate on the third conductive plate. Pressing the conductive plate to bring the second group of conductive bumps into contact with the first wiring layer, whereby a second passive bump is formed between the second conductive bump and the second passive element member. Forming an element; and patterning the third conductive plate to form a third wiring layer.

【0018】上記方法により、下記のプリント配線基板
が得られる。即ち、本発明の更に別のプリント配線基板
は、第1の絶縁性基材と、前記第1の絶縁性基材の第1
の面に配設された第1の配線層と、前記第1の絶縁性基
材の第2の面に配設された第2の配線層と、前記第1の
絶縁性基材の厚さ方向に貫通して形成され、前記第1の
配線層と前記第2の配線層とを接続する第1の導体バン
プ群と、前記第1の導体バンプ群の少なくとも二つの導
体バンプの間にわたって配設され、前記二つの導体バン
プとの間で第1の受動素子を形成する誘電性組成物又は
抵抗性組成物からなる第1の受動素子部材と、前記第1
の配線層を介して前記第1の絶縁性基材の第1の面に積
層された第2の絶縁性基材と、前記第2の絶縁性基材
の、前記第1の配線層と反対側の面に配設された第3の
配線層と、前記第2の絶縁性基材の厚さ方向に貫通して
形成され、前記第1の配線層と前記第3の配線層とを接
続する略円錐形の第2の導体バンプ群と、前記第2の導
体バンプ群の少なくとも二つの導体バンプの間にわたっ
て配設され、前記二つの導体バンプとの間で第2の受動
素子を形成する誘電性組成物又は抵抗性組成物からなる
第2の受動素子部材と、を具備する。
According to the above method, the following printed wiring board is obtained. That is, still another printed wiring board according to the present invention includes a first insulating base material and a first insulating base material.
A first wiring layer disposed on the second surface of the first insulating substrate, a second wiring layer disposed on the second surface of the first insulating substrate, and a thickness of the first insulating substrate. A first conductive bump group formed to penetrate the first wiring layer and connect the first wiring layer and the second wiring layer, and disposed between at least two conductive bumps of the first conductive bump group. A first passive element member comprising a dielectric composition or a resistive composition for forming a first passive element between the two conductive bumps;
A second insulating base material laminated on the first surface of the first insulating base material via the first wiring base, and a second insulating base material opposite to the first wiring layer. A third wiring layer disposed on the side surface of the second insulating substrate, and penetrating in a thickness direction of the second insulating base material, and connecting the first wiring layer and the third wiring layer. A second conductive bump group having a substantially conical shape and a second passive element formed between the two conductive bumps and disposed between at least two conductive bumps of the second conductive bump group. A second passive element member made of a dielectric composition or a resistive composition.

【0019】上記プリント配線基板及びその製造方法に
おいて、前記第1の受動素子と第2の受動素子とは同種
類の素子でもよいし、別種類の素子でもよい。
In the printed wiring board and the method of manufacturing the same, the first passive element and the second passive element may be of the same type or of different types.

【0020】本発明の更にもうひとつのプリント配線基
板製造方法は、第1の導体板上に略円錐形の導体バンプ
群を形成する工程と、前記導体バンプ群上に絶縁性基材
を載置する工程と、前記第1の導体板と前記絶縁性基材
とをプレスして前記導体バンプ群を前記絶縁性基材に貫
通させる工程と、第2の導体板上の、前記導体バンプが
当接する部分の周辺に誘電性組成物又は抵抗性組成物を
塗布して受動素子部材を形成する工程と、前記第1の導
体板と前記第2の導体板とを前記導体バンプ群と前記受
動素子部材とを対向させて載置する工程と、前記第1の
導体板と前記第2の導体板とを前記絶縁性基材を介して
プレスして一部の前記導体バンプ群を前記前記第2の導
体板に当接させるとともに他の一部の前記導体バンプ群
を前記受動素子部材の表面に当接させ、それにより前記
導体バンプ群、前記受動素子部材、及び前記第2の導体
板との間で受動素子を形成する工程と、前記第1の導体
板及び第2の導体板とをパターニングしてそれぞれ第1
の配線層と第2の配線層とを形成する工程と、を具備す
る。
[0020] Still another method of manufacturing a printed wiring board according to the present invention includes a step of forming a group of substantially conical conductive bumps on a first conductive plate, and placing an insulating base material on the group of conductive bumps. Pressing the first conductive plate and the insulating base material to penetrate the group of conductive bumps through the insulating base material; and contacting the conductive bumps on the second conductive plate with the conductive bumps. Forming a passive element member by applying a dielectric composition or a resistive composition to the periphery of the contacting portion; and connecting the first conductive plate and the second conductive plate to the conductive bump group and the passive element. Placing the member so as to face the member, and pressing the first conductive plate and the second conductive plate via the insulating base material to remove a part of the conductive bump group into the second conductive plate. And a part of the other conductive bump group is connected to the passive element portion. Forming a passive element between the group of conductive bumps, the passive element member, and the second conductive plate, thereby forming a first conductive plate and a second conductive plate. And pattern the first
Forming a second wiring layer and a second wiring layer.

【0021】この方法により、下記のプリント配線基板
が得られる。即ち、本発明の更にもう一つのプリント配
線基板は、絶縁性基材と、前記絶縁性基材の両面にそれ
ぞれ配設された第1の配線層及び第2の配線層と、前記
絶縁性基材の厚さ方向に貫通して形成され、前記第1の
配線層と第2の配線層とを接続する第1の導体バンプ群
と、前記絶縁性基材と前記第1の配線層又は前記第2の
配線層との間に埋設され、誘電性組成物又は抵抗性組成
物からなる受動素子部材と、前記絶縁性基材の厚さ方向
に貫通して形成され、前記第1の配線層又は第2の配線
層と前記受動素子部材との間で受動素子を形成する第2
の導体バンプ群と、を具備する。
According to this method, the following printed wiring board is obtained. That is, still another printed wiring board according to the present invention includes an insulating base material, a first wiring layer and a second wiring layer respectively disposed on both surfaces of the insulating base material, A first conductor bump group formed through the material in the thickness direction and connecting the first wiring layer and the second wiring layer; the insulating base material and the first wiring layer or the first conductive bump group; A passive element member buried between the second wiring layer and made of a dielectric composition or a resistive composition, and formed so as to penetrate in a thickness direction of the insulating base material; Or a second element for forming a passive element between a second wiring layer and the passive element member.
And a conductive bump group.

【0022】上記プリント配線基板において、前記受動
素子部材は、前記第2の導体バンプ群の先端側と前記第
1の配線層又は第2の配線層との間に介挿されていて良
い。
In the printed wiring board, the passive element member may be interposed between a tip end of the second conductive bump group and the first wiring layer or the second wiring layer.

【0023】また、上記プリント配線基板において、前
記受動素子部材は、前記第2の導体バンプ群の底面側と
前記第1の配線層又は第2の配線層との間に介挿されて
いても良い。
In the above printed wiring board, the passive element member may be interposed between the bottom surface of the second conductive bump group and the first wiring layer or the second wiring layer. good.

【0024】本発明の更に他のプリント配線基板製造方
法は、第1の導体板上に略円錐形の導体バンプ群を形成
する工程と、前記導体バンプ群上に絶縁性基材を載置す
る工程と、前記第1の導体板と前記絶縁性基材とをプレ
スして前記導体バンプ群を前記絶縁性基材に貫通させる
工程と、第2の導体板上の、前記導体バンプ群のうちの
一部の導体バンプが当接する部分に誘電性組成物又は抵
抗性組成物を塗布して、受動素子部材を形成する工程
と、前記第1の導体板と前記第2の導体板とを、前記導
体バンプ群と前記受動素子部材とが対向する向きに載置
する工程と、前記第1の導体板と前記第2の導体板とを
プレスして前記導体バンプ群を前記第2の導体板に当接
させ、それにより前記一部の導体バンプと前記受動素子
部材との間で受動素子を形成する工程と、前記第1の導
体板及び第2の導体板とをパターニングしてそれぞれ第
1の配線層と第2の配線層とを形成する工程と、を具備
する。
In still another method of manufacturing a printed wiring board according to the present invention, a step of forming a group of substantially conical conductive bumps on a first conductive plate, and placing an insulating base material on the group of conductive bumps. A step of pressing the first conductive plate and the insulating base material to penetrate the conductive bump group through the insulating base material, and a step of pressing the first conductive plate and the insulating base material through the insulating base material. A step of applying a dielectric composition or a resistive composition to a portion where a part of the conductor bumps abut, to form a passive element member, and the first conductor plate and the second conductor plate, Placing the conductive bump group and the passive element member in the facing direction; and pressing the first and second conductive plates to set the conductive bump group to the second conductive plate. A passive element between the part of the conductive bumps and the passive element member. Forming a comprises a step of forming a first of the first wiring layer respectively by patterning the conductive plate and second conductive plate and the second wiring layer.

【0025】この方法により、下記のプリント配線基板
が得られる。即ち、本発明の更に他のプリント配線基板
は、第1の導体板の一部に誘電性組成物又は抵抗性組成
物を塗布して、受動素子部材を形成する工程と、前記第
1の導体板上及び前記受動素子部材上に略円錐形の導体
バンプ群を形成する工程と、前記導体バンプ群上に絶縁
性基材と、更にその上に第2の導体板とを載置する工程
と、前記第1の導体板と前記第2の導体板とをプレスし
て前記導体バンプ群を前記絶縁性基材に貫通させると同
時に前記第1の導体板、前記受動素子部材、及び前記導
体バンプ群の一部との間で受動素子を形成する工程と、
前記第1の導体板及び第2の導体板とをパターニングし
てそれぞれ第1の配線層と第2の配線層とを形成する工
程と、を具備する。
According to this method, the following printed wiring board is obtained. That is, still another printed wiring board according to the present invention includes a step of applying a dielectric composition or a resistive composition to a part of a first conductor plate to form a passive element member; Forming a substantially conical conductive bump group on a plate and on the passive element member; placing an insulating base material on the conductive bump group and further mounting a second conductive plate thereon; Pressing the first conductive plate and the second conductive plate to cause the group of conductive bumps to penetrate the insulating base material, and at the same time, the first conductive plate, the passive element member, and the conductive bump Forming a passive element with a portion of the group;
Patterning the first conductive plate and the second conductive plate to form a first wiring layer and a second wiring layer, respectively.

【0026】本発明の更に他のもう一つのプリント配線
基板は、絶縁性基材と、前記絶縁性基材の両面にそれぞ
れ配設された第1の配線層及び第2の配線層と、誘電性
組成物又は抵抗性組成物からなり、前記絶縁性基材の厚
さ方向に前記第1の配線層と第2の配線層とを層間接続
し、前記第1の配線層及び第2の配線層との間で受動素
子を形成するバンプと、を具備する。
Still another printed wiring board according to the present invention comprises: an insulating base material; a first wiring layer and a second wiring layer provided on both surfaces of the insulating base material; The first wiring layer and the second wiring layer are connected to each other in the thickness direction of the insulating base material, and the first wiring layer and the second wiring And a bump forming a passive element between the layers.

【0027】このプリント配線基板は、例えば下記の方
法により製造される。即ち、本発明の更に他のもう一つ
のプリント配線基板製造方法は、第1の導体板上に誘電
性組成物又は抵抗性組成物を用いて略円錐形のバンプ群
を形成する工程と、前記バンプ群上に絶縁性基材と、更
にその上に第2の導体板とを載置する工程と、前記第1
の導体板と前記第2の導体板とをプレスして前記バンプ
群を前記絶縁性基材に貫通させると同時に前記第2の導
体板に当接させ、それにより前記第1の導体板、前記バ
ンプ、及び前記第2の導体板との間で受動素子を形成す
る工程と、前記第1の導体板及び第2の導体板とをパタ
ーニングしてそれぞれ第1の配線層と第2の配線層とを
形成する工程と、を具備する。
This printed wiring board is manufactured, for example, by the following method. That is, still another method of manufacturing a printed wiring board according to the present invention includes a step of forming a substantially conical bump group using a dielectric composition or a resistive composition on a first conductive plate; Placing an insulating base material on the bump group, and further mounting a second conductive plate thereon;
Pressing the conductor plate and the second conductor plate to allow the bump group to penetrate the insulating base material and simultaneously abut the second conductor plate, whereby the first conductor plate, Forming a passive element between the bump and the second conductor plate; and patterning the first and second conductor plates to form a first wiring layer and a second wiring layer, respectively. And a step of forming

【0028】本発明では、導体バンプ貫通法による製造
工程の途中で誘電性組成物又は抵抗性組成物を導体板の
表面に塗布するので、貫通孔を穿孔したり、その貫通孔
内に誘電性組成物又は抵抗性組成物を充填する手間が省
ける。その結果、導体バンプ貫通法の製造工程に比べ、
僅かな工程を追加するだけで受動素子を多層板内に形成
することができ、製造工程数の増加を最小限に抑えるこ
とができる。
In the present invention, since the dielectric composition or the resistive composition is applied to the surface of the conductor plate during the manufacturing process by the conductor bump penetration method, a through hole is formed or a dielectric material is formed in the through hole. The trouble of filling the composition or the resistive composition can be omitted. As a result, compared to the manufacturing process of the conductor bump penetration method,
Passive elements can be formed in the multilayer board by adding only a few steps, and an increase in the number of manufacturing steps can be minimized.

【0029】また、本発明では、誘電性組成物又は抵抗
性組成物からなる受動性素子部材を絶縁性基材とこの絶
縁性基材に積層される導体板や配線層との間に埋設さ
れ、導体バンプ、導体板、或いは配線層、との間で受動
素子を形成するので、多層板の内部に所定の受動素子を
内蔵させることができる。そのため、多層板の最外層表
面を広く利用することができ、より多くの素子や部品を
実装することができるので、集積度を更に向上させるこ
とができる。
In the present invention, a passive element member made of a dielectric composition or a resistive composition is embedded between an insulating base material and a conductor plate or a wiring layer laminated on the insulating base material. Since a passive element is formed between the conductive bump, the conductive plate, and the wiring layer, a predetermined passive element can be built in the multilayer board. Therefore, the outermost layer surface of the multilayer board can be widely used, and more elements and components can be mounted, so that the degree of integration can be further improved.

【0030】[0030]

【発明の実施の形態】(第1の実施の形態)以下、本発
明の発明の実施形態に係るプリント配線基板の製造方法
について説明する。図1は本実施形態に係るプリント配
線基板の製造方法のフローを示したフローチャートであ
り、図2〜図15は同プリント配線基板の製造方法の各
工程を模式的に示した垂直断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a method for manufacturing a printed wiring board according to an embodiment of the present invention will be described. FIG. 1 is a flowchart showing a flow of a method of manufacturing a printed wiring board according to the present embodiment, and FIGS. 2 to 15 are vertical cross-sectional views schematically showing steps of the method of manufacturing the printed wiring board. .

【0031】図2に示したように、まず銅箔などの導体
板1(第1の導体板)の片面に印刷技術により銀ペース
トなどの導電性組成物を用いて略円錐形の導体バンプ群
2,2,…を形成する(ステップ1)。
As shown in FIG. 2, first, a substantially conical conductive bump group is formed on one surface of a conductive plate 1 (first conductive plate) such as a copper foil by using a conductive composition such as a silver paste by a printing technique. Are formed (step 1).

【0032】次に図3に示すように、こうして形成した
導体バンプ群2,2,…の上に絶縁性基材としての絶縁
性基材プリプレグ(以下、絶縁性基材プリプレグを単に
「プリプレグ」という。)3を載置する(ステップ
2)。この状態で例えば表面が弾性材料で形成されたロ
ーラーの間を通過させるなどの方法により前記導体板1
とプリプレグ3とをプレスする(ステップ3)と、導体
バンプ群2,2,…がプリプレグ3を貫通して反対側に
突抜ける。それと同時に導体バンプ群2,2,…の先端
部分はローラーの弾性材料に押しつけられて丸まった形
になり、図4に示したような積層体4が得られる。
Next, as shown in FIG. 3, an insulating base material prepreg as an insulating base material (hereinafter referred to simply as “prepreg”) is placed on the conductive bump groups 2, 2,. 3) is placed (step 2). In this state, the conductor plate 1 is formed by, for example, passing between rollers formed of an elastic material.
Are pressed (Step 3), the conductor bump groups 2, 2,... Penetrate through the prepreg 3 and penetrate to the opposite side. At the same time, the tip portions of the conductive bump groups 2, 2,... Are pressed against the elastic material of the rollers to have a rounded shape, and the laminated body 4 as shown in FIG. 4 is obtained.

【0033】一方、前記積層体4とは別個に別の導体板
(第2の導体板)5を用意し、図5に示したようにこの
導体板5の一方の表面上に受動素子を形成する組成物を
例えば印刷技術を用いて塗布して(ステップ1')受動
素子部材6を形成する。この受動素子部材6を構成する
誘電性組成物や抵抗性組成物などの組成物としては、例
えば銀ペーストなどのように所定の電気的特性を備えた
粉状物や微粒子を樹脂とその溶剤に分散させたものが挙
げられる。この組成物を塗布して形成される受動素子部
材6は、塗布後乾燥することにより誘電体層や抵抗体層
を形成し、配線層を構成する導体板と組み合わされるこ
とにより、それぞれコンデンサーや抵抗として機能す
る。
On the other hand, another conductor plate (second conductor plate) 5 is prepared separately from the laminate 4 and a passive element is formed on one surface of the conductor plate 5 as shown in FIG. The composition to be applied is applied using, for example, a printing technique (step 1 ′) to form the passive element member 6. As a composition such as a dielectric composition or a resistive composition constituting the passive element member 6, a powder or fine particles having predetermined electric characteristics such as a silver paste can be used in a resin and a solvent thereof. Dispersed materials may be mentioned. The passive element member 6 formed by applying the composition forms a dielectric layer or a resistor layer by drying after application, and is combined with a conductor plate constituting a wiring layer, thereby forming a capacitor or a resistor. Function as

【0034】この受動素子部材を形成する位置として
は、図6に示したような隣接する二つの導体バンプ2と
導体バンプ2との隙間が挙げられる。図6中点線で示し
た円は導体バンプ2の外形を示しており、大きい方の円
は導体バンプ2の底面を示し、小さい方の円は導体板5
に突き当てられた導体バンプ2の当接面を示している。
As a position where the passive element member is formed, there is a gap between two adjacent conductor bumps 2 as shown in FIG. 6 indicate the outer shape of the conductor bump 2, the larger circle indicates the bottom surface of the conductor bump 2, and the smaller circle indicates the conductor plate 5.
2 shows the contact surface of the conductor bump 2 abutted on the surface.

【0035】なお、図6に示した位置の変形例として、
図7に示したように隣接する二つの導体バンプ2,2を
包含する長方形に塗布する方法や、図8に示したように
隣接する二つの導体バンプ2,2を包含する長円形に塗
布する方法、或いは図9に示すように隣接する二つの導
体バンプ2,2の側面の内側の半分どうしと接するよう
に半円形の切り欠き部分を備えた形状に塗布する方法な
どが挙げられる。
As a modification of the position shown in FIG.
As shown in FIG. 7, a method of applying a rectangular shape including two adjacent conductive bumps 2, 2 or a method of applying an oblong shape including two adjacent conductive bumps 2, 2 as shown in FIG. As shown in FIG. 9, a method of applying a shape having a semicircular cutout portion so as to be in contact with the inner halves of the side surfaces of the two adjacent conductor bumps 2 and 2 is exemplified.

【0036】次に、誘電性組成物又は抵抗性組成物を塗
布したら、乾燥して受動素子部材6を形成する(ステッ
プ2')。こうして得た導体板5と積層体4とを、図1
0に示すように受動素子部材6と導体バンプ群2,2,
…の先端とが対向する向きに載置する(ステップ4)。
この状態で例えばローラープレス間に通すことにより導
体板5と積層体4とをプレスすると(ステップ5)、プ
リプレグ3の図10中上面に突き出た導体バンプ群2,
2,…の先端部分が導体板5表面に当接され、図11に
示したように導体板1と5との間での層間接続が形成さ
れる。それと同時に受動素子部材6と隣接する二つの導
体バンプ2a,2bの各側面の一部との間で接触が形成
され、図11に示したような積層体7が形成される。
Next, after the dielectric composition or the resistive composition is applied, it is dried to form the passive element member 6 (step 2 '). The conductor plate 5 and the laminate 4 obtained in this way are
0, the passive element member 6 and the conductive bump groups 2, 2,
Are placed in a direction in which the tip of... Faces (Step 4).
In this state, when the conductor plate 5 and the laminate 4 are pressed by, for example, being passed between roller presses (Step 5), the conductor bump groups 2, 2 protruding from the upper surface of the prepreg 3 in FIG.
The tip portions of 2,... Are brought into contact with the surface of the conductor plate 5, and an interlayer connection between the conductor plates 1 and 5 is formed as shown in FIG. At the same time, a contact is formed between the passive element member 6 and a part of each side surface of the two adjacent conductor bumps 2a and 2b, and the laminated body 7 as shown in FIG. 11 is formed.

【0037】こうして得た積層体7の上下各面の導体板
1及び導体板5について、例えばエッチングを施すこと
によりパターニングして、それぞれ配線パターン1a及
び配線パターン5aを形成し、上下二層の多層板7aが
形成される。
The conductor plate 1 and the conductor plate 5 on each of the upper and lower surfaces of the laminate 7 thus obtained are patterned by, for example, etching to form a wiring pattern 1a and a wiring pattern 5a, respectively. A plate 7a is formed.

【0038】また、このパターニングにより受動素子部
材6が接していた部分の導体板5が除去されることによ
り、導体バンプ2a,2b、導体バンプ2a,2bの頭
部で接する配線層5a,5a、及び受動素子部材6とが
組み合わさって一つの受動素子が形成される。
Further, by removing the conductive plate 5 at the portion where the passive element member 6 is in contact by the patterning, the conductive bumps 2a and 2b, the wiring layers 5a and 5a contacting at the heads of the conductive bumps 2a and 2b, And the passive element member 6 is combined to form one passive element.

【0039】なお、受動素子部材6とこの受動素子部材
6に接触して受動素子の端子の一部を構成する二つの導
体バンプ2a,2bとの係合状態は図12に示したよう
な導体バンプ2a,2bの各側面の内側どうしを接続さ
せるような状態の他にもいくつかの変形例が考えられ
る。
The state of engagement between the passive element member 6 and the two conductor bumps 2a and 2b which are in contact with the passive element member 6 and constitute a part of the terminal of the passive element is as shown in FIG. In addition to a state in which the insides of the side surfaces of the bumps 2a and 2b are connected to each other, some modified examples can be considered.

【0040】例えば、図13に示したように受動素子部
材6を完全に貫通した状態である。これは図7に示した
配置の垂直断面に相当する。或いは、図14に示したよ
うに導体バンプ2a,2bの先端の一部、各内側が受動
素子部材6の左右両端とそれぞれ接している場合であ
る。
For example, as shown in FIG. 13, the passive element member 6 is completely penetrated. This corresponds to the vertical section of the arrangement shown in FIG. Alternatively, as shown in FIG. 14, a part of each of the front ends of the conductor bumps 2 a and 2 b is in contact with the left and right ends of the passive element member 6, respectively.

【0041】更に、図15に示したように、導体バンプ
2a,2bの各先端が受動素子部材6を完全に貫通して
おらず、受動素子部材6の途中で係止したようになって
いてもよい。
Further, as shown in FIG. 15, the respective ends of the conductor bumps 2a and 2b do not completely penetrate the passive element member 6, but are locked in the middle of the passive element member 6. Is also good.

【0042】以上詳述したように、本実施形態によれ
ば、導体バンプ群を用いて層間接続する多層板の製造過
程で誘電性組成物又は抵抗性組成物を導体板の表面に塗
布するので、受動素子を埋設するだけのためにわざわざ
貫通孔を穿孔したり、その貫通孔内に誘電性組成物又は
抵抗性組成物を充填するといった作業が不要である。
As described in detail above, according to the present embodiment, the dielectric composition or the resistive composition is applied to the surface of the conductive plate in the process of manufacturing the multilayer board for connecting layers using the conductive bump group. In addition, there is no need to perform operations such as piercing a through-hole only for embedding a passive element or filling the through-hole with a dielectric composition or a resistive composition.

【0043】その結果、導体バンプ貫通法の製造工程に
対して、受動素子部材を形成するという工程を追加する
だけで済み、追加の工程を最小限に留めながら受動素子
を多層板内に形成することができる。
As a result, it is only necessary to add a step of forming a passive element member to the manufacturing step of the conductor bump penetration method, and the passive element is formed in the multilayer board while minimizing the additional step. be able to.

【0044】また、本実施形態では、誘電性組成物又は
抵抗性組成物からなる受動性素子部材を絶縁性基材とこ
の絶縁性基材に積層される導体板や配線層との間に埋設
され、導体バンプ、導体板、或いは配線層、との間で受
動素子を形成するので、多層板の内部に所定の受動素子
を内蔵させることができる。そのため、多層板の最外層
表面を広く利用することができ、より多くの素子や部品
を実装することができるので、集積度を更に向上させる
ことができる。
In this embodiment, a passive element member made of a dielectric composition or a resistive composition is embedded between an insulating base material and a conductor plate or a wiring layer laminated on the insulating base material. Since a passive element is formed between the conductive bump, the conductive plate, and the wiring layer, a predetermined passive element can be built in the multilayer board. Therefore, the outermost layer surface of the multilayer board can be widely used, and more elements and components can be mounted, so that the degree of integration can be further improved.

【0045】以下、本実施形態に係る多層板を用いた半
導体パッケージと従来の多層板を用いた半導体パッケー
ジの集積度の違いについて説明する。図16は従来の多
層板を用いた半導体パッケージの垂直断面図であり、図
17は本実施形態に係る多層板を用いた半導体パッケー
ジの垂直断面図である。
The difference in the degree of integration between the semiconductor package using the multilayer board according to the present embodiment and the conventional semiconductor package using the multilayer board will be described. FIG. 16 is a vertical sectional view of a semiconductor package using a conventional multilayer board, and FIG. 17 is a vertical sectional view of a semiconductor package using the multilayer board according to the present embodiment.

【0046】従来の多層板では半導体チップ56と電源
線側配線層51aとを接続する際に抵抗Rやコンデンサ
ーCなどを介挿するには図16に示したように、電源線
側配線層51aに接続された配線層54aと半導体チッ
プ56と接続された配線層54bとの間に抵抗やコンデ
ンサーなどの受動素子55を接続しており、この受動素
子55を接続するためのスペースが必要となる。そのた
め、集積度を上げるための障害となっていた。
In the conventional multilayer board, when connecting the semiconductor chip 56 and the power supply line side wiring layer 51a with a resistor R, a capacitor C, etc., as shown in FIG. A passive element 55 such as a resistor or a capacitor is connected between a wiring layer 54a connected to the semiconductor chip 56 and a wiring layer 54b connected to the semiconductor chip 56, and a space for connecting the passive element 55 is required. . This has been an obstacle for increasing the degree of integration.

【0047】一方、本実施形態の多層板では、抵抗やコ
ンデンサーなどの受動素子を形成する受動素子部材60
を絶縁性基材53内の導体バンプ52aと導体バンプ5
2bとの間に配設してあるので、図17に示したように
半導体チップ56を配線層54bに接続するだけで、電
源線側配線層51aと半導体チップ56との間に受動素
子を介挿した配線を形成することができる。そのため、
受動素子55を基板の上面に配設するためのスペースが
不要になり、その分半導体パッケージを小型化でき、集
積度を向上させることができる。
On the other hand, in the multilayer board of this embodiment, the passive element member 60 for forming a passive element such as a resistor or a capacitor is used.
And the conductive bumps 52a and the conductive bumps 5 in the insulating base material 53.
2b, only by connecting the semiconductor chip 56 to the wiring layer 54b as shown in FIG. 17, a passive element is interposed between the power supply line side wiring layer 51a and the semiconductor chip 56. The inserted wiring can be formed. for that reason,
Space for disposing the passive element 55 on the upper surface of the substrate is not required, so that the semiconductor package can be reduced in size and the degree of integration can be improved.

【0048】なお、本発明は上記実施形態の内容に限定
されるものではない。
The present invention is not limited to the contents of the above embodiment.

【0049】例えば、上記実施形態では受動素子部材は
隣接する二つの導体バンプの間にわたって配設されてい
るが、一つの受動素子部材に三つ以上の導体バンプが接
触していてもよい。また、上記実施形態では1枚の絶縁
性基材の両面に配線層1a,5aが形成されたいわゆる
二層の配線層からなる多層板7aを例にして説明した
が、本発明が三層以上の配線層からなる多層板にも使用
できることはいうまでもない。
For example, in the above embodiment, the passive element member is disposed between two adjacent conductor bumps, but three or more conductor bumps may be in contact with one passive element member. Further, in the above embodiment, the multilayer board 7a composed of so-called two wiring layers in which the wiring layers 1a and 5a are formed on both surfaces of one insulating base material has been described as an example, but the present invention is not limited to three or more layers. Needless to say, it can also be used for a multilayer board composed of the above wiring layers.

【0050】更に、本実施形態において、導体バンプを
貫通させるのに使用する絶縁性基材としては、ガラスク
ロスやマット、有機合成繊維布やマット、或いは紙など
の補強材で強化された合成樹脂系シートが挙げられる。
その厚さは20〜400μm程度が好ましい。ここで、
合成樹脂としては、例えばポリカーボネート樹脂、ポリ
スルホン樹脂、熱可塑性ポリイミド樹脂、ポリ4フッ化
エチレン6フッ化プロピレン樹脂、ポリエーテルエーテ
ルケトン樹脂などの熱可塑性樹脂、エポキシ樹脂、ビス
マレイミドトリアジン樹脂、ポリイミド樹脂、フェノー
ル樹脂、ポリエステル樹脂、メラミン樹脂などの熱硬化
性樹脂、あるいはブタジエンゴム、ブチルゴム、天然ゴ
ム、ネオプレンゴム、シリコーンゴムなどのゴム類が挙
げられる。
Further, in the present embodiment, the insulating base material used for penetrating the conductor bumps may be a synthetic resin reinforced with a reinforcing material such as glass cloth or mat, organic synthetic fiber cloth or mat, or paper. System sheet.
The thickness is preferably about 20 to 400 μm. here,
As the synthetic resin, for example, a polycarbonate resin, a polysulfone resin, a thermoplastic polyimide resin, a polytetrafluoroethylene hexafluoropropylene resin, a thermoplastic resin such as a polyetheretherketone resin, an epoxy resin, a bismaleimide triazine resin, a polyimide resin, Thermosetting resins such as phenolic resins, polyester resins, and melamine resins, and rubbers such as butadiene rubber, butyl rubber, natural rubber, neoprene rubber, and silicone rubber are exemplified.

【0051】そして、前記略円錐形の導体バンプの形成
は、導電性組成物で形成する場合、例えば比較的厚いメ
タルマスクを用いた印刷法で、アスペクト比の高い略円
錐形の導体バンプ群を形成できる。また、前記略円錐形
の導体バンプ群の高さは、一般的に、20〜500μm
程度が可能である。
When forming the substantially conical conductive bumps by using a conductive composition, for example, a substantially conical conductive bump group having a high aspect ratio is formed by a printing method using a relatively thick metal mask. Can be formed. The height of the group of substantially conical conductive bumps is generally 20 to 500 μm.
Degrees are possible.

【0052】本発明において、略円錐形の導体バンプ群
を導電性金属で形成する手段としては、例えば、銅箔な
どの支持基体面の所定位置に、金もしくは銅のボールを
押し付け、しかる後に引き離すことにより先端が尖った
略円錐形の導体(素子)群を形成できる。また予め、略
円錐形の導体の形に対応する凹部を形成したプレートに
溶融金属を注入し、略円錐形の導体バンプ群を形成する
ことも可能である。更に他の手段として、支持フィルム
面上に感光性レジストを厚めに塗布し、支持フィルム側
から露光することにより先端が尖った台形の凹部を持っ
た窪み群を形成した後、前記支持フィルムを除去し、こ
の支持フィルム除去面に金属膜を張り、銅、金、銀、半
田などをメッキして所定位置に微小な略円錐形の導体バ
ンプ群を形成してもよい。
In the present invention, as a means for forming a group of substantially conical conductive bumps made of a conductive metal, for example, a gold or copper ball is pressed to a predetermined position on the surface of a supporting base such as a copper foil and then separated. Thereby, a conductor (element) group having a substantially conical shape with a sharp tip can be formed. Further, it is also possible to inject molten metal into a plate in which a concave portion corresponding to the shape of a substantially conical conductor is formed beforehand to form a substantially conical conductor bump group. As still another means, a photosensitive resist is applied thickly on the support film surface, and the support film is removed after forming a group of depressions having a trapezoidal concave portion with a sharp tip by exposing from the support film side. Then, a metal film may be formed on the support film-removed surface, and plated with copper, gold, silver, solder, or the like to form minute substantially conical conductive bumps at predetermined positions.

【0053】また、本発明において、前記略円錐形の導
体バンプ群を支持する基体としては、離形性のあるフィ
ルムあるいは金属箔などが挙げられ、この支持基体は1
枚のシートであってもよく、パターン化されたものでも
よく、その形状は特に限定されない。
In the present invention, examples of the substrate supporting the group of substantially conical conductive bumps include a releasable film or a metal foil.
It may be a single sheet or a patterned sheet, and its shape is not particularly limited.

【0054】更に本発明において、前記略円錐形の導体
バンプを合成樹脂系シートに貫通させる手段として、例
えば、略円錐形の導体バンプ群を形成した支持基体、及
び合成樹脂系シートなどをロールから巻き戻しながら、
加熱して樹脂分を柔らかくし、例えば、寸法や変形の少
ない金属製、硬質な耐熱性樹脂製、もしくはセラミック
製のローラと、合成樹脂側には加圧したとき弾性的に変
形するローラ、例えば前記のようなゴム製のローラとの
間を通過させることにより、略円錐形の導体バンプが貫
通し、合成樹脂系シート表面に両端側が露出してなる多
層板を連続的に製造することができる。
Further, in the present invention, as means for penetrating the substantially conical conductive bumps through the synthetic resin sheet, for example, a support base having a group of substantially conical conductive bumps formed thereon, a synthetic resin sheet or the like may be rolled. While rewinding,
Heating to soften the resin component, for example, a metal with small dimensions and deformation, a hard heat-resistant resin, or a ceramic roller, and a roller that elastically deforms when pressed on the synthetic resin side, for example, By passing between the rubber rollers as described above, a substantially conical conductive bump penetrates, and a multilayer board having both ends exposed on the surface of the synthetic resin sheet can be continuously manufactured. .

【0055】(第2の実施形態)以下、本発明の第2の
実施形態について説明する。なお、本実施形態以降の実
施形態のうち、先行する実施形態と重複する部分につい
ては説明を省略する。
(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described. Note that, of the embodiments after this embodiment, the description of the same parts as the preceding embodiment will be omitted.

【0056】図18は本実施形態に係るプリント配線基
板の製造方法のフローを示したフローチャートであり、
図19〜図23は同製造方法の各工程を模式的に示した
垂直断面図である。
FIG. 18 is a flowchart showing the flow of the method for manufacturing a printed wiring board according to the present embodiment.
19 to 23 are vertical sectional views schematically showing each step of the manufacturing method.

【0057】本実施形態に係るプリント配線基板を製造
するには、図18のステップ1a〜6aに従って多層板
7aを形成する。このステップ1a〜6aは、上記第1
の実施形態のステップ1〜6と同じ内容であり、本実施
形態のステップ1b〜2bは、受動素子部材6を形成す
る組成物を「第1の組成物1」と命名した以外は上記第
1の実施形態のステップ1'〜2'と同じである。
To manufacture the printed wiring board according to the present embodiment, a multilayer board 7a is formed according to steps 1a to 6a in FIG. The steps 1a to 6a are performed in the first
The steps 1b to 2b of the present embodiment are the same as the steps 1 to 6 of the embodiment, except that the composition for forming the passive element member 6 is named “first composition 1”. Are the same as Steps 1 ′ to 2 ′ of the embodiment.

【0058】ステップ1a〜6a及びステップ1b〜2
bを経て図19に示したような多層板7aが得られた
ら、この多層板7aの図中上面側に形成された配線層5
bと配線層5cとにわたって、受動素子を形成する組成
物2を例えば印刷技術を用いて塗布し(ステップ7
a)、図20に示したような受動素子部材8(第1の受
動素子部材)を形成する。
Steps 1a to 6a and 1b to 2
b, the multilayer board 7a as shown in FIG. 19 is obtained, and the wiring layer 5 formed on the upper surface side of the multilayer board 7a in the drawing is obtained.
A composition 2 for forming a passive element is applied, for example, using a printing technique over the wiring layer 5b and the wiring layer 5c (Step 7)
a), a passive element member 8 (first passive element member) as shown in FIG. 20 is formed.

【0059】この第2の受動素子部材8は前記受動素子
部材6と同じ性質の受動素子を形成するものであって
も、異なる性質の受動素子を形成するものであってもよ
いが、同じ性質の受動素子は同一層上に形成することが
製造工程上有利であるので、図20のように形成する層
が異なる場合には異なる性質の受動素子を配設するのが
好ましい。例えば、受動素子部材6が抵抗Rを構成する
抵抗性組成物を塗布したものであれば、受動素子部材8
はコンデンサーCを構成する誘電性組成物を塗布したも
のにするのが好ましい。
The second passive element member 8 may form a passive element having the same property as the passive element member 6 or may form a passive element having a different property. Since it is advantageous in the manufacturing process to form the passive elements on the same layer, it is preferable to dispose passive elements having different properties when the layers to be formed are different as shown in FIG. For example, if the passive element member 6 is formed by applying a resistive composition constituting the resistor R, the passive element member 8
Is preferably applied with a dielectric composition constituting the capacitor C.

【0060】図20のように第2の組成物を塗布した
ら、この第2の組成物を乾燥させて第2の受動素子部材
8を形成して(ステップ8a)、積層体7bを得る。
After the application of the second composition as shown in FIG. 20, the second composition is dried to form the second passive element member 8 (step 8a) to obtain the laminate 7b.

【0061】一方、積層体7bとは別個に導体板11を
用意し、この導体板11上に導体バンプ群12,12,
…を形成し(ステップ1c)、これにプリプレグ13を
載置し(ステップ2c)、プレスして(ステップ3
c)、図21のような積層体14を形成する。
On the other hand, a conductor plate 11 is prepared separately from the laminated body 7b, and the conductor bump groups 12, 12,
Are formed (step 1c), the prepreg 13 is placed thereon (step 2c), and pressed (step 3c).
c), forming a laminate 14 as shown in FIG.

【0062】次に先の積層体7bと積層体14とを、図
21に示したように導体バンプ群12,12,…の先端
側と第2の受動素子部材8とが対向する向きに載置し
(ステップ9a)する。
Next, the laminated body 7b and the laminated body 14 are mounted in such a manner that the front end side of the conductive bump groups 12, 12,... And the second passive element member 8 face each other as shown in FIG. (Step 9a).

【0063】しかる後にこの状態で積層体7bと積層体
14とを例えばローラープレス間に通すことによりプレ
スして(ステップ10a)、導体バンプ群12,12,
…の先端側を配線層5a〜5bに当接させる。このと
き、導体バンプ群12,12,…の一部(導体バンプ1
2aと12b)は第2の受動素子部材8を貫通してから
配線層5b,5cに当接する。この第2の受動素子部材
8を貫通することにより導体バンプ12aと12bとは
受動素子部材8と接触して第2の受動素子を形成し、図
22に示したような積層体15を形成する。
Thereafter, in this state, the laminate 7b and the laminate 14 are pressed by, for example, being passed between roller presses (step 10a), and the conductor bump groups 12, 12,
Are brought into contact with the wiring layers 5a to 5b. At this time, a part of the conductor bump groups 12, 12,.
2a and 12b) penetrate the second passive element member 8 and then come into contact with the wiring layers 5b and 5c. By penetrating the second passive element member 8, the conductive bumps 12a and 12b come into contact with the passive element member 8 to form a second passive element, and form a laminate 15 as shown in FIG. .

【0064】次いでこの積層体15の図中上面の導体板
11について例えばエッチング処理を施すことによりパ
ターニングして(ステップ11a)、配線層11aを形
成することにより図23に示したような多層板16が得
られる。
Next, the conductor plate 11 on the upper surface in the figure of the laminate 15 is patterned by, for example, etching (step 11a), and the wiring layer 11a is formed to form a multilayer board 16 as shown in FIG. Is obtained.

【0065】本実施形態では、種類の異なる二つの受動
素子を異なる絶縁性基材の中に埋設しているので、更に
集積度を向上させることができるという特有の効果が得
られる。
In this embodiment, since two different types of passive elements are embedded in different insulating base materials, a unique effect that the integration degree can be further improved is obtained.

【0066】また、本実施形態では異なる種類の受動素
子部材を異なる絶縁性基材の層に形成しているので、同
一層上に2種類の組成物を塗り分ける手間が掛からない
ので、追加される工数を最小限に抑えることができる。
In the present embodiment, since different types of passive element members are formed on different insulating base material layers, there is no need to separately apply two types of compositions on the same layer. Man-hours can be minimized.

【0067】(第3の実施形態)本実施形態では、第1
の実施形態で用いた積層体4と同じ積層体4を用いる。
(Third Embodiment) In the present embodiment, the first
The same laminated body 4 as the laminated body 4 used in the embodiment is used.

【0068】図24は本実施形態に係るプリント配線基
板の製造方法のフローを示したフローチャートであり、
図25〜図27は同製造方法の各工程を模式的に示した
垂直断面図である。
FIG. 24 is a flowchart showing the flow of the method for manufacturing a printed wiring board according to the present embodiment.
25 to 27 are vertical cross-sectional views schematically showing each step of the manufacturing method.

【0069】本実施形態に係るプリント配線基板を製造
するには、図24のステップ1d〜3dの工程を行なう
ことにより図25に示したような積層体4を得る。この
積層体4とは別個に別の導体板21を用意し、この導体
板21の一方の面上の、導体バンプ2aを突き当てる位
置に第1の組成物を例えば印刷技術を用いて塗布する
(ステップ1e)。またこのとき、導体バンプ2bを突
き当てる位置に第2の組成物を塗布してもよい。上記第
1の組成物と第2の組成物とは同種類の受動素子を形成
する組成物であってもよく、また異なる種類の受動素子
を形成する組成物であってもよい。
To manufacture the printed wiring board according to the present embodiment, the steps 1d to 3d in FIG. 24 are performed to obtain the laminate 4 as shown in FIG. A separate conductor plate 21 is prepared separately from the laminated body 4, and the first composition is applied to one surface of the conductor plate 21 at a position where the conductor bump 2 a is abutted by using, for example, a printing technique. (Step 1e). Further, at this time, the second composition may be applied to a position where the conductive bump 2b abuts. The first composition and the second composition may be compositions that form passive elements of the same type, or may be compositions that form passive elements of different types.

【0070】導体板21上に第1の組成物と希望する場
合には第2の組成物とを塗布後乾燥して(ステップ2
e)、図25に示したような受動素子部材22と受動素
子部材23とを形成する。
The first composition and, if desired, the second composition are applied onto the conductive plate 21 and then dried (step 2).
e), the passive element member 22 and the passive element member 23 as shown in FIG. 25 are formed.

【0071】しかる後に導体板21と積層体4とを、図
25に示したように導体バンプ群2a,2b,2,2,
…の先端側と受動素子部材22,23とが対向する向き
に載置する(ステップ4d)。この状態で導体板21と
積層体4とを例えばローラープレス間に通すことにより
プレスすると(ステップ5d)、導体バンプ2aが受動
素子部材22の図中下面側に当接し、導体バンプ2bが
受動素子部材23の図中下面側に当接すると同時に導体
バンプ群2,2,…の先端側が導体板21に当接して図
26に示したような導体板1と導体21との間で層間接
続が形成された積層体24が得られる。
Thereafter, the conductor plate 21 and the laminated body 4 are connected to the conductor bump groups 2a, 2b, 2, 2, as shown in FIG.
And the passive element members 22 and 23 are placed so as to face each other (step 4d). In this state, when the conductor plate 21 and the laminate 4 are pressed by, for example, being passed between roller presses (step 5d), the conductor bumps 2a abut on the lower surface side of the passive element member 22 in the drawing, and the conductor bumps 2b are .. At the same time as contacting the lower surface side of the member 23 in the drawing, the front end sides of the conductor bump groups 2, 2,. The formed laminate 24 is obtained.

【0072】こうして得られた積層体24の上下の導体
板1及び21について例えばエッチング処理を施すこと
によりパターニングして(ステップ6d)、それぞれ配
線層1a及び配線層21aを形成することにより図27
に示したような多層板25が得られる。
The upper and lower conductor plates 1 and 21 of the laminate 24 thus obtained are patterned by, for example, etching (step 6d) to form a wiring layer 1a and a wiring layer 21a, respectively.
Is obtained.

【0073】本実施形態によれば、導体バンプ2aや導
体バンプ2bと導体板21との間で基板の厚さ方向に受
動素子を形成しているので、配線層21aの図中水平方
向の広がりが極めて小さい受動素子を基板内に形成する
ことができる。したがって、配線層21a上には更に各
種半導体素子を高密度で実装できるので、集積度を更に
向上させることができる、という特有の効果が得られ
る。
According to the present embodiment, since the passive elements are formed in the thickness direction of the substrate between the conductor bumps 2a and the conductor bumps 2b and the conductor plate 21, the wiring layer 21a extends in the horizontal direction in the drawing. Can be formed in the substrate. Therefore, since various semiconductor elements can be mounted on the wiring layer 21a at a higher density, a unique effect that the degree of integration can be further improved can be obtained.

【0074】なお、受動素子部材22と23とを同じ誘
電性組成物又は抵抗性組成物を用いて形成してもよいこ
とは言うまでもない。
It is needless to say that the passive element members 22 and 23 may be formed by using the same dielectric composition or resistive composition.

【0075】(第4の実施形態)図28は本実施形態に
係るプリント配線基板の製造方法のフローを示したフロ
ーチャートであり、図29〜図33は同製造方法の各工
程を模式的に示した垂直断面図である。
(Fourth Embodiment) FIG. 28 is a flowchart showing a flow of a method of manufacturing a printed wiring board according to the present embodiment, and FIGS. 29 to 33 schematically show each step of the manufacturing method. FIG.

【0076】本実施形態に係るプリント配線基板を製造
するには、まず銅箔などの導体板31を用意し、この導
体板31の上に例えば印刷技術を用いて誘電性組成物又
は抵抗性組成物を塗布する(ステップ1f)。こうして
誘電性組成物又は抵抗性組成物を塗布した導体板31を
乾燥して(ステップ2f)、図29に示したような受動
素子部材32,32が形成された導体板31Aを得る。
To manufacture the printed wiring board according to the present embodiment, first, a conductive plate 31 such as a copper foil is prepared, and a dielectric composition or a resistive composition is formed on the conductive plate 31 by using, for example, a printing technique. An object is applied (step 1f). The conductor plate 31 coated with the dielectric composition or the resistive composition is dried (step 2f) to obtain a conductor plate 31A on which the passive element members 32, 32 are formed as shown in FIG.

【0077】次に導体板31Aの受動素子32,32を
形成した面上に例えば印刷技術を用いて例えば銀ペース
トなどの導電性組成物からなる略円錐形の導体バンプ群
33,33,…を形成して(ステップ3f)、図30に
示したような導体板31Bを得る。
Next, on the surface of the conductive plate 31A on which the passive elements 32, 32 are formed, a substantially conical conductive bump group 33, 33 made of a conductive composition such as silver paste is formed by using, for example, a printing technique. After forming (step 3f), a conductor plate 31B as shown in FIG. 30 is obtained.

【0078】このとき、受動素子部材32,32の上面
上に導体バンプ33a,33aが形成される。
At this time, the conductor bumps 33a are formed on the upper surfaces of the passive element members 32.

【0079】こうして得た導体板31Bの導体バンプ群
33a,33a,33,33,…の上にプリプレグ34
と更にその上に別の導体板35とを載置し(ステップ4
f)、この状態で導体板31B、プリプレグ34、及び
導体板35を例えばローラープレスの間に通すなどの方
法によりプレスすると(ステップ5f)、導体バンプ群
33a,33a,33,33,…がプリプレグ34を貫
通し、導体バンプ群33a,33a,33,33,…の
先端側が導体板35の下面側に当接して図32に示した
ような導体板31と導体板35との間が層間接続された
積層体36が得られる。
The prepreg 34 is placed on the conductor bump groups 33a, 33a, 33, 33,... Of the conductor plate 31B thus obtained.
And another conductive plate 35 is placed thereon (step 4).
f) In this state, when the conductor plate 31B, the prepreg 34, and the conductor plate 35 are pressed by, for example, being passed between roller presses (step 5f), the conductor bump groups 33a, 33a, 33, 33,. ., And the front ends of the conductor bump groups 33a, 33a, 33, 33,... Abut the lower surface of the conductor plate 35, and the conductor plate 31 and the conductor plate 35 as shown in FIG. The laminated body 36 obtained is obtained.

【0080】こうして得た積層体36の上下各面の導体
板31,35について例えばエッチング処理によりパタ
ーニングすると(ステップ6f)、図33に示したよう
な多層板37が形成される。
When the conductor plates 31 and 35 on the upper and lower surfaces of the laminate 36 thus obtained are patterned by, for example, an etching process (step 6f), a multilayer plate 37 as shown in FIG. 33 is formed.

【0081】本実施形態では、受動素子部材32を導体
バンプ33の底面側に配設しているので、導体バンプ3
3との接続が確実となる。また、受動素子部材32の厚
さが終始一定であるので、受動素子の能力を所期の値の
ものにすることが容易になるという特有の効果が得られ
る。
In this embodiment, since the passive element member 32 is disposed on the bottom surface side of the conductor bump 33, the conductor bump 3
The connection with 3 is ensured. In addition, since the thickness of the passive element member 32 is constant throughout, it is possible to obtain a specific effect that it is easy to set the performance of the passive element to a desired value.

【0082】また、本実施形態によれば、導体バンプ3
3aと導体板31,33との間で基板の厚さ方向に受動
素子を形成しているので、配線層31a,35aの図中
水平方向の広がりが極めて小さい受動素子を基板内に形
成することができる。したがって、配線層31a,35
a上には更に各種半導体素子を高密度で実装できるの
で、集積度を更に向上させることができる、という効果
が得られる。
According to the present embodiment, the conductor bumps 3
Since the passive elements are formed in the thickness direction of the substrate between 3a and the conductive plates 31 and 33, the passive elements in which the wiring layers 31a and 35a are extremely small in the horizontal direction in the drawing are formed in the substrate. Can be. Therefore, the wiring layers 31a, 35
Since various semiconductor elements can be mounted at a higher density on a, the effect of further improving the degree of integration can be obtained.

【0083】(第5の実施形態)図34は本実施形態に
係るプリント配線基板の製造方法のフローを示したフロ
ーチャートであり、図35〜図38は同製造方法の各工
程を模式的に示した垂直断面図である。
(Fifth Embodiment) FIG. 34 is a flowchart showing a flow of a method of manufacturing a printed wiring board according to the present embodiment, and FIGS. 35 to 38 schematically show steps of the manufacturing method. FIG.

【0084】本実施形態に係るプリント配線基板を製造
するには、まず銅箔などの導体板41を用意し、この導
体板41の上に例えば印刷技術により誘電性組成物又は
抵抗性組成物などの所期の受動素子を形成する組成物を
用いて略円錐形のバンプ群42,42,…を形成し(ス
テップ1g)、次いでこれらバンプ群42,42,…を
乾燥して(ステップ2g)、図35に示したような導体
板41Aを得る。
In order to manufacture the printed wiring board according to the present embodiment, first, a conductive plate 41 such as a copper foil is prepared, and a dielectric composition or a resistive composition or the like is formed on the conductive plate 41 by, for example, a printing technique. Are formed using the composition for forming the desired passive element (step 1g), and then these bump groups 42, 42,... Are dried (step 2g). Thus, a conductor plate 41A as shown in FIG. 35 is obtained.

【0085】次に、図36に示したように導体板41の
バンプ群42,42,…の上に絶縁性基材プリプレグ4
3と、更にその上に別の導体板44とを載置する(ステ
ップ3g)。
Next, as shown in FIG. 36, the insulating base material prepreg 4 is placed on the bump groups 42, 42,.
3 and another conductive plate 44 thereon (step 3g).

【0086】しかる後にこの状態で導体板41A、プリ
プレグ43、及び導体板44を、例えばローラープレス
間を通すなどの方法によりプレスすると(ステップ4
g)、バンプ群42,42,…が絶縁性基材プリプレグ
43に貫通すると同時にバンプ群42,42,…の先端
側が導体板44に当接して図37に示したような前記導
体板41と導体板44との間で層間接続が形成された積
層体45が得られる。
Thereafter, in this state, the conductor plate 41A, the prepreg 43, and the conductor plate 44 are pressed by a method such as passing between roller presses (Step 4).
g), the bump groups 42, 42,... penetrate the insulating base material prepreg 43, and at the same time, the front ends of the bump groups 42, 42,. A laminate 45 having an interlayer connection with the conductor plate 44 is obtained.

【0087】こうして得られた積層体45の上下各面に
配設された導体板41,44に例えばエッチング処理を
施すなどの方法によりパターニングを行ない(ステップ
5g)、図38に示したような配線層41a,44aが
それぞれ形成された多層板46が得られる。
The conductor plates 41 and 44 disposed on the upper and lower surfaces of the laminate 45 thus obtained are patterned by, for example, etching (step 5g), and the wiring as shown in FIG. A multilayer board 46 on which the layers 41a and 44a are respectively formed is obtained.

【0088】本実施形態では、バンプ自体を誘電性組成
物又は抵抗性組成物で構成しているので、多層板完成後
はバンプ自身がコンデンサーCや抵抗Rなどの受動素子
として機能する。そのため、更に集積度を向上させるこ
とができる。
In this embodiment, since the bump itself is made of a dielectric composition or a resistive composition, the bump itself functions as a passive element such as a capacitor C or a resistor R after the completion of the multilayer board. Therefore, the degree of integration can be further improved.

【0089】上述した各実施形態に記載された基板内蔵
抵抗(抵抗組成物の塗布・印刷により基板内に形成され
た抵抗)、基板内蔵コンデンサ−(コンデンサー組成物
の塗布・印刷により基板内に形成されたコンデンサー)
はプリント配線基板上に形成される電気回路のいかなる
抵抗、コンデンサーとしても使用可能であるが、特に電
源端子、GND端子接続部に形成された場合には、その
基板に実装する半導体装置の設計変更によって端子位置
が変更される可能性が低く、特に有効である。
The resistance built into the substrate (the resistance formed in the substrate by applying and printing the resistor composition) described in each of the above embodiments, the capacitor embedded in the substrate (formed in the substrate by coating and printing the capacitor composition) Condenser)
Can be used as any resistor or capacitor of an electric circuit formed on a printed wiring board. Especially when it is formed at a power supply terminal or GND terminal connection part, the design change of a semiconductor device mounted on the board is possible. It is particularly effective that the terminal position is unlikely to be changed due to this.

【0090】また、これらの端子に接続される受動素子
は特性変動の許容範囲が広いため、本発明の実施は特に
有効である。
Further, since the passive elements connected to these terminals have a wide allowable range of characteristic fluctuation, the embodiment of the present invention is particularly effective.

【0091】[0091]

【発明の効果】本発明によれば、導体バンプ貫通法によ
る製造工程の途中で誘電性組成物又は抵抗性組成物を導
体板の表面に塗布するので、貫通孔を穿孔したり、その
貫通孔内に誘電性組成物又は抵抗性組成物を充填する手
間が省ける。その結果、導体バンプ貫通法の製造工程に
比べ、僅かな工程を追加するだけで受動素子を多層板内
に形成することができ、製造工程数の増加を最小限に抑
えることができる。
According to the present invention, the dielectric composition or the resistive composition is applied to the surface of the conductor plate during the manufacturing process by the conductor bump penetration method. The trouble of filling the inside with the dielectric composition or the resistive composition can be omitted. As a result, the passive element can be formed in the multilayer board by adding only a few steps as compared with the manufacturing process of the conductor bump penetration method, and an increase in the number of manufacturing processes can be minimized.

【0092】また、本発明では、誘電性組成物又は抵抗
性組成物からなる受動性素子部材を絶縁性基材とこの絶
縁性基材に積層される導体板や配線層との間に埋設さ
れ、導体バンプ、導体板、或いは配線層、との間で受動
素子を形成するので、多層板の内部に所定の受動素子を
内蔵させることができる。そのため、多層板の最外層表
面を広く利用することができ、より多くの素子や部品を
実装することができるので、集積度を更に向上させるこ
とができる。
In the present invention, a passive element member made of a dielectric composition or a resistive composition is embedded between an insulating base material and a conductor plate or a wiring layer laminated on the insulating base material. Since a passive element is formed between the conductive bump, the conductive plate, and the wiring layer, a predetermined passive element can be built in the multilayer board. Therefore, the outermost layer surface of the multilayer board can be widely used, and more elements and components can be mounted, so that the degree of integration can be further improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施形態に係るプリント配線基板の製造
方法のフローを示したフローチャートである。
FIG. 1 is a flowchart illustrating a flow of a method for manufacturing a printed wiring board according to a first embodiment.

【図2】第1の実施形態に係るプリント配線基板の製造
工程を示した垂直断面図である。
FIG. 2 is a vertical sectional view showing a manufacturing process of the printed wiring board according to the first embodiment.

【図3】第1の実施形態に係るプリント配線基板の製造
工程を示した垂直断面図である。
FIG. 3 is a vertical sectional view showing a manufacturing process of the printed wiring board according to the first embodiment.

【図4】第1の実施形態に係るプリント配線基板の製造
工程を示した垂直断面図である。
FIG. 4 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図5】第1の実施形態に係るプリント配線基板の製造
工程を示した垂直断面図である。
FIG. 5 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図6】第1の実施形態に係るプリント配線基板の製造
工程を示した垂直断面図である。
FIG. 6 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図7】第1の実施形態に係るプリント配線基板の製造
工程を示した垂直断面図である。
FIG. 7 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図8】第1の実施形態に係るプリント配線基板の製造
工程を示した垂直断面図である。
FIG. 8 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図9】第1の実施形態に係るプリント配線基板の製造
工程を示した垂直断面図である。
FIG. 9 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図10】第1の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 10 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図11】第1の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 11 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図12】第1の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 12 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図13】第1の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 13 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図14】第1の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 14 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図15】第1の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 15 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the first embodiment.

【図16】従来の多層板を用いた半導体パッケージの垂
直断面図である。
FIG. 16 is a vertical sectional view of a semiconductor package using a conventional multilayer board.

【図17】第1の実施形態に係る多層板を用いた半導体
パッケージの垂直断面図である。
FIG. 17 is a vertical sectional view of a semiconductor package using the multilayer board according to the first embodiment.

【図18】第2の実施形態に係るプリント配線基板の製
造方法のフローを示したフローチャートである。
FIG. 18 is a flowchart illustrating a flow of a method for manufacturing a printed wiring board according to the second embodiment.

【図19】第2の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 19 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the second embodiment.

【図20】第2の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 20 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the second embodiment.

【図21】第2の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 21 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the second embodiment.

【図22】第2の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 22 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the second embodiment.

【図23】第2の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 23 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the second embodiment.

【図24】第3の実施形態に係るプリント配線基板製造
方法のフローを示したフローチャートである。
FIG. 24 is a flowchart showing a flow of a method for manufacturing a printed wiring board according to the third embodiment.

【図25】第3の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 25 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the third embodiment.

【図26】第3の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 26 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the third embodiment.

【図27】第3の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 27 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the third embodiment.

【図28】第4の実施形態に係るプリント配線基板の製
造方法のフローを示したフローチャートである。
FIG. 28 is a flowchart showing a flow of a method for manufacturing a printed wiring board according to the fourth embodiment.

【図29】第4の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 29 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the fourth embodiment.

【図30】第4の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 30 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the fourth embodiment.

【図31】第4の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 31 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the fourth embodiment;

【図32】第4の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 32 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the fourth embodiment;

【図33】第4の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 33 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the fourth embodiment;

【図34】第5の実施形態に係るプリント配線基板の製
造方法のフローを示したフローチャートである。
FIG. 34 is a flowchart showing a flow of a method for manufacturing a printed wiring board according to the fifth embodiment.

【図35】第5の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 35 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the fifth embodiment;

【図36】第5の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 36 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the fifth embodiment.

【図37】第5の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 37 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the fifth embodiment;

【図38】第5の実施形態に係るプリント配線基板の製
造工程を示した垂直断面図である。
FIG. 38 is a vertical sectional view showing the manufacturing process of the printed wiring board according to the fifth embodiment;

【図39】従来のプリント配線基板の製造方法の工程を
示した垂直断面図である。
FIG. 39 is a vertical sectional view showing steps of a conventional method for manufacturing a printed wiring board.

【符号の説明】[Explanation of symbols]

3…プリプレグ(絶縁性基材)、 1a…配線層(第1の配線層)、 5a…配線層(第2の配線層)、 2…導体バンプ、 6…受動素子部材、 1…導体板(第1の導体板)、 5…導体板(第2の導体板)。 3 prepreg (insulating base material), 1a wiring layer (first wiring layer), 5a wiring layer (second wiring layer), 2 conductor bump, 6 passive element member, 1 conductor plate ( 1st conductor plate), 5 ... conductor plate (2nd conductor plate).

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/46 H05K 3/46 B Fターム(参考) 4E351 AA01 BB03 BB05 BB22 BB26 BB30 BB31 BB46 BB49 CC12 CC21 DD04 DD05 DD52 DD54 EE01 GG20 5E317 AA24 BB12 BB14 BB25 CC22 CC25 CD36 GG17 5E346 AA06 AA12 AA13 AA14 AA15 AA22 AA32 AA35 AA43 BB01 BB16 BB20 CC21 CC25 DD02 DD07 DD09 DD12 DD32 EE02 EE06 EE07 EE09 EE31 FF24 FF45 HH25 HH32 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H05K 3/46 BF term (Reference) 4E351 AA01 BB03 BB05 BB22 BB26 BB30 BB31 BB46 BB49 CC12 CC21 DD04 DD05 DD52 DD54 EE01 GG20 5E317 AA24 BB12 BB14 BB25 CC22 CC25 CD36 GG17 5E346 AA06 AA12 AA13 AA14 AA15 AA22 AA32 AA35 AA43 BB01 BB16 BB20 CC21 CC25 DD02 DD07 DD09 DD12 DD32 EE02 EE25 EE02 EE09 HEEFFEEH

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基材と、 前記絶縁性基材の両面にそれぞれ配設された第1の配線
層及び第2の配線層と、 前記絶縁性基材の厚さ方向に貫通して形成され、前記第
1の配線層と第2の配線層とを層間接続する導体バンプ
群と、 前記第1の配線層と前記第2の配線層との間に埋設さ
れ、前記導体バンプとの間で受動素子を形成する誘電性
組成物又は抵抗性組成物からなる受動素子部材と、 を具備するプリント配線基板。
An insulating substrate; a first wiring layer and a second wiring layer respectively disposed on both surfaces of the insulating substrate; A conductive bump group formed between the first wiring layer and the second wiring layer, the conductive bump group being interposed between the first wiring layer and the second wiring layer, and being embedded between the first wiring layer and the second wiring layer; A passive element member made of a dielectric composition or a resistive composition forming a passive element therebetween.
【請求項2】 第1の導体板上に略円錐形の導体バンプ
群を形成する工程と、 前記導体バンプ群上に絶縁性基材を載置する工程と、 前記第1の導体板と前記絶縁性基材とをプレスして前記
導体バンプ群を前記絶縁性基材に貫通させる工程と、 第2の導体板上に誘電性組成物又は抵抗性組成物を塗布
して受動素子部材を形成する工程と、 前記第1の導体板と前記第2の導体板とを、前記導体バ
ンプ群と前記受動素子部材とを対向させて載置する工程
と、 前記第1の導体板と前記第2の導体板とを前記導体バン
プ群のうちの少なくとも二つが前記受動素子部材と接す
るようにプレスして前記導体バンプ群の少なくとも二つ
の間で受動素子を形成する工程と、 前記第1の導体板と前記第2の導体板とをパターニング
してそれぞれ第1の配線層と第2の配線層とを形成する
工程と、 を具備するプリント配線基板の製造方法。
A step of forming a group of substantially conical conductive bumps on the first conductive plate; a step of placing an insulating base material on the group of conductive bumps; Pressing an insulating base material to penetrate the conductive bump group through the insulating base material; and applying a dielectric composition or a resistive composition on the second conductive plate to form a passive element member And placing the first conductor plate and the second conductor plate with the conductor bump group and the passive element member facing each other; and placing the first conductor plate and the second conductor plate together. Pressing a conductive plate between at least two of the conductive bumps to form a passive element between at least two of the conductive bumps; and a first conductive plate. And the second conductor plate are patterned to form a first wiring layer and a second Forming a second wiring layer. 2. A method for manufacturing a printed wiring board, comprising:
【請求項3】 第1の導体板上に略円錐形の導体バンプ
群を形成する工程と、 前記導体バンプ群上に絶縁性基材を載置する工程と、 前記第1の導体板と前記絶縁性基材とをプレスして前記
導体バンプ群を前記絶縁性基材に貫通させる工程と、 第2の導体板上の、前記導体バンプが当接する部分と前
記導体バンプが当接する部分との間に誘電性組成物又は
抵抗性組成物を塗布して、受動素子部材を形成する工程
と、 前記第1の導体板と前記第2の導体板とを、前記導体バ
ンプ群と前記受動素子部材とが対向する向きに載置する
工程と、 前記第1の導体板と前記第2の導体板とをプレスして前
記導体バンプ群を前記第2の導体板に当接させ、それに
より前記導体バンプと前記受動素子部材との間で受動素
子を形成する工程と、 前記第1の導体板及び第2の導体板とをパターニングし
てそれぞれ第1の配線層と第2の配線層とを形成する工
程と、 を具備するプリント配線基板の製造方法。
A step of forming a group of substantially conical conductive bumps on the first conductive plate; a step of placing an insulating base material on the group of conductive bumps; Pressing an insulative base material to penetrate the conductive bump group through the insulative base material; and forming a portion of the second conductive plate where the conductive bump abuts and where the conductive bump abuts. A step of forming a passive element member by applying a dielectric composition or a resistive composition between the first conductive plate and the second conductive plate, the conductive bump group and the passive element member And placing the first and second conductor plates against each other so that the group of conductor bumps abuts on the second conductor plate. Forming a passive element between the bump and the passive element member; and the first conductive plate And forming a first wiring layer and a second wiring layer by patterning the second conductor plate and the second wiring layer, respectively.
【請求項4】 絶縁性基材と、 前記絶縁性基材の両面にそれぞれ配設された第1の配線
層及び第2の配線層と、 前記絶縁性基材の厚さ方向に形成され、前記第1の配線
層と第2の配線層とを層間接続する導体バンプ群と、 前記導体バンプ群の少なくとも二つの導体バンプの間に
わたって配設され、前記二つの導体バンプとの間で受動
素子を形成する誘電性組成物又は抵抗性組成物からなる
受動素子部材と、 を具備するプリント配線基板。
4. An insulating base material, a first wiring layer and a second wiring layer respectively disposed on both surfaces of the insulating base material, and formed in a thickness direction of the insulating base material, A conductive bump group for interlayer-connecting the first wiring layer and the second wiring layer, a passive element disposed between at least two conductive bumps of the conductive bump group, and a passive element between the two conductive bumps; And a passive element member made of a dielectric composition or a resistive composition.
【請求項5】 第1の導体板上に略円錐形の第1の導体
バンプ群を形成する工程と、 前記第1の導体バンプ群上に第1の絶縁性基材を載置す
る工程と、 前記第1の導体板と前記第1の絶縁性基材とをプレスし
て前記第1の導体バンプ群を前記第1の絶縁性基材に貫
通させる工程と、 第2の導体板上の、前記第1の導体バンプが当接する部
分の隙間に誘電性組成物又は抵抗性組成物を塗布して、
第1の受動素子部材を形成する工程と、 前記第1の導体板と前記第2の導体板とを、前記第1の
導体バンプ群と前記第1の受動素子部材とを対向させて
載置する工程と、 前記第1の導体板と前記第2の導体板とをプレスして前
記第1の導体バンプ群を前記第2の導体板に当接させ、
それにより前記第1の導体バンプと前記第1の受動素子
部材との間で第1の受動素子を形成する工程と、 前記第1の導体板及び第2の導体板とをパターニングし
てそれぞれ第1の配線層と第2の配線層とを形成し、第
1の積層体を得る工程と、 前記第1の配線層上の、第2の導体バンプが当接する部
分の隙間に第2の誘電性組成物又は抵抗性組成物を塗布
して、第2の受動素子部材を形成する工程と、 第3の導体板上に略円錐形の第2の導体バンプ群を形成
する工程と、 前記第2の導体バンプ群上に第2の絶縁性基材を載置す
る工程と、 前記第3の導体板と前記第2の絶縁性基材とをプレスし
て前記第2の導体バンプ群を前記第2の絶縁性基材に貫
通させる工程と、 前記第1の積層体と前記第3の導体板とを、前記第2の
受動素子部材と前記第2の導体バンプ群とを対向させて
載置する工程と、 前記第1の積層体と前記第3の導体板とをプレスして前
記第2の導体バンプ群を前記第1の配線層に当接させ、
それにより前記第2の導体バンプと前記第2の受動素子
部材との間で第2の受動素子を形成する工程と、 前記第3の導体板をパターニングして第3の配線層を形
成する工程と、 を具備するプリント配線基板の製造方法。
5. A step of forming a first group of substantially conical conductive bumps on a first conductive plate, and a step of placing a first insulating base material on the first group of conductive bumps. Pressing the first conductive plate and the first insulating base material to penetrate the first conductive bump group through the first insulating base material; Applying a dielectric composition or a resistive composition to a gap between portions where the first conductive bumps abut,
Forming a first passive element member; placing the first conductor plate and the second conductor plate such that the first conductor bump group and the first passive element member face each other; Pressing the first conductor plate and the second conductor plate to bring the first conductor bump group into contact with the second conductor plate;
A step of forming a first passive element between the first conductive bump and the first passive element member; and patterning the first and second conductive plates and the second conductive plate, respectively. Forming a first wiring layer and a second wiring layer to obtain a first stacked body; and forming a second dielectric layer in a gap on the first wiring layer where the second conductive bump abuts. Applying a conductive composition or a resistive composition to form a second passive element member; forming a substantially conical second conductive bump group on a third conductive plate; Placing a second insulating base material on the second conductive bump group, and pressing the third conductive plate and the second insulating base material so that the second conductive bump group is A step of penetrating through a second insulating base material, the first laminate and the third conductor plate being connected to the second passive element member, Placing the second conductor bump group facing the second conductor bump group, and pressing the first laminate and the third conductor plate so as to remove the second conductor bump group from the first wiring layer. Abut
A step of forming a second passive element between the second conductive bump and the second passive element member, and a step of patterning the third conductive plate to form a third wiring layer A method for manufacturing a printed wiring board, comprising:
【請求項6】 第1の絶縁性基材と、 前記第1の絶縁性基材の第1の面に配設された第1の配
線層と、 前記第1の絶縁性基材の第2の面に配設された第2の配
線層と、 前記第1の絶縁性基材の厚さ方向に貫通して形成され、
前記第1の配線層と前記第2の配線層とを接続する第1
の導体バンプ群と、 前記第1の導体バンプ群の少なくとも二つの導体バンプ
の間にわたって配設され、前記二つの導体バンプ間で第
1の受動素子を形成する誘電性組成物又は抵抗性組成物
からなる第1の受動素子部材と、 前記第1の配線層を介して前記第1の絶縁性基材の第1
の面に積層された第2の絶縁性基材と、 前記第2の絶縁性基材の、前記第1の配線層と反対側の
面に配設された第3の配線層と、 前記第2の絶縁性基材の厚さ方向に貫通して形成され、
前記第1の配線層と前記第3の配線層とを層間接続する
第2の導体バンプ群と、 前記第2の導体バンプ群の少なくとも二つの導体バンプ
の間にわたって配設され、前記二つの導体バンプとの間
で第2の受動素子を形成する誘電性組成物又は抵抗性組
成物からなる第2の受動素子部材と、 を具備することを特徴とするプリント配線基板。
6. A first insulating base material, a first wiring layer disposed on a first surface of the first insulating base material, and a second wiring layer of the first insulating base material. A second wiring layer disposed on the surface of the first insulating base material, formed in the thickness direction of the first insulating base material,
A first connecting the first wiring layer and the second wiring layer;
And a dielectric composition or a resistive composition disposed between at least two conductor bumps of the first conductor bump group to form a first passive element between the two conductor bumps. A first passive element member comprising:
A second insulating base material laminated on a surface of the second insulating base material; a third wiring layer disposed on a surface of the second insulating base material opposite to the first wiring layer; 2 is formed penetrating in the thickness direction of the insulating base material,
A second conductor bump group for interlayer connection between the first wiring layer and the third wiring layer; and a second conductor bump group disposed between at least two conductor bumps of the second conductor bump group. A second passive element member made of a dielectric composition or a resistive composition that forms a second passive element with the bump.
【請求項7】 第1の導体板上に略円錐形の導体バンプ
群を形成する工程と、 前記導体バンプ群上に絶縁性基材を載置する工程と、 前記第1の導体板と前記絶縁性基材とをプレスして前記
導体バンプ群を前記絶縁性基材に貫通させる工程と、 第2の導体板上の、前記導体バンプが当接する部分の周
辺に誘電性組成物又は抵抗性組成物を塗布して、受動素
子部材を形成する工程と、 前記第1の導体板と前記第2の導体板とを、前記導体バ
ンプ群と前記受動素子部材とを対向させて載置する工程
と、 前記第1の導体板と前記第2の導体板とを前記絶縁性基
材を介してプレスして一部の前記導体バンプ群を前記前
記第2の導体板に当接させるとともに他の一部の前記導
体バンプ群を前記受動素子部材に当接させ、それにより
前記導体バンプ群、前記受動素子部材、及び前記第2の
導体板との間で受動素子を形成する工程と、 前記第1の導体板及び第2の導体板とをパターニングし
てそれぞれ第1の配線層と第2の配線層とを形成する工
程と、 を具備するプリント配線基板の製造方法。
7. A step of forming a group of substantially conical conductive bumps on a first conductive plate; a step of placing an insulating base material on the group of conductive bumps; Pressing an insulative base material to penetrate the conductive bump group through the insulative base material; and forming a dielectric composition or a resistive material around a portion of the second conductive plate where the conductive bump contacts. A step of applying a composition to form a passive element member; and a step of placing the first conductor plate and the second conductor plate with the conductor bump group and the passive element member facing each other. And pressing the first conductor plate and the second conductor plate via the insulating base material to bring a part of the conductor bump group into contact with the second conductor plate, and A part of the conductive bumps are brought into contact with the passive element member, whereby the conductive bumps are Forming a passive element between the passive element member and the second conductive plate; and patterning the first conductive plate and the second conductive plate to form a first wiring layer and a second conductive plate, respectively. Forming a wiring layer; and a method for manufacturing a printed wiring board, comprising:
【請求項8】 絶縁性基材と、 前記絶縁性基材の両面にそれぞれ配設された第1の配線
層及び第2の配線層と、 前記絶縁性基材の厚さ方向に貫通して形成され、前記第
1の配線層と第2の配線層とを接続する第1の導体バン
プ群と、 前記絶縁性基材と前記第1の配線層又は前記第2の配線
層との間に埋設され、誘電性組成物又は抵抗性組成物か
らなる受動素子部材と、 前記絶縁性基材の厚さ方向に貫通して形成され、前記第
1の配線層又は第2の配線層と前記受動素子部材との間
で受動素子を形成する第2の導体バンプ群と、を具備す
るプリント配線基板。
8. An insulating base material, a first wiring layer and a second wiring layer respectively provided on both surfaces of the insulating base material, and penetrating in a thickness direction of the insulating base material. A first group of conductive bumps formed and connecting the first wiring layer and the second wiring layer; and between the insulating base material and the first wiring layer or the second wiring layer. A passive element member buried and made of a dielectric composition or a resistive composition, formed so as to penetrate in a thickness direction of the insulating base material, and connected to the first wiring layer or the second wiring layer, A second conductive bump group forming a passive element with the element member.
【請求項9】 請求項8記載のプリント配線基板であっ
て、前記受動素子部材が、前記第2の導体バンプ群の先
端側と前記第1の配線層又は第2の配線層との間に介挿
されていることを特徴するプリント配線基板。
9. The printed wiring board according to claim 8, wherein said passive element member is located between a tip side of said second conductive bump group and said first wiring layer or said second wiring layer. A printed wiring board characterized by being interposed.
【請求項10】 請求項8記載のプリント配線基板であ
って、前記受動素子部材が、前記第2の導体バンプ群の
底面側と前記第1の配線層又は第2の配線層との間に介
挿されていることを特徴するプリント配線基板。
10. The printed wiring board according to claim 8, wherein said passive element member is provided between a bottom surface of said second conductive bump group and said first wiring layer or said second wiring layer. A printed wiring board characterized by being interposed.
【請求項11】 第1の導体板上に略円錐形の導体バン
プ群を形成する工程と、 前記導体バンプ群上に絶縁性基材を載置する工程と、 前記第1の導体板と前記絶縁性基材とをプレスして前記
導体バンプ群を前記絶縁性基材に貫通させる工程と、 第2の導体板上の、前記導体バンプ群のうちの一部の導
体バンプが当接する部分に誘電性組成物又は抵抗性組成
物を塗布して、受動素子部材を形成する工程と、 前記第1の導体板と前記第2の導体板とを、前記導体バ
ンプ群と前記受動素子部材とが対向する向きに載置する
工程と、 前記第1の導体板と前記第2の導体板とをプレスして前
記導体バンプ群を前記第2の導体板に当接させ、それに
より前記一部の導体バンプと前記受動素子部材との間で
受動素子を形成する工程と、 前記第1の導体板及び第2の導体板とをパターニングし
てそれぞれ第1の配線層と第2の配線層とを形成する工
程と、 を具備するプリント配線基板の製造方法。
11. A step of forming a group of substantially conical conductive bumps on a first conductive plate; a step of placing an insulating base material on the group of conductive bumps; Pressing an insulating base material to penetrate the conductive bump group through the insulating base material; and pressing a part of the conductive bump group on the second conductive plate where a part of the conductive bumps abut. A step of applying a dielectric composition or a resistive composition to form a passive element member; and forming the first conductor plate and the second conductor plate by using the conductor bump group and the passive element member. Placing in a facing direction, pressing the first conductor plate and the second conductor plate to bring the conductor bump group into contact with the second conductor plate; Forming a passive element between a conductive bump and the passive element member; Forming a first wiring layer and a second wiring layer by patterning the first wiring layer and the second conductor plate, respectively.
【請求項12】 第1の導体板の一部に誘電性組成物又
は抵抗性組成物を塗布して、受動素子部材を形成する工
程と、 前記第1の導体板上及び前記受動素子部材上に略円錐形
の導体バンプ群を形成する工程と、 前記導体バンプ群上に絶縁性基材と、更にその上に第2
の導体板とを載置する工程と、 前記第1の導体板と前記第2の導体板とをプレスして前
記導体バンプ群を前記絶縁性基材に貫通させると同時に
前記第1の導体板、前記受動素子部材、及び前記導体バ
ンプ群の一部との間で受動素子を形成する工程と、 前記第1の導体板及び第2の導体板とをパターニングし
てそれぞれ第1の配線層と第2の配線層とを形成する工
程と、 を具備するプリント配線基板の製造方法。
12. A step of applying a dielectric composition or a resistive composition to a part of the first conductor plate to form a passive element member, and on the first conductor plate and the passive element member Forming a substantially conical conductive bump group on the conductive bump group; an insulating base material on the conductive bump group;
Placing the first conductive plate and the second conductive plate to press the first conductive plate and the second conductive plate so that the conductive bump group penetrates through the insulating base material, and at the same time, the first conductive plate Forming a passive element between the passive element member and a part of the conductive bump group; patterning the first conductive plate and the second conductive plate to form a first wiring layer, Forming a second wiring layer. A method for manufacturing a printed wiring board, comprising:
【請求項13】 絶縁性基材と、 前記絶縁性基材の両面にそれぞれ配設された第1の配線
層及び第2の配線層と、 誘電性組成物又は抵抗性組成物からなり、前記絶縁性基
材の厚さ方向に前記第1の配線層と第2の配線層とを層
間接続し、前記第1の配線層及び第2の配線層との間で
受動素子を形成するバンプと、 を具備するプリント配線基板。
13. An insulating base material, a first wiring layer and a second wiring layer respectively disposed on both surfaces of the insulating base material, and a dielectric composition or a resistive composition, A bump for interconnecting the first wiring layer and the second wiring layer in the thickness direction of the insulating base material and forming a passive element between the first wiring layer and the second wiring layer; A printed wiring board comprising:
JP35050099A 1999-12-09 1999-12-09 Printed circuit board and method for manufacturing printed circuit board Expired - Fee Related JP3964085B2 (en)

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