JP2001156605A - Delay circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay circuit device that can keep the ratio of the delay time of output data to the period of a clock signal constant even when the period of the outputted clock signal is changed. SOLUTION: This delay circuit device is provided with a voltage controlled oscillator 13 that oscillates a clock signal based on a control signal received from an oscillating frequency control voltage input terminal 7, a voltage mirror circuit 11 that converts the control signal received from the oscillating frequency control voltage input terminal 7 in response to a mirror ratio received from a mirror ratio changeover input terminal 12, and a delay circuit 14 that delays data received from a data input terminal 9 based on a conversion signal received from the voltage mirror circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit device, and more particularly, to a delay circuit for delaying input data for a predetermined time and outputting the delayed data.

[0002]

2. Description of the Related Art A conventional delay circuit device has a unit delay time Δ
A delay circuit formed by cascade-connecting delay elements having t (N is a natural number) and a selector for selecting any one of the outputs of the delay elements are provided below. This will be described with reference to FIG.

FIG. 2 is a block diagram showing a configuration of a conventional delay circuit device. In the figure, 21 is the unit delay time Δ
t, a delay circuit 22 formed by cascading N delay elements 21, a data input terminal 23,
Is a data output terminal, 25 is a selector for selecting any one of the outputs of the N delay elements 21, and 26 is a control signal input terminal.

The operation of the conventional delay circuit device configured as described above will be described below. The first-stage delay element 21 of the delay circuit 22 outputs the data input from the data input terminal 23 to the second-stage delay element 21 and the selector 25 with a delay of the unit delay time Δt. Second stage delay element 21
Delays the data input from the first-stage delay element 21 by the unit delay time Δt and outputs the delayed data to the next-stage delay element 21 and selector 25. The final stage (Nth stage) delay element 21 outputs the data input from the preceding stage delay element 21 to the selector 25 with a delay of the unit delay time Δt. Thus, the delay circuit 22 outputs data delayed by Δt, Δt × 2,... And Δt × N to the selector 25. Selector 25
Selects one of the N delayed data input from the delay circuit 22 based on the signal input from the control signal input terminal 26, and outputs the data to the data output terminal 24.

As described above, the conventional delay circuit device delays the data input from the data input terminal 23 by an integral multiple of the unit delay time Δt of the delay element 21.
The data was output to the data output terminal 24.

Further, the conventional delay circuit device is supplied with a clock signal from the outside or oscillates and outputs the clock signal. However, the period of the clock signal is independent of the delay time of the delay circuit of the device. .

[0007]

As described above, in the conventional delay circuit device, the delay time of the output data is set to an integral multiple of the unit delay time Δt of the delay element, so that the clock supplied or output is output. When the period of the signal changes, the ratio of the delay time of the output data to the period of the clock signal changes.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and maintains a constant ratio between the delay time of output data and the cycle of a clock signal even when the cycle of the output clock signal changes. It is an object of the present invention to provide a delay circuit device that can perform the operation.

[0009]

According to a first aspect of the present invention, there is provided a delay circuit device comprising: a control signal input terminal for inputting a control signal for controlling a frequency of a clock signal; and the control signal input terminal. A clock oscillating means for oscillating a clock signal based on a control signal input from the oscilloscope, a clock output terminal for outputting a clock signal oscillated from the clock oscillating means, a clock signal frequency and a desired output data delay time. A mirror ratio input terminal for inputting a mirror ratio, a mirror circuit for converting a control signal input from the control signal input terminal according to the mirror ratio input from the mirror ratio input terminal, and a data input for inputting desired data Terminal and the output of data input from the data input terminal are delayed based on the control signal converted in the mirror circuit. A delay circuit that, characterized by comprising a data output terminal for outputting the data input to the delay circuit.

[0010]

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an example of the configuration of the delay circuit device according to Embodiment 1 of the present invention. In the figure, 1-6
Is a voltage-controlled inverter (delay element) whose clock signal frequency or unit delay time is controlled by a voltage; 7 is an oscillation frequency control voltage input terminal for inputting a voltage for controlling the frequency of the clock signal; 8 is a clock output terminal; Is a data input terminal, 10 is a data output terminal, 11 is a voltage mirror circuit, 12 is a mirror ratio switching input terminal, 13 is formed by cascading voltage controlled inverters 1 to 3, and the output of the voltage controlled inverter 3 is voltage controlled. A voltage-controlled oscillator (clock oscillating means) 14 serving as an input to the inverter 1 is a delay circuit formed by cascading voltage-controlled inverters 4 to 6.

The operation of the delay circuit device configured as described above will be described with reference to FIG. The voltage controlled oscillator 13 oscillates a clock signal based on the control voltage input from the oscillation frequency control voltage input terminal 7 and outputs the clock signal to the clock output terminal 8. The voltage mirror circuit 11 converts the control voltage input from the oscillation frequency control voltage input terminal 7 according to the mirror ratio input from the mirror ratio switching input terminal 12, and outputs the converted voltage to the delay circuit 14. The delay circuit 14 delays data input from the data input terminal 9 based on the converted voltage input from the voltage mirror circuit 11, and outputs the data to the data output terminal 10.

As described above, according to the delay circuit device of the first embodiment, the voltage controlled oscillator 13 oscillates the clock signal based on the control voltage input from the oscillation frequency control voltage input terminal 7, and the delay circuit 14 delays the input data, and the voltage mirror circuit 11
Therefore, even when the control voltage changes and the cycle of the output clock signal changes, the ratio between the delay time of the output data and the cycle of the clock signal can be kept constant.

Further, according to the delay circuit device according to the first embodiment, the mirror ratio switching input terminal 12 inputs the mirror ratio, and the voltage mirror circuit 11 applies the control voltage input from the oscillation frequency control voltage input terminal 7 to the mirror voltage. Convert according to the mirror ratio,
Since the delay circuit delays the input data based on the voltage input from the voltage mirror circuit 11, the ratio of the delay time of the output data to the change of the cycle of the clock signal can be changed.

In the first embodiment, a voltage controlled oscillator formed by cascading three voltage controlled inverters is used as the clock oscillating means. However, the number of connected voltage controlled inverters is not limited to three. If the number is an odd number of 2M-1 (M is a natural number), the same effect as described above can be obtained.

In the first embodiment, the number of connected voltage-controlled inverters forming the voltage-controlled oscillator is equal to the number of connected voltage-controlled inverters forming the delay circuit. It does not have to be.

In the first embodiment, the voltage-controlled inverter controlled by the voltage and the voltage mirror circuit are used. However, the same effect as described above can be obtained by using the current-controlled inverter and the current mirror circuit controlled by the current. Can be obtained.

In the first embodiment, the voltage control inverter is used as the delay element. However, the voltage control NAND, the voltage control NOR, the current control NAND, or the current control NOR is used.
The same effect can be obtained by using.

[0018]

As described above, according to the present invention, a control signal input terminal for inputting a control signal for controlling the frequency of a clock signal, and a clock signal is oscillated based on the control signal input from the control signal input terminal. A clock oscillating means, a clock output terminal for outputting a clock signal oscillated from the clock oscillating means, a mirror ratio input terminal for inputting a mirror ratio between a frequency of the clock signal and a delay time of desired output data, A mirror circuit for converting a control signal input from the control signal input terminal according to a mirror ratio input from the mirror ratio input terminal, a data input terminal for inputting desired data, and a data input terminal for inputting data input from the data input terminal. A delay circuit for delaying an output based on the control signal converted by the mirror circuit; and a data input to the delay circuit. And a data output terminal for outputting a clock signal, the delay circuit is controlled by a control signal that controls the frequency of the clock signal, and the delay time of the data to be output and the clock are output even when the cycle of the output clock signal changes. The ratio with the period of the signal can be kept constant, and the effect of changing the ratio of the delay time of the output data to the change of the period of the clock signal can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of a delay circuit device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a conventional delay circuit device.

[Explanation of symbols]

 1 to 6 voltage control inverter 7 oscillation frequency control voltage input terminal 8 clock output terminal 9 data input terminal 10 data output terminal 11 voltage mirror circuit 12 mirror ratio switching input terminal 13 voltage controlled oscillator 14 delay circuit 21 delay element 22 delay circuit 23 data Input terminal 24 Data output terminal 25 Selector 26 Control signal input terminal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takahiro Parki 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Incorporated F term (reference) 5J001 BB00 BB10 BB11 BB12 BB20 DD01 DD06 5J056 AA39 BB01 CC00 CC05 CC16 5J098 AB04 AB22 AC04 AC20 AD03 FA03 FA09 5J106 AA03 CC03 CC58 DD08 KK01 KK12 KK32

Claims (1)

[Claims] A control signal input terminal for inputting a control signal for controlling a frequency of a clock signal; a clock oscillating means for oscillating a clock signal based on a control signal input from the control signal input terminal; A clock output terminal for outputting a clock signal oscillated from a clock signal, a mirror ratio input terminal for inputting a mirror ratio between a frequency of the clock signal and a delay time of desired output data, and a control signal input from the control signal input terminal A mirror circuit that converts the data according to the mirror ratio input from the mirror ratio input terminal, a data input terminal that inputs desired data, and a control that converts the output of the data input from the data input terminal in the mirror circuit. A delay circuit for delaying based on a signal, and a data output terminal for outputting data input to the delay circuit Delay circuit device comprising the and.