JP2002094495A - Voltage-controlled oscillator and multi-bit rate timing extracting circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate timing extraction with respect to reception signals having multiple different bit rates. SOLUTION: Each time a reception signal is changed from 'H' to 'L' and from 'L' to 'H' states, re-timing is performed according to the changing point by a timing extracting circuit. The oscillation frequency range of voltage- controlled oscillators 8A and 8B of a clock-recovery circuit 6 is switched according to a bit rate identification signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator and a multi-bit rate / timing extracting circuit using the same.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional burst signal timing extraction circuit provided in a receiving device in a main device. In FIG. 5, 1 is a burst signal input terminal,
Reference numeral 51 denotes a timing extraction circuit that generates a clock that matches the bit phase of the received burst signal. Reference numeral 3 denotes an output terminal of the clock. Reference numeral 52 denotes a reference clock source that generates a reference clock having the same frequency as the bit rate of the received burst signal. .

The timing extracting circuit 51 comprises a clock reproducing circuit 53 and a PLL circuit 54. First, the clock recovery circuit 53 oscillates when the signal at the reception signal input terminal 55a is "H", its oscillation frequency is controlled by the control voltage at the control signal input terminal 55b, and outputs an oscillation clock from the output terminal 55c. Voltage-controlled oscillators 55A and 55B, an inverter 56 for inverting a burst signal received at the burst signal input terminal 1 and inputting the inverted signal to the voltage-controlled oscillator 55B,
It comprises a two-input OR gate 57 for calculating the logical sum of the output signals of 5A and 55B.

The PLL circuit 54 includes a voltage control oscillator 55C having the same configuration and characteristics as those of the voltage control oscillators 55A and 55B, a reference clock from the reference clock source 52, and a phase of an output clock from the voltage control oscillator 55C. And a control voltage generating circuit 59 for applying a control voltage to the voltage control oscillators 55A, 55B and 55C according to the comparison output signal of the phase comparator 58. ing. The reception signal input terminal 55a of the voltage control oscillator 55C is always pulled up to “H”.

FIG. 6 shows the voltage control oscillator 55 described above.
It is a block diagram which shows the internal structure of A, 55B, 55C. In FIG. 6, reference numeral 61 denotes a variable delay circuit whose delay amount changes according to a control voltage input to a control voltage input terminal 55b, and is configured by connecting n variable delay elements 611 to 61n in series. 62 is a variable delay circuit 6
2 is a two-input NA that inverts and outputs the output signal from 1 when the received signal input to the received signal input terminal 55a is “H”.
An ND gate 63 is an inverter that inverts the output signal of the NAND gate 62 and outputs the inverted signal to the output terminal 55c.

The voltage controlled oscillators 55A, 55B,
In 55C, the oscillation operation is performed when the reception signal input to the reception signal input terminal 55a is “H”, and the frequency at this time is controlled by the control voltage of the control voltage input terminal 55b. When the signal is "L", the oscillation operation is stopped. FIG. 8 shows the operation waveform of each part. H is an output signal of the NAND gate 62, and H 'is an output signal of the variable delay circuit 61.

Next, the operation of the timing extraction circuit of FIG. 5 will be described with reference to the waveform diagram of FIG. In the PLL circuit 54, shortly after power-on, the phase of the reference clock G 'output from the reference clock source 52 and the phase of the clock F' output from the continuously oscillating voltage control oscillator 55C are synchronized, and the control voltage at that time is controlled. Since the voltage is output from the voltage generation circuit 59, the voltage control oscillators 55A and 55B of the clock recovery circuit 53 that inputs the same control voltage to the control voltage input terminal 55b are in a state where they can oscillate. When the signal input terminal 55a is at "H", oscillation is performed at the same frequency as the voltage control oscillator 55C.

Here, when the received signal A is input from the burst signal input terminal 1 to the clock recovery circuit 53, it is directly input to one voltage control oscillator 55A and inverted by the inverter 56 to the other voltage control oscillator 55B. The received signal B is input. The received signal A is an NRZ signal, and “H” of the data is “1” in the “H” portion.
The above is continuous. In the “L” part, “L” of data is 1
The above is continuous. When the reception signal A is "H", the oscillation operation is performed by one voltage control oscillator 55A, and when the reception signal A is "L", the other voltage control oscillator 55B
The oscillating operation is performed by.

At this time, the voltage control oscillators 55A, 55A
5B starts oscillating when the reception signal input to the reception signal input terminal 55a changes from “L” to “H”, and the output signals C ′ and D ′ appearing at the output terminal 55c are set to “H”. Therefore, timing extraction (retiming) is performed in which the clock phase is returned to an appropriate position in accordance with the sign change of the received signal A. This operation is complemented by the voltage control oscillators 55A and 55B each time the received signal A changes from "H" to "L" and "L" to "H". The output signal E ′ appearing at the terminal 3 is a continuous clock phase-synchronized with the bit of the received signal A.

As described above, the PLL for stabilizing the frequency
By providing a portion of the circuit 54 and a portion of the timing extraction circuit 52 that instantaneously adjusts the clock to the phase of the received signal, instantaneous timing extraction for the burst signal is completed. However, the maximum receivable number of consecutive same-codes is determined by the magnitude of the difference between the frequency of the input signal A and the frequency of the reference clock G '. References: M. Banu and AEDunlop, E1ect
ron. Lett. vol. 28, No. 23, pp. 2127-2130, 1992.

[0011]

However, the conventional timing extraction circuit for a burst signal assumes that the oscillation frequency of the voltage controlled oscillator is fixed and that a signal of a fixed bit rate is received. . For this reason,
A single timing extraction circuit cannot receive a signal obtained by time multiplexing (time division multiplexing) signals of a plurality of bit rates greatly different from a predetermined bit rate.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a voltage controlled oscillator capable of switching an oscillation frequency range and to receive a signal obtained by time-multiplexing a plurality of signals having greatly different bit rates by using the voltage controlled oscillator. An object of the present invention is to provide a multi-bit rate / timing extraction circuit which can be used.

[0013]

According to a first aspect of the present invention, there is provided a delay circuit wherein one input port is connected to a reception signal input terminal, and the delay circuit is connected between the other input port and the output port. And a two-input AND gate whose output port is connected to an output terminal, wherein the delay circuit is controlled by a control voltage input to a control voltage input terminal. And one of the plurality of fixed delay elements is selected according to a bit rate identification signal input to an identification signal input terminal, the plurality of fixed delay elements having different delay amounts, and is connected in series to the variable delay circuit. And a fixed delay circuit.

According to a second aspect of the present invention, a delay circuit has one input port connected to a reception signal input terminal, the delay circuit connected between the other input port and an output port, and the output port connected to an output terminal. A voltage controlled oscillator having a connected two-input AND gate,
A variable delay circuit whose delay amount is controlled by a control voltage input to a control voltage input terminal and a fixed delay element connected in series to the variable delay circuit are configured as one set, and the variable delay circuit is configured by a plurality of sets. The common control voltage is input as the same, and the fixed delay element has a different amount of delay in each set, and any one set is selected according to the bit rate identification signal input to the identification signal input terminal. It was to so.

According to a third aspect of the present invention, there is provided a multi-bit rate / timing extraction circuit comprising: a first voltage-controlled oscillator in which a reception signal is directly input to a reception signal input terminal; A second voltage-controlled oscillator, a clock recovery circuit comprising an OR gate in which output terminals of the first and second voltage-controlled oscillators are connected to respective input ports, a third voltage-controlled oscillator, and the third voltage A phase comparator for comparing the phase of the clock at the output terminal of the oscillator with the reference clock; and a PLL circuit including a control voltage generation circuit for generating a control voltage according to the comparison result of the phase comparator. 3. The voltage controlled oscillator according to claim 1 or 2, wherein the second and third voltage controlled oscillators are the voltage controlled oscillator according to claim 1 or 2, and the control voltage of the first, second and third voltage controlled oscillators is controlled. The output of the control voltage generation circuit is commonly connected to the input terminal, the identification signal input terminals of the first and second voltage control oscillators are commonly connected, and the reception signal input terminal of the third voltage control oscillator is connected to a high potential. And a fixed signal is input to the identification signal input terminal.

[0016]

FIG. 1 is a block diagram showing an embodiment of a multi-bit rate / timing extraction circuit according to the present invention. In FIG. 1, 1 is a burst signal input terminal, 2 is a timing extraction circuit that generates a clock that matches the bit phase of the input burst signal, 3 is an output terminal of the clock, 4 is a reference clock source that generates a reference clock,
Reference numeral 5 denotes a bit rate identification signal input terminal for identifying the bit rate of the burst signal input to the reception signal input terminal 1 by a circuit (not shown) and inputting the identification signal.

The timing extracting circuit 2 comprises a clock reproducing circuit 6 and a PLL circuit 7. First, the clock recovery circuit 6 oscillates when the signal at the reception signal input terminal 8a is "H", the oscillation frequency is controlled by the control voltage at the control signal input terminal 8b, and the identification signal input terminal 8d
The oscillation frequency range is switched by a bit rate identification signal input to the input terminal 8c, and the voltage control oscillators 8A and 8B for outputting an oscillation clock from the output terminal 8c and the voltage control oscillator 8B for inverting the signal input to the burst signal input terminal 1 And a two-input O which takes the logical sum of the output signals of the voltage-controlled oscillators 8A and 8B.
And an R gate 10. The output frequency variable range of the voltage controlled oscillators 8A and 8B is wider than that of the conventional voltage controlled oscillator.

The PLL circuit 7 includes a voltage control oscillator 8C having the same configuration and characteristics as those of the voltage control oscillators 8A and 8B, a reference clock from the reference clock source 4, and an output clock signal from the voltage control oscillator 8C. Phase comparator 11 for comparing phases and outputting the comparison signal
And a control voltage generating circuit 12 for applying a control voltage to the voltage control oscillators 8A, 8B, 8C according to the output signal of the phase comparator 11. The reception signal input terminal 8a of the voltage control oscillator 8C is always pulled up to "H", and a fixed voltage Va for selecting a specific oscillation frequency range is applied to the identification signal input terminal 8d.

Next, the operation will be described with reference to the waveform diagram of FIG. In the PLL circuit 7, some time after the power is turned on, the phase of the reference clock G output from the clock source 4 and the phase of the clock F output from the continuously oscillating voltage control oscillator 8C are synchronized, and the control voltage at that time becomes equal to the control voltage generation circuit 12
The voltage control oscillators 8A and 8B of the clock recovery circuit 6 which input the same control voltage to the control voltage input terminal 8b also output the same control voltage to the identification signal input terminal 8d if they can oscillate. Oscillation is performed at a frequency corresponding to the control voltage in a specific frequency range corresponding to the input bit rate identification signal I. In this way, the control voltage is stabilized by the PLL circuit 7 so as to correspond to the reference clock, that is, not to fluctuate due to the influence of the external environment.

Here, when the received signal A is input from the burst signal input terminal 1 to the clock recovery circuit 6, it is input as it is to one voltage control oscillator 8A and inverted by the inverter 9 to the other voltage control oscillator 8B. Signal B
Enter as Note that the received signal A is an NRZ signal, and “H” of data is continuous in the “H” portion.
In the “L” part, “L” of the data is continuous. When the reception signal A is “H”, the oscillation operation is performed by one voltage control oscillator 8A, and when the reception signal A is “L”, the oscillation operation is performed by the other voltage control oscillator 8B. In these voltage controlled oscillators 8A and 8B, the bit rate identification signal I is input to the identification signal input terminal 8d and the oscillation frequency range (range) is switched according to the bit rate. Oscillates a clock with a frequency.

At this time, the voltage control oscillators 8A and 8B
Starts oscillation when the reception signals A and B input to the reception signal input terminal 8a change from "L" to "H", and the signals C and D at the output terminal 8c rise to "H". Therefore, timing extraction (retiming) is performed in which the clock phase is returned to an appropriate position according to the change in the sign of the received signal A. Since this operation is complemented by the voltage controlled oscillators 8A and 8B, the output signal E, which is ORed by the OR gate 10 and appears at the output terminal 3, is a continuous clock phase-synchronized with the bit of the received signal A. .

As described above, when a plurality of bit rate signals are input in a time multiplexed (time division multiplexed) manner, the frequency range is switched by the bit rate identification signal each time the bit rate changes, and the control voltage is controlled. Thus, the frequency is adjusted to the frequency corresponding to the bit rate, and a continuous clock phase-synchronized with the bits of the received signal at the bit rate is obtained.

FIG. 3 shows the above-described voltage controlled oscillator 8A,
It is a block diagram which shows the structure of 8B, 8C. In FIG. 3, reference numeral 21 denotes a selector for switching an output port according to a bit rate identification signal I input to the identification signal input terminal 8d, and reference numeral 22 denotes m fixed delay elements 221 having different delays connected to respective output ports of the selector 21. , 222,
,..., 22 m are fixed delay circuits, and 23 is an m-input OR for taking a logical sum of m outputs of the fixed delay circuit 22.
A gate 24 is a variable delay circuit composed of n delay elements 241 to 24n for delaying the output signal of the OR gate 23 by an amount corresponding to a control voltage input to the control signal input terminal 8b, and 25 is a variable delay circuit 24 A NAND gate 26 which takes the logical sum of the signal from the input terminal 8a and the signal from the reception signal input terminal 8a is an inverter for inverting the output signal of the NAND gate 25.

The voltage controlled oscillators 8A, 8B, 8C
Then, NAND gate 25 → selector 21 → fixed delay circuit 22 → OR gate 23 → variable delay circuit 24 → NAND
Oscillation is performed so that the propagation delay time of the loop of the gate 25 corresponds to a half cycle of the oscillation clock. The oscillation frequency is adjusted by the fixed delay circuit 2 selected by the bit rate identification signal I input to the identification signal input terminal 8d.
The adjustment is performed by adjusting the total delay amount of the delay amount (coarse adjustment) by the two specific fixed delay elements and the delay amount (fine adjustment) by the variable delay circuit 24. Since the delay amount of the variable delay circuit 24 is adjusted by the PLL circuit 7, it mainly serves to suppress the influence of the external environment and stabilize the clock.

FIG. 9A shows this voltage-controlled oscillator 8
A shows oscillation frequency characteristics with respect to control voltages A, 8B, and 8C. One of a plurality of characteristic curves is selected by a bit rate identification signal I, and a specific oscillation frequency is determined by a control voltage within the range. Is done. Therefore,
A conventional voltage controlled oscillator 55 having only one characteristic curve
The oscillation frequency range is greatly expanded as compared with the characteristic diagrams of A, 55B, and 55C ((b) of FIG. 9), and it is possible to obtain a clock that is phase-synchronized with the bits of the burst signal having many different bit rates. Become like

FIG. 4 shows the voltage-controlled oscillator 8A,
It is a block diagram which shows the structure of another example of 8B, 8C. The difference from FIG. 3 is that each delay element 2 of the fixed delay circuit 22
, 22m, are individually connected in series with the variable delay circuit 24, and a plurality of fixed delay elements and variable delay circuits are provided as one set, and the output signal of the variable delay circuit 24 is set to m. Input to the input OR gate 23, and the OR
The difference is that the output of the gate 23 is input to the NAND gate 25.

[0027]

As described above, according to the voltage controlled oscillator of the present invention, the oscillation frequency range of the clock can be greatly expanded. For a signal, a clock phase-synchronized with the bit can be reproduced. Further, compared to a case where a plurality of timing extraction circuits are simply configured in parallel in correspondence with input signals of different bit rates, there is an advantage that the circuit can be made smaller and power consumption can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a timing extraction circuit according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the timing extraction circuit of FIG. 1;

FIG. 3 is a block diagram of a voltage control oscillator of the timing extraction circuit of FIG. 1;

FIG. 4 is a block diagram of a voltage control oscillator as another example of the timing extraction circuit of FIG. 1;

FIG. 5 is a block diagram of a conventional timing extraction circuit.

FIG. 6 is a block diagram of a voltage control oscillator of the timing extraction circuit of FIG. 5;

FIG. 7 is an operation waveform diagram of the timing extraction circuit of FIG. 5;

8 is an operation waveform diagram of the voltage-controlled oscillator of FIG.

9A is a characteristic diagram of the oscillation frequency with respect to the control voltage of the voltage controlled oscillator of FIGS. 3 and 4, and FIG. 9B is a characteristic diagram of the oscillation frequency with respect to the control voltage of the voltage controlled oscillator of FIG.

[Explanation of symbols]

1: burst signal input terminal, 2: timing extraction circuit,
3: output terminal, 4: reference clock source, 5: bit rate identification signal input terminal, 6: clock recovery circuit, 7: PLL
Circuit, 8A, 8B, 8C: Voltage controlled oscillator, 8a:
Received signal input terminal, 8b: control signal input terminal, 8c: output terminal, 8d: identification signal input terminal, 9: inverter, 1
0: OR gate, 11: phase comparator, 12: control voltage generation circuit 21: selector, 22: fixed delay circuit, 221, 22
2, 22m: fixed delay element, 23: OR gate, 24:
Variable delay circuits, 241 to 24n: variable delay elements, 25:
NAND gate, 26: inverter 51: timing extraction circuit, 52: reference clock source, 53: clock recovery circuit, 54: PLL circuit, 55A, 55B, 55C: voltage controlled oscillator, 55a: reception signal input terminal, 55b:
Control signal input terminal, 55c: output terminal, 56: inverter, 57: OR gate, 58: phase comparator, 59: control voltage generation circuit 61: variable delay circuit, 611 to 61n: variable delay element,
62: NAND gate, 63: inverter

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J043 AA03 AA05 AA22 LL01 5K047 AA05 GG05 GG09 GG10 GG44 GG45 MM36 MM46 MM50 MM53 MM63

Claims (3)

[Claims] A delay circuit having one input port connected to a reception signal input terminal, the delay circuit connected between the other input port and an output port, and the output port connected to an output terminal; A voltage-controlled oscillator having an input AND gate, wherein the delay circuit includes a variable delay circuit whose delay amount is controlled by a control voltage input to a control voltage input terminal, and a plurality of fixed delay elements having different delay amounts. A fixed delay circuit that selects one of the plurality of fixed delay elements and is connected in series to the variable delay circuit in accordance with the bit rate identification signal input to the identification signal input terminal. Voltage controlled oscillator. 2. A delay circuit, wherein one input port is connected to a reception signal input terminal, the delay circuit is connected between the other input port and an output port, and the output port is connected to an output terminal. A voltage controlled oscillator comprising an input AND gate, wherein the delay circuit is a variable delay circuit whose delay amount is controlled by a control voltage input to a control voltage input terminal, and a fixed delay element connected in series to the variable delay circuit As one set, the variable delay circuit inputs the same control voltage as the same in each set, and the fixed delay element varies the amount of delay in each set, and is connected to the identification signal input terminal. A voltage controlled oscillator characterized in that any one set is selected in response to an input bit rate identification signal. 3. A first voltage controlled oscillator in which a received signal is directly input to a received signal input terminal, a second voltage controlled oscillator in which the received signal is inverted and input to a received signal input terminal, and the first and second oscillators. A clock recovery circuit comprising an OR gate in which an output terminal of the voltage-controlled oscillator is connected to each input port; a third voltage-controlled oscillator; and a phase comparison between a clock of an output terminal of the third voltage oscillator and a reference clock And a PLL circuit comprising a control voltage generating circuit for generating a control voltage according to the comparison result of the phase comparator. The first, second, and third voltage controlled oscillators are 3. The voltage controlled oscillator according to item 1 or 2, wherein an output of the control voltage generating circuit is commonly connected to control voltage input terminals of the first, second, and third voltage controlled oscillators; The identification signal input terminals of the first and second voltage controlled oscillators are commonly connected, the reception signal input terminal of the third voltage controlled oscillator is pulled up to a high potential, and a fixed signal is input to the identification signal input terminal. A multi-bit rate / timing extraction circuit characterized in that: