JP2001143492A - Sample-and-hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample-and-hold circuit which can be operated in a wide band, while reducing the influence of clock-feed-through. SOLUTION: In a sample-and-hold circuit, having a sample switch sampling analog input voltage and a hold-capacitor holding analog input voltage sampled by the sample switch and outputting it as analog output voltage, analog output voltage is compared with reference voltage, when the analog output voltage is lower than the reference voltage, the circuit helps to charge the hold- capacitor, and when the analog output voltage is higher than the reference voltage, the circuit helps to discharge the hold-capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample-and-hold circuit which samples an analog input voltage and outputs the sampled and held analog output voltage as an analog output voltage.

[0002]

2. Description of the Related Art Generally, a sample and hold circuit includes a sample switch for sampling an analog input voltage and a hold capacitor for holding the analog input voltage sampled by the sample switch and outputting the analog input voltage as an analog output voltage. Be composed.
In the sample and hold circuit, by turning on and off the sample switch once, the analog input voltage at the time when the sample switch is turned off is held in the hold capacitor.

A transistor is usually used as a sample switch. Therefore, when the sample switch is turned off, the parasitic capacitance existing between the gate and the source and between the gate and the drain of the transistor is combined with the hold capacitor, and the hold voltage held by the hold capacitor fluctuates. Such a phenomenon that the hold voltage of the hold capacitor fluctuates due to the influence of the parasitic capacitance of the sample switch is called clock feedthrough.

Due to the influence of the clock feedthrough, the error amount of the hold voltage held in the hold capacitor depends on the input level of the analog input voltage.
The analog input voltage tends to decrease as it approaches the intermediate potential between the power supply and the ground, and conversely, tends to increase as it approaches the power supply or the ground. Therefore, for example, in an analog-to-digital conversion circuit using a sample-and-hold circuit, various characteristics such as linearity are deteriorated.

In the conventional sample and hold circuit, in order to reduce the influence of clock feedthrough, the transistor size of the sample switch is reduced or the capacitance of the hold capacitor is reduced to such an extent that the shift of the hold voltage due to clock feedthrough does not cause a problem. The ratio between the capacitance of the hold capacitor and the parasitic capacitance of the transistor is increased. In addition, a method of using a dummy transistor, a dummy capacitor, or the like to cancel the influence of clock feedthrough is widely used.

[0006] For example, Japanese Patent Application Laid-Open No.
Japanese Patent No. 6935 discloses that a capacitor for increasing the capacitance is provided between the analog output voltage and the ground via a switch for increasing the capacitance, and the switch for increasing the capacitance is turned on when the sample switch is turned off. A sample-and-hold circuit has been proposed in which the effect of clock feedthrough is reduced by combining a capacitor with a hold capacitor and increasing the capacitance value.

However, all of these methods involve a significant increase in the layout area, so that a circuit using a lot of sample and hold circuits has a problem that the chip cost is significantly increased. Also, the on-resistance value R of the transistor of the sample switch and the capacitance value C of the hold capacitor
And the time constant CR becomes large, so that high-speed operation cannot be performed, and it is difficult to widen the operating frequency band of the sample-and-hold circuit.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a sample and hold circuit which solves the above-mentioned problems of the prior art and reduces the influence of clock feedthrough and operates over a wide band. is there.

[0009]

In order to achieve the above object, the present invention provides a sample switch for sampling an analog input voltage, holding the analog input voltage sampled by the sample switch, and outputting the analog output voltage to an analog output. A hold capacitor that outputs a voltage, a comparator that compares the analog output voltage with a reference voltage, and a comparator that compares the analog output voltage with a reference voltage when the analog output voltage is smaller than the reference voltage. An auxiliary circuit that assists in charging the charge, and that assists in discharging the charge from the hold capacitor when the analog output voltage is greater than the reference voltage. Is what you do.

Here, the reference voltage is the analog input voltage, and the comparator preferably compares the analog output voltage with the analog input voltage.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a sample and hold circuit according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings. FIG. 1 is a circuit diagram of a sample and hold circuit according to an embodiment of the present invention. The sample-and-hold circuit 10 in the illustrated example is different from a conventionally known sample-and-hold circuit including a sample switch 12 and a hold capacitor 14 in addition to two comparators 16 and 1.
8 and an auxiliary circuit 20.

First, the sample switch 12 samples the analog input voltage AIN. In the case of the illustrated example, the sample switch 12 is a P-type MOS transistor (hereinafter referred to as PMOS).
22 and an N-type MOS transistor (hereinafter, referred to as NMOS) 24. These PMOS 22 and NM
The both ends of the OS 24 are connected in parallel between the analog input voltage AIN and the analog output voltage VOUT, and the control signal S0N and the control signal S0 are input to the gate thereof.

The control signals S0 and S0N are signals for controlling ON / OFF of the sample switch 12, and the control signal S0N is an inverted signal of the control signal S0. PMOS 22 and NMOS constituting sample switch 12
24, when the control signal S0 is at a high level, that is, when the control signal S0N is at a low level, the analog input voltage AIN and the analog output voltage VOUT are conducted, and conversely, the control signal is at a low level and the control signal S0N Turns off when is at high level.

The hold capacitor 14 holds the analog input voltage AIN sampled by the sample switch 12 and outputs it as an analog output voltage VOUT. In the illustrated example, both ends are connected to the analog output voltage VOUT and the ground. It is connected to the voltage VSS. Needless to say, the present invention is applicable to any conventionally known sample and hold circuit including a sample switch and a hold capacitor.

Subsequently, the comparators 16 and 18 compare the analog output voltage VOUT with the analog input voltage AIN serving as a reference voltage. In the illustrated example, the comparator 16 outputs a high level only when the analog input voltage AIN is higher than the analog output voltage VOUT, whereas the comparator 18 outputs the analog input voltage AIN more than the analog output voltage VOUT. High level is output only when is lower.

In the circuit example shown in FIG. 1, two comparators 16 and 18 are used. However, as shown in FIG. 2, only one comparator may be used. The difference between the sample and hold circuit 34 in FIG. 2 and the sample and hold circuit 10 in FIG. 1 is that the same function is realized by using an inverter 36 that inverts and outputs the output signal of the comparator 16 instead of the comparator 18. It is. The same components other than the above are denoted by the same reference numerals.

In the example shown in FIG. 1, the analog input voltage AIN is used as an example of the reference voltage to be compared with the analog output signal VOUT. However, the analog input voltage AIN does not always need to be used as the reference voltage. That is, a reference voltage having an arbitrary potential is set, the analog output voltage VOUT is compared with the reference voltage, and the potential of the hold capacitor 14 is charged and discharged to the level of the reference voltage to adjust the analog output voltage VOUT. Is also good.

Finally, the auxiliary circuit 20 sets the analog output voltage VOUT to the reference voltage in accordance with the comparison result from the comparators 16 and 18 with respect to the charging and discharging of the hold capacitor 14 via the sample switch 12. In the case of the example, when the voltage is smaller than the analog input voltage AIN,
Assists in charging the hold capacitor 14 with charge,
When the analog output voltage VOUT is higher than the analog input voltage AIN, it assists in discharging the charge from the hold capacitor 14.

That is, the auxiliary circuit 20 operates when the sample switch 12 is on, that is, when the control signal S0N is at a low level and the control signal S0 is at a high level, and assists charging and discharging of the hold capacitor 14. . In the case of the present embodiment, the auxiliary circuit 20 includes the NAND gate 26
And a P-type MOS transistor (hereinafter referred to as PMOS)
28, an AND gate 30, and an N-type MOS transistor (hereinafter, referred to as NMOS) 32.

Here, NAND gate 26 and AND gate
The control signal S1 is input to the first input terminal of the gate 30 and the output signals from the comparators 16 and 18 are input to the second input terminal. The output signals are input to the gates of the PMOS 28 and the NMOS 32, respectively. Has been entered. Also, the PMOS 28 and the NMO
The source of S32 is connected to the power supply voltage VDD and the ground voltage VSS, respectively, and its drain is both connected to the analog output voltage VOUT.

The control signal S1 is a signal for controlling the operation of the auxiliary circuit 20, and the auxiliary circuit 20 becomes operable when the control signal S1 is at a high level.
On the other hand, the auxiliary circuit 20 stops when the control signal S1 is at the low level, that is, the output signal of the NAND gate 26 is at the high level, the output signal of the AND gate 30 is at the low level, and both the PMOS 28 and the NMOS 32 are turned off. And is electrically disconnected from the analog output voltage VOUT.

Note that the specific circuit configuration of the auxiliary circuit 20 is not limited to the illustrated example, but is another circuit configuration that realizes the same function by changing the circuit according to the polarity of each signal. You may. Although the circuit examples shown in FIGS. 1 and 2 apply the present invention to a sample and hold circuit composed of only the sample switch 12 and the hold capacitor 14, the present invention is configured using, for example, an amplifier. It is also applicable to a circuit that charges and discharges a capacitance such as a sample and hold circuit.

The operation of the sample and hold circuit of the present invention when the analog input voltage AIN changes from zero level to full level will be described below with reference to the timing chart shown in FIG.

As shown in the timing chart of FIG.
In an initial state, the control signal S0 is at a low level, the control signal S0N is at a high level, and the control signal S1 is at a low level. That is, the sample switch 12 is off, and the auxiliary circuit 20 is also stopped. The analog input voltage AIN is at a zero level, and the analog output voltage VOUT is also at a zero level substantially equal to the analog input voltage AIN. That is, the output signals of the comparators 16 and 18 are both at the low level.

First, the analog input voltage AIN changes from zero level to full level. At this time, since the sample switch 12 is off, the analog output voltage VOUT maintains the state of zero level. Also, comparator 1
6 and 18 always operate, the analog input voltage A
With the change of IN, the output signal of the comparator 16 changes from a low level to a high level. The comparator 1
The output signal of No. 8 maintains the low level.

Subsequently, the control signal S0 goes high, the control signal S0N goes low, and the control signal S1 goes high. As a result, the sample switch 12 is turned on and the auxiliary circuit 20 is also operable. That is, the full level of the analog input voltage AIN is charged to the hold capacitor 14 via the sample switch 12 and is output as the analog output voltage VOUT.

As described above, the output signal of the comparator 16 is at the high level. On the other hand, the output signal of the comparator 18 maintains the low level. When the control signal S1 goes high, the NA of the auxiliary circuit 20
The output signals of the ND gate 26 and the AND gate 30 are at low level, so that the PMOS 28 is on and the NMOS 32
Is off, and the hold capacitor 14 is connected to the PMOS2
8 to a full level at high speed.

At this time, when the voltage of the analog output voltage VOUT becomes higher than the voltage level of the analog input voltage AIN due to the charging of the hold capacitor 14 by the PMOS 28, the output signal of the comparator 16 changes to low level and the PMOS 28 is turned off. At the same time, the output signal of the comparator 18 becomes high level, and the NMOS 32 is turned on to start discharging. Further, when the potential of the hold capacitor becomes lower than the voltage level of the analog input voltage AIN, the PMOS 28 is turned on, as in the initial charging.
The NMOS 32 turns off and starts charging. Thus, when the auxiliary circuit operates, the potential of the hold capacitor 14 is rapidly set to a value close to the analog input voltage AIN,
Thereafter, a minute vibration is repeated near the analog input voltage AIN.

Subsequently, the control signal S1 goes low after a predetermined period of time. This control signal S1 corresponds to the control signal S
It operates in synchronization with 0, S0N. In the case of the present embodiment, the control signal S1 rises in synchronization with the rise of the control signal S0, ie, in synchronization with the fall of the control signal S0N, and after a predetermined time required for charging and discharging the hold capacitor 14, but Before the falling of the control signal S0,
That is, it falls before the rise of the control signal S0N.

When the control signal S1 goes low, PM
Both the OS 28 and the NMOS 32 are turned off, but since the sample switch 12 is turned on, the analog input voltage AIN and the analog output voltage VO generated when the auxiliary circuit operates.
Minute error from UT, PMOS 28 or NMOS 32
The error due to the influence of clock feedthrough that occurs when the analog output voltage is turned off is corrected.
UT is set to a full level substantially equal to the analog input voltage AIN.

Thereafter, the control signal S0 goes low and the control signal S0N goes high. This allows
The sample switch 12 turns off. At this time, the PMOS 22 and the NMOS 24 forming the sample switch 12
Of the PMOS 22
And the parasitic capacitance of the NMOS 24 is the hold capacitor 1
4 and the analog output voltage VOUT fluctuates.

In the conventional sample and hold circuit having only the sample switch 12 and the hold capacitor 14, in order to reduce the influence of clock feedthrough,
The transistor size of the sample switch cannot be increased. Therefore, as shown in the timing chart of FIG. 4, the hold capacitor is slowly charged only through the sample switch. Therefore, the time required for sampling is long, and it is difficult to operate at high speed.

On the other hand, in the present invention, these PMOs
Even if the transistor sizes of S22 and NMOS 24 are reduced, PMOS 28
And the hold capacitor 14 can be charged and discharged at high speed via the NMOS 32. Therefore, the PMOS 22 and the NMOS 24 forming the sample switch 12
, The influence of clock feedthrough can be suppressed to a negligible level.

In the above embodiment, the analog input voltage AIN changes from zero level to full level, and the hold capacitor 14 is charged to the full level at high speed via the PMOS 28 of the auxiliary circuit 20. On the contrary, when the analog input voltage AIN changes from the full level to the zero level, the same operation is performed, and the hold capacitor 14 is connected to the NMOS 32 of the auxiliary circuit 20.
Is rapidly discharged to zero level.

The sample and hold circuit 10 of the present invention is basically as described above. As described above, the sample and hold circuit of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. is there.

[0036]

As described above in detail, the sample and hold circuit of the present invention compares the analog output voltage with the reference voltage, and charges the hold capacitor when the analog output voltage is smaller than the reference voltage. To help
If the analog output voltage is higher than the reference voltage, it assists in discharging the charge from the hold capacitor. According to the sample and hold circuit of the present invention, the hold circuit can be charged and discharged at a high speed by the auxiliary circuit. Therefore, the sample and hold circuit can be suitably used especially for a sample and hold circuit using a large-capacity hold capacitor. Can be reduced to such an extent that the influence of clock feedthrough can be ignored, the parasitic capacitance of the analog input voltage node does not increase, and the sample-and-hold circuit can operate over a wide band.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a sample hold circuit of the present invention.

FIG. 2 is a configuration circuit diagram of another embodiment of the sample and hold circuit of the present invention.

FIG. 3 is a timing chart of an example showing an operation of the sample and hold circuit of the present invention.

FIG. 4 is a timing chart showing an example of the operation of a conventional sample and hold circuit.

[Explanation of symbols]

 10, 34 Sample hold circuit 12 Sample switch 14 Hold capacitor 16, 18 Comparator 20 Auxiliary circuit 22, 28 P-type MOS transistor 24, 32 N-type MOS transistor 26 NAND gate 30 AND gate 36 Inverter

Claims (2)

[Claims] A sample switch for sampling an analog input voltage; a hold capacitor for holding the analog input voltage sampled by the sample switch and outputting the analog input voltage as an analog output voltage;
A comparator that compares the analog output voltage with a reference voltage, and, according to a comparison result from the comparator, assists in charging the hold capacitor when the analog output voltage is smaller than the reference voltage. And an auxiliary circuit for assisting discharge of the electric charge from the hold capacitor when the analog output voltage is higher than the reference voltage. 2. The sample and hold circuit according to claim 1, wherein the reference voltage is the analog input voltage, and wherein the comparator compares the analog output voltage with the analog input voltage.