JP2000232348A - Sample-and-hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a sample-and-hold circuit which suppresses an increase in chip cost, reduces influence due to clock feed through in a broadband and has a few errors by controlling to change the control voltage of a sample switch stepwise when the sample switch is turned off. SOLUTION: This sample-and-hold circuit 10 has a control circuit 12 controlling the control voltage of a sample switch SW in addition to the sample switch and a hold capacitor CH. The circuit 12 controls so as to change the control voltage stepwise when the switch SW is turned off. Then, the circuit 12 has an inverter 22, a delay circuit 24, an OR gate 26 and an inverter 28 in addition to a control signal generation circuit 18 generating a control signal PG controlling the control voltage of a PMOS 14 and a control signal generation circuit 20 generating a control signal NG controlling the control voltage of an NMOS 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing the influence of clock feedthrough in a sample and hold circuit.

[0002]

2. Description of the Related Art Generally, a sample and hold circuit includes a sample switch for sampling an analog input voltage and a hold capacitor for holding the analog input voltage sampled by the sample switch and outputting the analog input voltage as an analog output voltage. Be composed.
In the sample and hold circuit, by turning on and off the sample switch once, the analog input voltage at the time when the sample switch is turned off is held in the hold capacitor.

A transistor is usually used as a sample switch. Therefore, when the sample switch is turned off, the parasitic capacitance existing between the gate and the source and between the gate and the drain of the transistor is combined with the hold capacitor, and the hold voltage held by the hold capacitor fluctuates. Such a phenomenon that the hold voltage of the hold capacitor fluctuates due to the influence of the parasitic capacitance of the sample switch is called clock feedthrough.

Due to the influence of the clock feedthrough, the error amount of the hold voltage held in the hold capacitor depends on the input level of the analog input voltage.
The analog input voltage tends to decrease as it approaches the intermediate potential between the power supply and the ground, and conversely, tends to increase as it approaches the power supply or the ground. Therefore, for example, in an analog-to-digital conversion circuit using a sample-and-hold circuit, various characteristics such as linearity are deteriorated.

In the conventional sample and hold circuit, in order to reduce the influence of clock feedthrough, the transistor size of the sample switch is reduced or the capacitance of the hold capacitor is reduced to such an extent that the shift of the hold voltage due to clock feedthrough does not cause a problem. The ratio between the capacitance of the hold capacitor and the parasitic capacitance of the transistor is increased. In addition, a method of using a dummy transistor, a dummy capacitor, or the like to cancel the influence of clock feedthrough is widely used.

[0006] For example, Japanese Patent Application Laid-Open No.
Japanese Patent No. 6935 discloses that a capacitor for increasing the capacitance is provided between the analog output voltage and the ground via a switch for increasing the capacitance, and the switch for increasing the capacitance is turned on when the sample switch is turned off. A sample-and-hold circuit has been proposed in which the effect of clock feedthrough is reduced by combining a capacitor with a hold capacitor and increasing the capacitance value.

However, all of these methods involve a significant increase in the layout area, so that a circuit using a lot of sample and hold circuits has a problem that the chip cost is significantly increased. Also, the on-resistance value R of the transistor of the sample switch and the capacitance value C of the hold capacitor
And the time constant CR becomes large, so that high-speed operation cannot be performed, and it is difficult to widen the operating frequency band of the sample-and-hold circuit.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems based on the prior art, and to improve the analog output voltage due to the influence of clock feedthrough while maintaining a wide band characteristic without increasing the chip cost. It is an object of the present invention to provide a sample-and-hold circuit that can reduce the error of (1).

[0009]

In order to achieve the above object, the present invention provides a sample switch for sampling an analog input voltage, holding the analog input voltage sampled by the sample switch, and outputting the analog output voltage to an analog output. The present invention provides a sample and hold circuit comprising: a hold capacitor that outputs a voltage; and a control circuit that controls the control voltage of the sample switch to change stepwise when the sample switch is turned off. .

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a sample and hold circuit according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of a sample and hold circuit according to the present invention. The sample and hold circuit 10 in the illustrated example has a control circuit 12 that controls a control voltage of the sample switch SW in addition to the sample switch SW and the hold capacitor CH.

First, the sample switch SW is for sampling the analog input voltage AIN. In the illustrated example, the sample switch SW is a P-type MOS transistor (hereinafter referred to as PMOS).
14 and an N-type MOS transistor (hereinafter referred to as NMOS) 16. These PMOS 14 and NM
The OS 16 has both ends connected in parallel between the analog input voltage AIN and the analog output voltage SHOUT, and has a gate connected to a control signal PG and a control signal NG described later.
Are respectively input.

The hold capacitor CH holds the analog input voltage AIN sampled by the sample switch SW and outputs this as an analog output voltage SHOUT. In the illustrated example, both ends are connected to the analog output voltage SHOUT and the ground. Connected to VSS. The sample switch SW and the hold capacitor CH are conventionally known, and any of the conventionally known ones can be applied to the present invention.

Subsequently, when the sample switch SW is turned off, the control circuit 12 controls the control voltage so as to change the control voltage in a stepwise manner.
Control signal PG for controlling the control voltage of MOS 14
, A control signal generating circuit 20 for generating a control signal NG for controlling the control voltage of the NMOS 16, an inverter 22, a delay circuit 24,
It has an OR gate 26 and an inverter 28.

In the control circuit 12, first, the control signal generation circuit 18 includes NMOSs N11, N12, N2 and P
MOSP3 is provided. NMOS N11, N12, N2
Are connected in series between the power supply VDD and the ground VSS, and a connection point between the NMOS N12 and the NMOS N2 is used as a control signal PG. The control signal SCLK #, which is the output of the inverter 22, is input to the gates of the NMOSs N11 and N12, and the control signal SCLK is input to the gate of the NMOS N2.
Is entered. The PMOS P3 is connected to the power supply VDD.
And the control signal PG.
The control signal SCLK2 which is the output of the gate 26 is input.

On the other hand, the control signal generation circuit 20
It has PMOSs P1, P21, P22 and NMOS N3. The PMOSs P1, P21, and P22 are connected in series between the power supply VDD and the ground VSS, and a connection point between the PMOS P1 and the PMOS P21 is used as a control signal NG. A control signal SCLK # output from the inverter 22 is input to the gate of the PMOS P1.
The control signal SCLK is input to the gate of P22. The NMOS N3 is connected to the control signal NG and the ground V
SS, and the gate of the inverter 28
Output is input.

The inverter 22 has a control signal SCL.
K has been entered. The delay circuit 24 has a predetermined number of buffers connected in series. The control signal SCLK is input to the first buffer, and the output of the last buffer is input to one input terminal of the OR gate 26. O
The control signal SCLK is also input to the other input terminal of the R gate 26, and its output is input to the gate of the PMOS P3 as described above and also to the inverter 28 as the control signal SCLK2. .

Hereinafter, the operation of the sample and hold circuit of the present invention will be described with reference to the timing chart shown in FIG.

As shown in the timing chart of FIG.
Control signal SCLK is a source signal for generating control signals PG and NG for controlling sample switch SW, and control signal SCLK # is a signal obtained by inverting control signal SCLK by inverter 22. Also, the control signal SCLK2
Is a control signal SCLK delayed by an OR gate 26 and a control signal SC delayed by a predetermined fixed time by a delay circuit 24.
The logical sum with LK is taken, and the fall timing of the control signal SCLK is delayed by a time corresponding to the delay time of the delay circuit 24.

First, when the control signal SCLK changes from the low level to the high level, the control signal SCLK # changes from the high level to the low level, and the control signal SCLK2 changes from the low level to the high level.

In response, the control circuit 12 controls the NMOS N11, N12 and PMO of the control signal generation circuit 18
SP3 turns off and NMOS N2 turns on. Further, the PMOSP1 of the control signal generation circuit 20 turns on, and the PMOSP1
21, P22 and NMOS N3 are turned off. Therefore, the control signal PG is applied to the ground V via the NMOS N2.
It is discharged to the voltage level of SS and the control signal N
G is charged up to the voltage level of the power supply VDD via the PMOS P1. As a result, both the PMOS 14 and the NMOS 16 of the sample switch SW are turned on, and the analog input voltage AIN is changed to the sample switch S.
While being held by the hold capacitor CH via W, it is output as an analog output voltage SHOUT.

Subsequently, when the control signal SCLK changes from a high level to a low level, the control signal SCLK # changes from a low level to a high level. After the time corresponding to the time, it changes from the high level to the low level.

First, at the stage when the control signal SCLK changes from the high level to the low level, the control signal generation circuit 18
NMOSN2 is turned off, and NMOSN11 and N12 are turned on. The PMOSP2 of the control signal generation circuit 20
1, P22 is turned on, and PMOS P1 is turned off. At this time, as shown in the timing chart of FIG. 2, the control signal SCLK2 is still at the high level, and the output of the inverter 28 is also at the low level.
3 and NMOS N3 remain off.

In response, the control signal PG is output from the NMOS
It is charged up through N11 and N12, and the control signal NG is discharged through PMOSs P21 and P22. When the voltage levels of the control signal PG and the control signal NG change, an influence of the clock feedthrough of the PMOS 14 and the NMOS 16 of the sample switch SW occurs in the hold capacitor CH in accordance with the change of the voltage levels. As shown, the voltage level of the analog output voltage SHOUT varies from the voltage level of the analog input voltage AIN.

However, the control signal PG is output from the NMOS N1
1 and N12, only the intermediate potential of the power supply VDD- (the threshold value of the NMOS + α) is charged up due to the influence of the substrate bias effect and the like, and the voltage level of the analog input voltage AIN becomes | Analog input voltage AIN-Voltage level of control signal PG |> PM
When the threshold value of the OS is reached, that is, when the voltage level of the analog input voltage AIN is close to the power supply VDD, the PMOS 14 of the sample switch SW is kept on.

Similarly, the control signal NG is the PMOSP2
1 and P22, the ground VSS + (PMO
The discharge is performed only up to the intermediate potential of (the threshold value of S + α), and the voltage level of the analog input voltage AIN is | │analog input voltage AIN−voltage level of control signal NG│>
When the threshold value of the NMOS is reached, that is, when the voltage level of the analog input voltage AIN is close to the ground VSS, the NMOS 16 of the sample switch SW maintains the ON state.

Therefore, when the voltage level of the analog input voltage AIN is close to the power supply VDD or the ground VSS, the sample switch SW is kept on, and the hold voltage of the hold capacitor CH is changed to the analog voltage after a predetermined time. It returns to the voltage level of the input voltage AIN. In other words, the delay time of the delay circuit 24 is for making a predetermined constant time necessary for the hold voltage of the hold capacitor CH to return to the voltage level of the analog input voltage AIN.

On the other hand, the analog input voltage AIN
Is close to the intermediate potential between the power supply VDD and the ground VSS, the PMOS 14 and NM of the sample switch SW
Since the OS 16 is turned off, the influence of clock feedthrough occurs. However, in this case, the influence of the clock feedthrough is extremely small, and the voltage change amount of the analog output voltage SHOUT can be kept within an allowable range.

Subsequently, as described above, the control signal SCLK
Is changed from the high level to the low level, and after a time corresponding to the delay time of the delay circuit 24, the control signal SCLK
2 changes from high level to low level, and inverter 2
The output 8 changes from low level to high level.

In response, P of control signal generation circuit 18
MOSP3 is turned on, and the control signal PG is
3, the charge is charged up from the intermediate potential to the voltage level of the power supply VDD. Similarly, the NMOS N3 of the control signal generation circuit 20 is also turned on, and the control signal NG is
From the intermediate potential to the voltage level of the ground VSS. Therefore, both the PMOS 14 and the NMOS 16 of the sample switch SW are turned off. At this time, the voltage level of the analog output voltage SHOUT fluctuates from the voltage level of the analog input voltage AIN due to the influence of clock feedthrough.

However, in the sample and hold circuit 10 of the present invention, the control signal PG and the control signal NG are once changed to the intermediate potential between the power supply VDD and the ground VSS, and then changed to the voltage levels of the power supply VDD and the ground VSS. That is, the analog input voltage AI
Even when the voltage level of N is close to the voltage level of the power supply VDD or the ground VSS, since the potential difference between the analog input voltage AIN and the control signal PG and the control signal NG is small, as shown in the timing chart of FIG. The influence of the through is very small, and the voltage change amount of the analog output voltage SHOUT can be kept within an allowable range.

The sample and hold circuit 10 of the present invention is basically as described above. The specific circuit configuration of the control circuit 12 is not limited to the illustrated example, and may be another circuit configuration that realizes the same function. For example, FIG. 3 shows a configuration circuit diagram of another embodiment of the sample and hold circuit of the present invention. This sample hold circuit 3
Reference numeral 0 denotes a configuration in which the same function as that of the sample and hold circuit 10 in FIG. 1 is applied by applying another circuit configuration.

The difference between the sample-and-hold circuit 30 of FIG. 3 and the sample-and-hold circuit 10 of FIG.
1 at one end, not the power supply VDD but the power supply VDD
1 and the PMOS of the control signal generation circuit 18
P3 and the point that the power supply VDD2 is supplied instead of the power supply VDD to the PMOS P1 of the control signal generation circuit 20, and the PMOS P21 and P2 of the control signal generation circuit 20
2 is that a PMOS P2 is used in place of the power supply VDD2 and one end thereof is supplied with a power supply VDD3 instead of the ground VSS. The same components other than the above are denoted by the same reference numerals.

The sample and hold circuit 30 shown in FIG.
In this example, the intermediate potential is directly supplied from the outside instead of generating the intermediate potential by using the substrate bias effect or the like as in the sample and hold circuit 10 of FIG. VDD1> power supply VDD
3> ground VSS. As described above, the circuit configuration of the control circuit 12 may be any circuit configuration that controls the control voltage to change stepwise when the sample switch SW is turned off.

Although the sample and hold circuit of the present invention has been described in detail above, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

[0036]

As described in detail above, the sample and hold circuit of the present invention controls the control voltage of the sample switch so as to change stepwise when the sample switch is turned off. As a result, according to the sample and hold circuit of the present invention, it is possible to obtain a sample and hold circuit with a reduced error in which the influence of clock feedthrough is reduced over a wide band while suppressing an increase in chip cost.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a sample hold circuit of the present invention.

FIG. 2 is a timing chart of an example showing an operation of the sample and hold circuit shown in FIG. 1;

FIG. 3 is a configuration circuit diagram of another embodiment of the sample and hold circuit of the present invention.

[Explanation of symbols]

Reference Signs List 10 sample hold circuit 12 control circuit 14, P1, P2, P21, P22, P3 P-type MOS
Transistor 16, N1, N11, N12, N2, N3 N-type MOS
Transistors 18, 20 Control signal generation circuit 22, 28 Inverter 24 Delay circuit 26 OR gate SW Sample switch CH Hold capacitor AIN Analog input voltage SHOUT Analog output voltage PG, NG Control signal SCLK, SCLK￣, SCLK2 Control signal VDD, VDD1, VDD2 , VDD3 Power VSS Ground

Continued on front page F-term (reference) 5J022 AA01 BA01 CA10 CD04 CF07 CG01 5J055 AX29 BX17 CX24 DX13 DX14 DX22 DX61 DX73 DX83 EY10 EY21 EZ07 EZ12 EZ25 EZ50 GX01 GX04

Claims (1)

[Claims] A sample switch for sampling an analog input voltage; a hold capacitor for holding the analog input voltage sampled by the sample switch and outputting the analog input voltage as an analog output voltage;
A control circuit for controlling the control voltage of the sample switch to change stepwise when the sample switch is turned off.