JP2001134548A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor system which can switch programs to become visible by processors even with the same physical address and then simplify the circuit constitution, lower the cost, and improve software development efficiency. SOLUTION: The multiprocessor system is constituted by connecting CPUs 1 and 2, on-chip ROMs 12 and 13 stored with programs, and an external ROM 14 and an external RAM 15 to a common system bus 3 and comprises an arbiter 6 which determines a CPU allowed to occupy the bus according to specific bus priority in response to bus request signals REQ4 and REQ5 from the CPUs 1 and 2 and outputs bus permission signals GNT7 and GNT8, a decoder 10 which outputs a select signal CSa for selecting memories corresponding to the CPUs 1 and 2 according to the bus permission signals GNT7 and GNT8 and the address signal A31-A0 of the system bus, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multiprocessor system in which a plurality of processors are connected to a common system bus.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional multiprocessor system. Two CPUs (Centr
al Processing Units) 51 and 52 are connected to a single system bus 53 and share the same physical address. C
An arbiter 56 for arbitrating bus access competition between the PUs 51 and 52 is provided.

[0003] Peripheral circuits such as a decoder 60, on-chip ROMs (Read Only Memory) 62 and 63, and a memory interface 61 are connected to a system bus 53, and an external bus 66 is connected via the memory interface 61. An external ROM 64 and an external RAM (Ran
A peripheral circuit such as a dom access memory (65) is connected.

[0004] The decoder 60 outputs a select signal CSa for selecting a peripheral circuit assigned to the address space of the system bus 53. The memory interface 61 also has an address decoder function, and a select signal for selecting a peripheral circuit assigned to the address space of the system bus 53.
Outputs CSb.

[0005] The operation of the arbiter 56 will be described. C
Before any of the PUs 51 and 52 starts bus access, the bus request signals 54 and 55 are output to the arbiter 56. Then, the arbiter 56 determines the CPU that permits the bus access according to the predetermined bus priority, and outputs the bus permission signals 57 and 58 to the CPU. The CPU that has received the bus permission signal starts accessing the system bus 53.
The CPU that has not received the bus permission signal is the system bus 53
Suspends access to and waits for a bus permission signal.

In this way, the CPUs 51 and 52 can share memories such as the on-chip ROMs 62 and 63, the external ROM 64, and the external RAM 65 while avoiding contention for bus access.

[0007]

Generally, a CPU is often started from the same physical address at the time of reset or occurrence of an interrupt. When a plurality of CPUs are connected to a single bus, it is desired to start different programs depending on the CPUs when the CPUs are reset or when an interrupt occurs.

However, in the circuit configuration shown in FIG. 5, since the two CPUs 51 and 52 have a common physical address, it is impossible to switch the startup program at the time of reset or at the time of occurrence of an interrupt for each CPU.

A related prior art is disclosed in Japanese Patent Laid-Open No. 5-197.
No. 617 describes a method of allocating an upper address of a bus for each processor and accessing a shared memory via a buffer. However, there is no concept of arbitration of the shared bus, and the physical address is fixed for each processor, so that the degree of freedom in program design is limited.

By adopting the shared bus system, when developing a system-on-a-chip or the like, the number of pins can be reduced and the chip area can be reduced by using a single bus, so that cost and power consumption can be reduced. Therefore, there is a need for an efficient method of allocating shared memory while performing efficient bus arbitration.

Further, by using a single bus, when a plurality of processors access the same physical address, it is necessary to switch a visible program for each processor. Further, in order to eliminate the interaction at the time of program development and to increase the independence between the processors, a function such as a write restriction to the shared memory is required, thereby improving the efficiency of program development.

An object of the present invention is to switch a program which can be visualized for each processor even with the same physical address, thereby simplifying a circuit configuration, reducing costs and improving software development efficiency. It is to provide a processor system.

[0013]

SUMMARY OF THE INVENTION The present invention is directed to a multiprocessor system in which a plurality of processors and a plurality of memories for storing programs are connected to a common system bus, in accordance with a bus request signal from each processor. A bus arbiter that outputs a bus permission signal according to a bus priority according to a bus priority and a select signal that selects a memory corresponding to each processor based on the bus permission signal and a system bus address signal are stored in each memory. And a decoder for outputting to a multiprocessor system.

According to the present invention, the processor that occupies the system bus can be identified by checking the bus grant signal from the bus arbiter by the decoder. Therefore, even if the processors share the same physical address, a different program can be started for each processor by switching the memory corresponding to the processor that is occupying the bus.

Further, the present invention is characterized by including a timing conversion circuit interposed between the bus arbiter and the decoder, for converting the timing of the bus permission signal from the bus arbiter and outputting the converted signal to the decoder.

According to the present invention, the bus arbiter and the system bus have a high degree of circuit configuration independence. Generally, the timing of the bus enable signal is not synchronized with the clock of the system bus, so that the signal processing in the decoder is complicated. However, by providing the timing conversion circuit, the signal relating to bus arbitration and the system bus can be processed at the same timing, so that signal processing in the decoder can be simplified.

Further, according to the present invention, the memory has a first physical address space for permitting read access from all processors, and a second physical address space for permitting write access by a specific processor and prohibiting write access by other processors. And an address space.

According to the present invention, a memory address space in which write access is permitted or prohibited is allocated to each processor, so that a memory address space that can be used exclusively by a specific processor can be secured. Can be eliminated, and the efficiency of program development is improved.

[0019]

FIG. 1 is a block diagram showing an embodiment of the present invention. The two CPUs 1 and 2 are connected to a single system bus 3 and share the same physical address. An arbiter 6 for arbitrating bus access contention between the CPUs 1 and 2 is provided.

Peripheral circuits such as a decoder 10, on-chip ROMs 12, 13 and a memory interface 11 are connected to the system bus 3.
1, an external bus 16 is connected to the external bus 16, and peripheral circuits such as an external ROM 14 and an external RAM 15 are connected to the external bus 16.

The decoder 10 outputs a select signal CSa for selecting a peripheral circuit assigned to the address space of the system bus 3. The memory interface 11 also has an address decoder function, and a select signal CSb for selecting a peripheral circuit assigned to the address space of the system bus 3.
Is output. A timing conversion circuit 9 intervenes between the arbiter 6 and the decoder 10.

FIG. 2 is a timing chart showing the operation. First, when the CPU 1 needs access to the system bus 3, the CPU 1 makes the bus request signal REQ 4 of the CPU 1 active (high level) and outputs it to the arbiter 6. on the other hand,
When the CPU 2 needs access to the system bus 3, it makes the bus request signal REQ 5 of the CPU 2 active (high level) and outputs it to the arbiter 6.

The arbiter 6 determines a processor that permits occupation of the bus according to a predetermined bus priority. C
When permitting the PU1 to occupy the bus, the bus permit signal GNT7 is activated and output to the CPU1, and the bus permit signal GNT8 is deactivated (low level).
Output to On the other hand, when permitting the CPU 2 to occupy the bus, the bus permission signal GNT8 is activated and output to the CPU 2, and the bus permission signal GNT7 is deactivated and output to the CPU 1.

If both the CPUs 1 and 2 are processors having an instruction cache memory therein, the instructions stored in the instruction cache memory can be read.
When a so-called cache hit occurs, there is no need to access the bus, so that the instruction can be executed without activating the bus permission signal. Therefore, if the cache hit continues, both CPUs 1 and 2 can operate simultaneously. However, when the instruction to be executed is not stored in the instruction cache memory and a so-called cache miss occurs, a bus access is required. The bus request signal is activated and the arbiter 6 waits for the bus occupation permission.
Reads instructions stored in peripheral memory.

When the bus permission signal GNT8 to the CPU 2 is active and the CPU 2 is performing the bus access,
CPU1 mishits the cache and generates a bus request signal.
When REQ4 is activated, the arbiter 6 determines the bus priority of the CPUs 1 and 2 when the current bus access ends. For example, when the bus priority of the CPU 1 is higher, the exclusive use of the bus is transferred to the CPU 1, the bus permission signal GNT7 to the CPU 1 is activated, the bus permission signal GNT8 to the CPU 2 is deactivated, and the bus access of the CPU 2 is interrupted. Let it. Conversely, when the bus priority of the CPU 2 is higher, the bus permission signal GNT7 to the CPU 1 is kept inactive, and the bus permission signal GNT8 to the CPU 2 is kept active, and the CPU 2 continues the bus access.

Referring to FIG. 2, the system bus 3 is configured as a synchronous bus operating in synchronization with a clock CLK. At time T1, which is the rising edge of the clock CLK, the CPU 1 sets the bus request signal REQ4 to active (high level) in order to read an instruction stored in the peripheral memory. At this time, the bus request signal REQ5 of the CPU 2 is inactive (low level). The arbiter 6 activates the bus permission signal GNT7 to the CPU 1 based on the state of the bus request signal REQ4.

Next, at time T2 when the clock CLK falls.
Then, the CPU 1, knowing that the bus occupation has been permitted, starts the bus access at time T3, which is the rising of the next clock CLK, and drives the address signals A31-A0 of the system bus 3.

Here, the bus permission signals GNT7 and GNT8 are input to the timing conversion circuit 9.

FIG. 3 is a circuit diagram showing an example of the timing conversion circuit 9. The timing conversion circuit 9 is composed of a D-type flip-flop. The bus permission signal GNT7 is input to the D terminal, and the bus permission signal GNT8 is not used. Here, two CPUs are used as a multiprocessor system.
This is because the bus conflict can be prevented if only one bus permission signal is monitored since the buses 1 and 2 are used. In a configuration using three or more processors, each bus permission signal is used.

The clock CLK of the system bus 3 is input to a clock terminal of a D-type flip-flop, and a bus enable signal
GNT7 is latched at the rising edge of the clock CLK and output from the Q terminal as an address signal A32. At time T3 in FIG. 2, the active bus permission signal GNT7 is latched,
Set the address signal A32 to high level. Thus, the bus permission signal GNT7 is the address signal A3 synchronized with the clock CLK.
2 so that the decoder 10 outputs the address signal A3
1-A0 and the address signal A32 can be processed at the same timing, and the circuit configuration of the decoder 10 can be simplified.

At time T4, when the CPU 2 attempts to read an instruction stored in the peripheral memory, the bus request signal REQ5 is activated before starting the bus access. Here, assuming that the bus priority is higher in the CPU 2 than in the CPU 1, the arbiter 6 activates the bus permission signal GNT8 to give the right to use the bus to the CPU 2, and further deactivates the bus permission signal GNT7 to activate the bus of the CPU 1. Prohibit use.

At time T5, which is the falling edge of the clock CLK, the CPU 2 knows that the bus occupation has been permitted and starts bus access from time T6, which is the rising edge of the next clock CLK, and the address signal of the system bus 3 Drive A31-A0. The timing conversion circuit 9 latches the inactive state of the bus permission signal GNT7 at time T6, and outputs the address signal A32
To low level.

Returning to FIG. 1, the address signals A31-A0 of the system bus 3 and the address signals of the timing conversion circuit 9
When A32 is input to the decoder 10, the decoder 10 outputs a select signal CSa in accordance with an address map differently assigned to each processor.

FIG. 4 is an explanatory diagram showing an example of the address map. The address map of the CPU 1 has the address AD0
From on to the address AD1 before the on-chip ROM 12,
External ROM from address AD2 to address AD3
14. Addresses AD4 to AD7 are allocated to the external RAM 15.

The address map of the CPU 2 has an address AD
On-chip ROM 1 from 0 to just before address AD1
3. External R from address AD2 to address AD3
The OM 14 and the addresses from the address AD4 to the address AD7 are allocated to the external RAM 15.

Accordingly, the CPU 1 determines that the address AD0
When the access to an address before AD1 is started, the decoder 10 activates one of the select signals CSa to select the on-chip ROM 12. On the other hand, C
When the PU2 starts accessing an address between the addresses AD0 and AD1, the decoder 10 activates one of the select signals to select the on-chip ROM 13.

Thus, even if the physical address spaces of the CPUs 1 and 2 are the same, the address space from the address AD0 to just before the address AD1 is stored in one of the on-chip ROMs 12 and 13 according to the CPU having the bus use right. Switch.

Normally, the CPU often starts up from the same physical address at the time of reset or occurrence of an interrupt. When a plurality of CPUs are connected to a single bus,
At the time of reset or interrupt occurrence, there are times when it is desired to start a different program depending on the CPU.

In this embodiment, by setting a start address at the time of reset or a start address at the time of occurrence of an interrupt in the address space from the address AD0 to a position immediately before the address AD1, the on-chip R is set according to the CPU to be started.
Either of the OMs 12 and 13 can be selected. Therefore, the start program from each start address is made different for each of the on-chip ROMs 12 and 13 so that C
Different programs can be started by PU.

The memory interface 11 bidirectionally connects the system bus 3 and the external bus 16 via a buffer or the like, and selects based on a select signal CSa from the decoder 10 and an address signal A32 from the timing conversion circuit 9. The signal CSb is supplied to the external ROM 14, the external RAM
15 is output.

Referring to the address map of FIG. 4, the external RAM 15 is allocated from the address AD4 to a position immediately before the address AD7, and has the same address space as viewed from the CPUs 1 and 2. In the address map of the CPU 1, the address space from the address AD4 to the address AD5 and the address space from the address AD6 to the address AD7 are located in a readable / writable area. The memory interface 11 has a memory protect function so that the address space is a readable / writable area. Regarding the address map of the CPU 2, the address space from the address AD5 to a position before the address AD6 and the address space from the address AD6 to a position before the address AD7 are stored in a readable / writable area.
The memory interface 11 has a memory protect function so that the address space from 4 to just before the address AD5 is a readable / writable area.

Therefore, from address AD4 to address AD
The address space before the address 5 is inhibited from being written by the CPU 2, the address space from the address AD5 to the address before the address AD6 is inhibited from being written by the CPU 1, and the address space from the address AD6 to the address before the address AD7 is the address space of both CPUs 1. 2 becomes freely accessible.

As described above, by securing a plurality of physical address spaces having different access rights for each CPU,
An address space that can be used exclusively by a specific CPU can be secured. For this reason, it is possible to eliminate the interaction at the time of program development such that the operation of the CPU 2 is affected by the failure of the program of the CPU 1, and the efficiency of the program development is improved.

[0044]

As described above, according to the present invention, the processor which occupies the system bus can be identified by the decoder checking the bus grant signal from the bus arbiter. Therefore, even if the processors share the same physical address, a different program can be started for each processor by switching the memory corresponding to the processor that is occupying the bus.

Further, by providing a timing conversion circuit for converting the timing of the bus permission signal, a signal relating to bus arbitration and a system bus can be processed at the same timing, so that signal processing in the decoder can be simplified.

Further, by allocating a memory address space in which write access is permitted or prohibited for each processor, a memory address space that can be used exclusively by a specific processor can be secured, so that interaction during program development can be eliminated. The efficiency of program development is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation.

FIG. 3 is a circuit diagram illustrating an example of a timing conversion circuit 9;

FIG. 4 is an explanatory diagram showing an example of an address map.

FIG. 5 is a block diagram illustrating an example of a conventional multiprocessor system.

[Explanation of symbols]

 1, 2 CPU 3 System bus 6 Arbiter 9 Timing conversion circuit 10 Decoder 11 Memory interface 12, 13 On-chip ROM 14 External ROM 15 External RAM 16 External bus

Claims (3)

[Claims] In a multiprocessor system in which a plurality of processors and a plurality of memories for storing programs are connected to a common system bus, exclusive use of a bus is permitted according to a predetermined bus priority in response to a bus request signal from each processor. Determine which processor to use,
A multiprocessor comprising: a bus arbiter that outputs a bus permission signal; and a decoder that outputs a select signal for selecting a memory corresponding to each processor to each memory based on the bus permission signal and an address signal of a system bus. system. 2. The multiprocessor system according to claim 1, further comprising a timing conversion circuit interposed between the bus arbiter and the decoder, for converting a timing of a bus permission signal from the bus arbiter and outputting the converted signal to the decoder. 3. The memory has a first physical address space for permitting read access from all processors, a second physical address space for permitting write access by a specific processor, and prohibiting write access by other processors. The multiprocessor system according to claim 1, further comprising: