JP2001101024A - Tester for integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently execute a test instruction to be executed by a microprocessor in a tester for integrated circuit using a microprocessor. SOLUTION: A test circuit 13 is integrated in an integrated circuit, and a test instruction 4 stored in an inside memory 11 from an outside data bus 5 by the test circuit 13 is executed by a microprocessor 15 so that a test close to a real operation can be executed. Moreover, expected values are compared inside according to the test instruction 4 so that the compared result of the expected values can be stored in the inside memory, and outputted to the outside part. Thus, efficient test can easily and quickly be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device for an integrated circuit.

[0002]

2. Description of the Related Art Integrated circuits are mass-produced on a single silicon wafer by using photographic technology. However, if a silicon wafer has a structural defect, normal operation of the integrated circuit cannot be expected. , It becomes defective. Due to this problem in the manufacture of semiconductor integrated circuits, it is unavoidable that defective products will be included at a certain probability, and it is unavoidable to inspect these defective products before shipment and sort out defective products. The purpose of the test.

Generally, a test pattern is applied to an input terminal of an integrated circuit so that a faulty part can be determined, and an output pattern appearing at an output terminal is observed and compared with an expected value of the output pattern. A faulty part in the integrated circuit is determined, and a defective product is selected. However, in order to test all faulty parts of the integrated circuit, a very large number of test patterns are required, and the test time is enormous. In order to solve this, there is an integrated circuit test device in which a mechanism for facilitating the test is built in the integrated circuit in advance, and a microprocessor test instruction is input from the outside using an input circuit, and the microprocessor uses the test circuit. There is a test device that performs a test by executing. This test apparatus will be described with reference to FIG.

In FIG. 9, reference numeral 91 denotes an internal bus.
2 is a microprocessor connected to the internal bus 91, 93 is a peripheral circuit connected to the internal bus 91,
Reference numeral 94 denotes an input / output circuit which is connected to the internal bus 91 and performs input / output with the outside. Reference numeral 95 denotes a test instruction which is input from the outside using the input / output circuit 94 and executed by the microprocessor 92.

The operation of the conventional integrated circuit test apparatus configured as described above will be described below.
First, a test instruction 95 for testing the microprocessor 92 and the peripheral circuit 93 is created. Next, the first test instruction 95 is input using the input / output circuit 94 and the internal bus 9
1 and executed by the microprocessor 92, and outputs the result of executing the test instruction 95 to the outside via the internal bus 91 using the input / output circuit 94. Next, the second test instruction 95 is input and executed in the same manner until all the test instructions are executed. Thus, the microprocessor 92 and the peripheral circuit 93 can be tested by the test instruction 95 from the outside, and the test result can be output to the outside using the input / output circuit 94.

[0006]

However, in the above conventional configuration, the test instructions are read out one by one from the outside and executed, so that the test instructions are executed in a different manner from the operation executed on the actual application. The problem is that the test time is long because the test instruction is read from the outside each time a single test instruction is executed, and complicated test operations such as conditional branching are performed because the test instructions are executed sequentially from top to bottom. There is a problem that it is difficult to perform the test instruction and a problem that the test instruction creation efficiency is low because the test instruction is described by binary data of 0 and 1.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and allows a complicated test operation such as conditional branching to be performed in a state where a test of a peripheral circuit is close to an actual operation. It is intended to provide a test device.

[0008]

In order to solve the above-mentioned problems, a test apparatus for an integrated circuit according to the present invention is connected to an internal data bus, and controls an external bus I / F to connect a microprocessor from the external data bus. And a test circuit for storing a test instruction executed in the internal memory in the internal memory.

According to the above configuration, the test instruction can be stored in the internal memory from the external data bus, and the test instruction stored in the internal memory can be executed by the microprocessor.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. The present invention is not limited to this embodiment at all, and can be implemented in various modes without departing from the gist.

(Embodiment) FIG. 1 is a block diagram showing an example of a test apparatus according to an embodiment of the present invention, wherein 1 is a reset circuit for resetting an integrated circuit to an initial state, and 2 is a reset circuit. A reset signal for triggering the reset circuit 1 from outside, 3 is a test instruction written in C language and assembler, 4 is a test instruction compiled from the test instruction 3, and 5 is an external input for inputting the test instruction 4. A data bus 6 is a read signal of the test instruction 4, 7 is a write signal to the outside, 8
Is an external bus that interfaces between the external bus and the internal bus
9 is an internal address bus; 10 is an internal data bus; 11 is an internal memory for storing the test instruction 4 and the test result; 12 is an arbiter for arbitrating the internal bus; Is a test circuit for performing an operation of storing the test instruction 4 in the internal memory 11 in the test mode, 14 is a test control signal for controlling the test circuit 13, and 15 is a test control signal for storing the test instruction 4 stored in the internal memory 11. Reference numeral 16 denotes a microprocessor to be executed, and a peripheral circuit 16 is tested by the test instruction 4.

An operation example of the test apparatus for an integrated circuit configured as described above will be described with reference to FIGS.

FIG. 2 is a flowchart showing an operation example of the test apparatus for an integrated circuit.

First, as a step 1, a test instruction 4 is created (21). Next, as step 2, test instruction 4
Is stored in the internal memory 11 from the external data bus 5 via the external bus I / F 8 (22). Further, as step 3, the test instruction 4 stored in the internal memory 11 is executed by the microprocessor 15, and the test result is stored in the internal memory 1.
1 (23). Finally, as a step 4, the test result stored in the internal memory 11 is output to the external data bus 5 via the external bus I / F 8 (24).

FIG. 3 is a flowchart showing an example of step 1. First, a test instruction 3 is created using C language or assembler (31). FIG. 4 is a diagram showing an example of a test instruction. In the main function, data is stored in the address Addr.
Reads the Write function that writes Data and the data at address Addr, compares it with the expected value expectedData, and sets the value 0 if the expected value matches and the value 1 if the expected value does not match ResultMemAddr
The data is written to the register of the peripheral circuit 16 by using the Read function for sequentially writing the test result from the address of the internal memory 11 specified by the above, the expected value is compared, and the expected value comparison result is written to the internal memory 11. The test instruction 3 ends with a TestEnd function that sets a test end flag.

The test instruction 3 as described above is created, and then the test instruction 3 is converted into the binary data test instruction 4 by using a compiler of the target microprocessor 15 (32).

FIG. 5 is a flowchart showing an example of step 2. First, the reset signal 2 is applied to the reset signal 2 by setting the test control signal 14 to the Hi state and keeping the Hi state. Operate and start up the integrated circuit in the test mode. When you start up in test mode,
The external bus I / F 8, the internal memory 11, the arbiter 12, the test circuit 13, the microprocessor 15, and the peripheral circuit 16 are initialized (41). Next, the bus arbiter 12 gives the bus right to the test circuit 13, and the test circuit 13 becomes a bus master (42). The test circuit 13 controls the external bus I / F 8 to set the read signal to Hi (43). When the read signal 6 is Hi, the data of the test instruction 4 is input to the external data bus 5 (44). The test circuit 13 controls the external bus I / F 8 to output the data on the external data bus 5 to the internal data bus 10, and the read signal 6
During Hi, the address signal of the internal memory 11, which is the storage location, is output to the internal data bus 10, stored in the internal memory 11, and the read signal 6 is set to Lo (45). Here, instead of directly storing the test instruction 4 in the internal memory 11, a register is provided in the test circuit 13, the test instruction 4 is once stored in the register of the test circuit 13, and then written in the internal memory 11. Has the same effect.

If it is not the last test instruction 4, the address of the internal memory 11 where the test instruction 4 is stored is incremented by one. Similarly, the test instruction 4 is stored in the internal memory 11, and the last test instruction 4 is stored in the internal memory 11. 11 until it is stored in the storage unit 11 (46, 47). When the storage in the internal memory 11 is completed, the test circuit 11 relinquishes the bus right (48).

FIG. 6 is a flow chart showing an example of step 3 in which the bus master is changed from the test circuit 13 to the microprocessor 15 by the arbiter 12 (5).
1). The microprocessor 15 executes the test instruction 4 stored in the internal memory 11 (52). In this case, in the case of the test instruction 4 for writing a test result (for example, the Read instruction in FIG. 4) (53), it is checked whether or not there is sufficient write space in the internal memory 11 (54). The test result is written to the address of the internal memory 11 designated by the instruction 4 (5
5). If there is not enough space, external bus I / F
8 to the external data bus 5 (56). If the executed test instruction 4 is not a test end instruction (5
7) The next test instruction 4 is executed, and if it is a test end instruction, the test control signal 14 is set to Lo and the test instruction 4
Is terminated (58).

FIG. 7 shows an example of use of the internal memory 11, in which the test instruction 4 is stored at the start address where the microprocessor 15 executes the instruction, and the test is started from the test result write start address specified by the test instruction 4. The result (here, the expected value comparison result 0 or 1) is stored. If the internal memory 11 does not have enough space to store the test instruction 4, the test instruction 4 is divided into portions that can be divided. If the space for storing the test results is insufficient, the test circuit 13 controls the external bus I / F 8 to output the test results that could not be written to the external data bus 5.

FIG. 8 is a flow chart showing an example of step 4. If the test result is written in the internal memory 11 (62), the microprocessor 15
Relinquishes the bus right, and the test circuit 13 becomes the bus master (63). The test circuit 13 generates an address of the internal memory 11 in which the test result is stored on the internal address bus 9 and outputs the test result on the internal data bus 10 (64). The test circuit 13 controls the external bus I / F 8 to set the write signal 7 to Hi, and outputs the test result on the internal data bus 10 to the external data bus 5 while the write signal 7 is Hi (65). The data is output to the external data bus 5 while increasing the address of the internal bus 11 until the last test result is output (66, 67).

As described above, according to the present embodiment, a complicated test operation such as a conditional branch can be performed in a state where the test of the peripheral circuit is close to the actual operation, and an efficient test can be performed.

[0023]

As described above, the present invention provides a test circuit for storing a test instruction executed by a microprocessor from an external data bus in an internal memory by controlling an external bus I / F connected to the internal data bus. With such a configuration, it is possible to easily create a complicated test instruction, and it is possible to perform a high-speed and efficient test in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of an integrated circuit test apparatus.

FIG. 2 is a flowchart showing a processing flow of a test device for an integrated circuit;

FIG. 3 is a flowchart showing an example of step 1;

FIG. 4 is a diagram illustrating an example of a test instruction.

FIG. 5 is a flowchart showing an example of step 2;

FIG. 6 is a flowchart showing an example of step 3

FIG. 7 is a diagram illustrating a usage example of an internal memory;

FIG. 8 is a flowchart showing an example of step 4;

FIG. 9 is a block diagram showing a conventional integrated circuit test apparatus.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reset circuit 2 reset signal 3, 4 test instruction 5 external data bus 6 read signal 7 write signal 8 external bus I / F 9 internal address bus 10 internal data bus 11 internal memory 12 arbiter 13 test circuit 14 test control signal 15 microprocessor 16 Peripheral circuits

Claims (4)

[Claims] An internal data bus; a microprocessor connected to the internal data bus; an internal memory connected to the internal data bus; a peripheral circuit connected to the internal data bus; External bus I / F connected to the external data bus connected to the internal data bus via the external bus I / F, and controlling the external bus I / F connected to the internal data bus. A test circuit for storing a test instruction executed by the microprocessor from the external data bus in the internal memory. 2. The integrated circuit test according to claim 1, wherein the test instruction has a test instruction for comparing an observed value observed in the integrated circuit with an expected expected value of the observed value. apparatus. 3. The integrated circuit test apparatus according to claim 1, wherein said test instruction is described in a procedural language such as C language. 4. The test apparatus for an integrated circuit according to claim 1, wherein said internal memory stores a result of said test instruction.