JP2006023257A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce time required for initializing the entire system LSI without increasing the circuit scale. <P>SOLUTION: A scan chain switching circuit 124 for selectively switching an internal bus 153 used for normal operation and a scan chain 161, and a scan circuit 121 for controlling an external non-volatile RAM 103 when the scan chain 161 is selected are provided inside an external non-volatile RAM control circuit 111 in a system LSI 101. In the initial setting, an initial setting value recorded in the external non-volatile RAM 103 is directly set to an internal register without going through an external work RAM 102 and a built-in microcomputer 113. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an integrated circuit, and more particularly to an inspection technique for a large-scale system LSI with a built-in microcomputer function and an initialization technique during normal operation.

<Conventional example 1>
Usually, before shipping a product, it is necessary to check whether the product is manufactured according to specifications. For example, in the case of a semiconductor, it is inspected whether the function of the product is working as specified by actually operating it before shipment.

  However, in the case of a large-scale system LSI, there is a problem that it is very difficult to inspect a system LSI developed without considering the inspection process before shipment for two reasons as described below. was there.

  First, the first reason is that the number of functions of a large-scale system LSI is very large with respect to the time that can be spent for inspection. This has become more prominent due to the recent enhancement of functionality of system LSIs and integration of peripheral components (single chip).

  The second reason is that the number of terminals of the system LSI is smaller than the number of functions to be inspected. Usually, the inspection of the system LSI is performed by applying a signal to a terminal of the system LSI and operating it. However, while the functions of the system LSI have dramatically increased, the number of terminals prepared on the periphery and back surface of the LSI has not increased so much. For this reason, in order to operate the functions inside the LSI, it is necessary to take a very complicated procedure, or there is a possibility that the inspection cannot be completed by the control from the external terminal.

  As a technique for solving such a problem, Patent Document 1 discloses that a scan circuit is built in a large-scale system LSI. Hereinafter, such a conventional technique will be described with reference to FIG.

  The system LSI 200 includes a scan control circuit 201, data holding elements 211 to 214, combinational circuits 221 to 223, a system LSI external terminal group 230, and a scan control terminal 231.

  The data holding elements 211 to 214 are generally called flip-flops, and include a data input terminal D, a data output terminal Q, and a data output terminal NQ that outputs an inverted signal with respect to the output signal of the data output terminal Q. , A clock input terminal CK (not shown), a scan data input terminal DT, and an NT terminal (not shown) for switching to the scan operation mode.

  In FIG. 2, only a minimum circuit is shown to illustrate a simple configuration of the scan circuit. However, the circuit configuration is not limited to this, and for example, two or more data holding elements may be used. There may be any number of combinational circuits.

  Next, the connection of the normal circuit in FIG. 2 will be described. The data holding elements 211 to 214 and the combinational circuits 221 to 223 arbitrarily connect the D terminal, the Q terminal, and the NQ terminal of the data holding elements 211 to 214 and the input / output terminals of the combinational circuits 221 to 223. It is connected so as to perform a predetermined operation depending on the combination.

  In order to obtain the update timing of the data held by the data holding elements 211 to 214, a common synchronous clock signal (not shown) is input to the CK terminals of the data holding elements 211 to 214.

  An input signal to a functional circuit group configured by the data holding elements 211 to 214 and the combinational circuits 221 to 223 is input from one of a plurality of system LSI external terminal groups 230. A processing result in the functional circuit group is output from one of the plurality of system LSI external terminal groups 230.

  In the scan control circuit 201, the functional circuit group and the system LSI external terminal group 230 are fixedly connected, and when the functional circuit group normally operates, the internal functions always operate according to the specifications of the terminal group. It has become.

  Next, the connection of the scan circuit in FIG. 2 will be described. The scan data input terminal DT and the data output terminal Q or NQ in the data holding elements 211 to 214 are connected in a chain by a series of signal lines 251 (shown by bold dotted lines in FIG. 2). Hereinafter, a series of signal lines 251 connected in this manner in a chain shape is referred to as a scan chain.

  The start point 281 and the end point 291 of the scan chain 251 are connected to any one of the plurality of system LSI external terminal groups 230 via the scan control circuit 201, respectively. Here, when the functional circuit group is controlled by the scan control terminal 231, it is used as a dedicated terminal when the system LSI external terminal group 230 has a sufficient number of terminals, while it is usually used when there is no number of terminals. Used as a dual-purpose terminal.

  Next, the operation of the scan circuit and the defect detection principle of the system LSI will be described. When the system LSI is inspected, an input signal is input from the scan control terminal 231 to control the functional circuit group. This operation is called a scan mode.

  At this time, the scan control circuit 201 connects the system LSI external terminal group 230 and the scan chain 251, and the NT terminals (not shown) of the data holding elements 211 to 214 are turned on. When an operation clock is given in this state, data at a terminal connected to the start point 281 of the scan chain is given to the DT terminal of the data holding element 211 and the value is held.

  When the next operation clock is supplied, an inverted signal of the value held in the data holding element 211 is supplied to the DT terminal of the data holding element 212 and the value is held. On the other hand, the next data given to the terminal is given to the DT terminal of the data holding element 211 via the start point 281 of the scan chain, and the value is held. At this time, the value given to the data holding element 212 is an inverted value compared with the value held by the data holding element 211. However, when used in a scan test, the inverted value is used as described later. It does not matter.

  In this way, the data holding elements 211 to 214 are sequentially set while shifting the data, and when the operation clocks are input by the number of the data holding elements 211 to 214, all the data holding elements 211 to 214 are set. Data supplied from the terminal to 214 is held. This series of operations is called scan shift.

  After the scan shift is completed, the NT terminals of all the data holding elements 211 to 214 are turned off. At this time, the values of the data holding elements 211 to 214 are calculated by the combinational circuits 221 to 223, and the calculation results are given to the D terminals of the data holding elements 211 to 214. Then, in the next operation clock, the values based on the calculation results are held in the data holding elements 211 to 214. This operation is called scan capture.

  Then, the scan shift is performed again after the scan capture is completed, so that each value of the captured data holding elements 211 to 214 is output to the end point 291 of the scan chain. By outputting the output result from one of the plurality of system LSI external terminal groups 230, the captured data can be observed.

  Thus, an arbitrary value can be set by scan-shifting the combinational circuits 221 to 223 during scan capture. Further, the operation results of the combinational circuits 221 to 223 can be taken out by scan-shifting.

  Here, since the circuit configuration of the data holding element group constituting the combinational circuit group and the scan circuit is clarified at the development stage of the system LSI 200, the output results of the scan shift and the scan capture are The result of the circuit configuration can be theoretically calculated in advance. Accordingly, by comparing this theoretical value with the actual scan shift and scan capture output results, it is possible to detect whether the internal circuit is manufactured according to the specifications.

  In the conventional example 1, it is described that the circuit of the normal operation is closed, but at the actual scan test, arbitrary values are given to these input terminals to hold the values of the output terminals. Thus, the inspection between the input / output terminals of the normal circuit and the data holding element is performed.

  Here, when the NQ terminal of the previous data holding element is connected to the DT terminal of the data holding element, the data is inverted and delivered. However, it is sufficient that an arbitrary value can be given to each data holding element, and data should be given in consideration of the data inversion point that has been clarified in the LSI development stage. That is, on the scan chain, when a value is given to the data holding element after the data inversion position, it can be dealt with by giving the inverted value. It is also clear that if there are a plurality of inversion locations, it can be handled accordingly. The same applies when observing data after scan capture.

  The inversion signal is used for the following reason. A flip-flop used for a normal data holding element has a Q terminal and an NQ terminal. As a normal function, when only the Q terminal (or NQ terminal) is used in terms of the circuit configuration, it is better to use the unused NQ terminal (or Q terminal) for connecting the scan chain. This is because it is advantageous in terms of out and distribution of wiring resources.

<Conventional example 2>
In general system LSIs, it is often desirable to temporarily hold data during the data processing. It is also necessary to retain settings necessary for data processing. When the amount of data is small, it is held in a data holding element such as a flip-flop. However, when the amount of data is large and the data units are collected, a RAM (Randam Access Memory) may be built in and data may be held in the RAM. As described above, in a complicated system LSI with a large amount of data processing, it is common to use a large number of internal RAMs.

  Here, in order to inspect whether the internal RAM is manufactured according to the specification, it is common to incorporate a circuit for internal RAM testing. As a test method for the internal RAM, a direct access method for inspecting by directly controlling the internal RAM from outside the LSI, and a RAM inspection circuit having an internal RAM inspection circuit and controlling the inspection circuit from the outside. There are two types of indirect access schemes.

  In recent years, the use of internal RAM and the increase in capacity have progressed, and it has become difficult to inspect all functions of all internal RAMs from an external terminal within a certain time. Further, it is necessary to inspect whether the RAM operates at a frequency at the time of actual use, but high-speed access from the external terminal of the system LSI to the internal RAM is becoming difficult. Therefore, the mainstream of the internal RAM inspection method is the indirect access method.

  However, on the other hand, in many cases, a direct access type inspection circuit is built in for the purpose of identifying a defective part in manufacturing, mounting a redundant circuit, and maintaining and improving LSI quality. In the direct access method, the internal RAM has an address bus, an input data bus, an output data bus, a chip enable terminal, a write enable terminal, and the like that are directly connected to an external terminal of the LSI. It can be freely controlled.

  However, in the case of a system LSI having a large number of RAMs, it is often impossible to always connect all the terminals of all the RAMs to the external terminals of the LSI due to the limitation of the number of terminals. In many cases, the RAM to be inspected is selected by an enable terminal and inspected.

  FIG. 3 shows an example of a direct address method which is one of RAM inspection methods. As shown in FIG. 3, the system LSI 301 includes internal RAMs 311 to 313. These are connected to the logic circuit by selector groups 321 to 323 during normal operation, but these selector groups 321 to 323 are switched during a RAM test in which the internal RAMs 311 to 313 are directly accessed from the outside.

  As a result, the address terminals and lead terminals of the internal RAMs 311 to 313 are visible from the outside of the system LSI 301, and the internal RAMs 311 to 313 are easily inspected. In the inspection circuit according to Conventional Example 2, the address bus and the write data bus are shared by the internal RAMs 311 to 313, and the target internal RAM is selected by an enable signal for each of the internal RAMs 311 to 313.

  When it is desired to read the internal RAMs 311 to 313, the data selector 324 may be switched by an enable signal so that the read data of the target internal RAM is output.

<Conventional example 3>
In a system LSI with a built-in microcomputer function, it is necessary to store a program necessary for the built-in microcomputer to execute in a place where the built-in microcomputer can fetch. Here, there are various methods for the storage location, but the storage location is roughly divided into two methods, which are placed inside or outside the system LSI.

  Examples of means for placing a program inside the system LSI include a ROM (Read Only Memory) and a non-volatile RAM incorporated in the system LSI. If any attempt is made to secure an area for storing a large program, the LSI is manufactured. There is a disadvantage that the cost becomes high. Further, with a relatively inexpensive ROM, the program cannot be changed after the system LSI is manufactured. Therefore, at present, the method of placing the program outside the system LSI is the mainstream.

  As means for placing the program outside the system LSI, ROM and nonvolatile RAM are conceivable. The method of placing the program in the ROM is advantageous from the viewpoint of cost and access speed. However, as with the built-in ROM method, the program cannot be modified after hardware implementation, and today's programs have become larger and system LSIs have been used. It is not realistic even from the development speed of the set. For the above reasons, the program used by the system LSI is mainly stored in an external nonvolatile RAM.

  Hereinafter, the program execution operation of the system LSI using the nonvolatile RAM will be described with reference to FIG. As shown in FIG. 4, the system LSI 401 includes an internal microcomputer 411, an external work RAM control circuit 412, a nonvolatile RAM control circuit 413, a data processing circuit group 414, an internal bus 421, and a register access bus 422. I have.

  An external work RAM 402 is connected to the system LSI 401 via an external work RAM control circuit 412, and a nonvolatile RAM 403 is connected via a nonvolatile RAM control circuit 413.

  Next, the operation at the time of initialization of this circuit will be described. The built-in microcomputer 411 whose reset is released after the system LSI 401 is energized fetches a specific address predetermined by the built-in microcomputer 411 in the accessible address space, and starts executing an instruction. In this conventional example 3, the program is stored in the nonvolatile RAM 403, and the first fetch is designed to be accessed here. Thereafter, unless there is a jump instruction, a branch instruction, or the like, fetch and instruction processing are executed in the order of addresses, and the system LSI 401 starts operating.

  However, generally, the non-volatile RAM 403 has low operating performance and cannot keep up with the operating performance of the high-performance built-in microcomputer 411. Therefore, a program using the system LSI 401 having the high-performance built-in microcomputer 411 is executed after copying the program that is always used by the built-in microcomputer 411 from the nonvolatile RAM 403 to the external work RAM 402 having high operation performance.

  Such a copying method includes a method of reading / writing by the built-in microcomputer 411 and a method of providing a copy control circuit in addition to the built-in microcomputer 411 and using the control circuit. Suppose there is nothing.

  On the other hand, the data processing circuit group 414 operates under the control of the built-in microcomputer 411. In order for the data processing circuit group 414 to start operation, it is necessary to perform initial setting from the built-in microcomputer 411 via the register access bus 422.

  FIG. 5 is a flowchart showing a procedure for initializing the system LSI. First, after energizing the system LSI 401 in step S501, the built-in microcomputer 411 is released from reset in step S502, and initial fetch and instruction execution are performed from the nonvolatile RAM 403 in step S503.

  When the minimum instruction processing is completed, the built-in microcomputer 411 or a copy control circuit (not shown) operates, and the program is copied from the nonvolatile RAM 403 to the external work RAM 402 in step S504. After the program transfer is completed, fetching and instruction execution are performed again from the external work RAM 402 in step S505.

  Note that step S504 and step S505 may be performed at the same time in order to shorten the overall initialization time. In that case, the copying control circuit becomes an essential component, and it is necessary to take care that the program being executed in step S505 does not affect the program being copied.

When the initialization of the built-in microcomputer 411 itself is completed, in step S506, the data processing circuit group to be actually operated is initialized. When the initial setting is completed, data processing is actually started in step S507, and the entire system LSI 401 is in a normal operation state.
Japanese Patent Laid-Open No. 2002-250753

  Here, the scan circuit is a factor that increases the circuit scale of the LSI by, for example, about 10%, although it is used only at the time of inspection before shipment (usually about several seconds). The cost of an LSI is greatly influenced by the chip area determined by the circuit scale of the LSI, so it is necessary to develop the chip with as little chip area as possible. However, there is a problem that the cost is increased by mounting the scan circuit in the LSI. Similar problems apply to the RAM test circuit.

  In the system LSI, it takes a certain time from the start of the built-in microcomputer to the initial setting inside the LSI until the actual data processing is started. This is particularly noticeable with the recent high integration of system LSIs and the increase in the scale of programs for executing built-in microcomputers. Such an increase in the time until the operation of the system LSI starts increases the operation start time of a device using the system LSI, and there is a problem that the attractiveness of the product is lowered.

  As described above, the initialization of the entire system LSI takes time because the built-in microcomputer execution program stored in the nonvolatile RAM is temporarily stored in the external work RAM and then read and set by the built-in microcomputer. This is because there is a problem with the procedure. That is, it takes time to initialize the data processing circuit. However, it is not preferable to add a dedicated circuit for solving this problem because it increases the circuit scale of the system LSI.

  The present invention has been made in view of the above points, and an object thereof is to reduce the time required for initialization of the entire system LSI without causing an increase in circuit scale.

  In the present invention, for the above purpose, after the data of the nonvolatile RAM is taken into the system LSI, the inside of the data processing circuit is initialized by using the inspection scanning circuit and the RAM inspection circuit of the data processing circuit. .

That is, the invention of claim 1 is a program calculation processing means for calculating a program,
Program reading means for reading a program to be executed from the program storage means in which the program is stored;
Internal data transfer means for sending the read program to the program processing means;
Data processing means for controlling the program calculation processing means to perform predetermined data processing;
Internal inspection that inspects for defects in the circuit by connecting multiple data holding elements that hold predetermined data in a chain and shifting the data held by each data holding element according to the synchronization clock Means,
An integrated circuit comprising at least a clock control means for controlling a clock for operating the internal inspection means,
Program read selection means for reading data from the program storage means via the program reading means and selecting either the internal data transfer means or the internal inspection means as an output destination of the read data;
A program storage means control means for controlling the program storage means when the program read selection means has selected the internal inspection means as an output destination of the data;
The data processing means is configured to be initialized by sending initial setting data from the program storage means to the internal inspection means.

The invention of claim 2 is an integrated circuit according to claim 1,
A program writing unit for writing data to the program storage unit;
The program storage means control means further has a function of controlling the program writing means to write data output from the internal inspection means to the program storage means,
The holding value of the data holding element of the internal inspection unit is configured to be written into the program storage unit via the program writing unit.

The invention of claim 3 is an integrated circuit according to claim 1 or 2, wherein
The apparatus further comprises an internal inspection result confirmation means for determining the presence / absence of a defect in the circuit based on the data used for the internal inspection and the inspection result output by the internal inspection means.

The invention of claim 4 is the integrated circuit according to any one of claims 1 to 3, wherein
The number of chains of the internal inspection means and the number of data signals in the program reading means are the same.

The invention of claim 5 is an integrated circuit according to any one of claims 1 to 4,
While initializing the data processing means from the program storage means through the internal inspection means, the value of the input / output terminal of the circuit and the input / output direction are fixed so as to be fixed. Input / output terminal control means for controlling the signal is further provided.

The invention of claim 6 is an integrated circuit according to claim 2,
A chain in which the data holding elements in the internal inspection means are connected to each other is configured in a ring shape, and further includes data holding element chain access means for reading or writing data values at arbitrary locations thereof,
The program storage means control means has a function of selecting either the data holding element chain access means or the program writing means and writing data to the program storage means using the selected means. ,
The clock control means has a function of generating a clock by the number of stages of data holding elements connected to the data holding element chain;
A holding value of each data holding element at an arbitrary time is configured to be written to the program storage means via the data holding element chain access means or the program writing means.

The invention of claim 7 is a program calculation processing means for calculating a program,
Program reading means for reading a program to be executed from the program storage means in which the program is stored;
Internal data transfer means for sending the read program to the program processing means;
Data processing means for controlling the program calculation processing means to perform predetermined data processing;
Internal data group holding means for holding a set data group necessary for operating the circuit;
An internal circuit comprising: internal data group holding means direct access means for reading and writing arbitrary locations in the data held in the internal data group holding means,
A program reading destination selecting means for connecting the program reading means and the internal data group holding means direct access means;
A program storage means control means for controlling the program storage means when the program reading destination selection means selects the internal data group holding means direct access means;
The internal data group holding unit is initialized by sending initial setting data from the program storage unit to the internal data group holding unit direct access unit.

The invention of claim 8 is an integrated circuit according to claim 7,
A program writing unit for writing data to the program storage unit;
The program storage means control means further has a function of controlling the program writing means to write data output from the internal data group holding means direct access means to the program storage means,
The holding value of the internal data group holding unit is configured to be written into the program storage unit via the internal data group holding unit direct access unit and the program writing unit.

The invention according to claim 9 is the integrated circuit according to claim 7 or 8, wherein
During the initial setting of the data processing means from the program storage means through the internal data group holding means direct access means, the value of the input / output terminal of the circuit and the input / output direction are fixed to the input / output terminal. It is further characterized by further comprising input / output terminal control means for controlling the connected internal signal.

The invention of claim 10 is the integrated circuit according to claim 1,
The program storage means control means detects that data stored in the program storage means is being read to the internal data transfer means via the program read means, and a period other than this data read period And a function of connecting the program storage means to the internal inspection means.

The invention of claim 11 is an integrated circuit according to claim 1,
It further comprises an address analysis means for analyzing the address information of the data transfer target,
The internal data transfer means has address information for data transfer,
The internal inspection unit has a function of reading or writing data with respect to any data holding element based on the address analyzed by the address analysis unit,
At any time, the program operation processing means can access any data holding element.

The invention of claim 12 is the integrated circuit according to claim 7,
The program storage means control means detects that data stored in the program storage means is being read to the internal data transfer means via the program read means, and a period other than this data read period The program storage means further has a function of connecting to the internal data group holding means direct access means.

  According to the integrated circuit of the present invention, the initialization of the data processing circuit does not go through the external work RAM or the built-in microcomputer in the initialization of the system LSI. The initial setting time of the system LSI can be shortened. In addition, in the present invention, since the scan circuit and the RAM inspection circuit, which are usually provided in the system LSI, are diverted, the increase in the circuit scale for realizing it is slight, which is advantageous in suppressing the increase in cost. It becomes.

  In addition, the state inside the system LSI is held outside the LSI using a scan circuit when the power is turned off, and is initialized using the initialization circuit according to the present invention when the power is turned on, thereby reproducing the state when the power is turned on. Can be made.

  Furthermore, when developing a system LSI, the internal state can be observed by outputting the internal state to an external RAM using a scan circuit or reading the internal state with a built-in microcomputer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or its application.

<Embodiment 1>
FIG. 1 shows a configuration of a system LSI according to the first embodiment of the present invention. As shown in FIG. 1, the system LSI 101 includes an external nonvolatile RAM control circuit 111 (program reading means), an external work RAM control circuit 112 (program calculation processing means), and a built-in microcomputer 113 (data processing means). And a data processing circuit 114 (internal inspection means).

  Among these, the external nonvolatile RAM control circuit 111 includes a scan control circuit 121 (program storage means control means), an external nonvolatile RAM switching circuit 122 (program read selection means), an access control circuit 123, and a scan chain switching. Circuit 124.

  The data processing circuit 114 includes a large number of data holding elements (flip-flops), and the data holding elements are connected in a chain as described in the prior art. In the first embodiment, only the scan chain 161 is described, and description of each data holding element connected in the middle thereof is omitted.

  The external nonvolatile RAM control circuit 111 is connected to an external nonvolatile RAM 103 (program storage means) via a data bus 151 and an address bus 152, and the external work RAM control circuit 112 is externally connected via a data bus 154. It is connected to the work RAM 102.

  The external non-volatile RAM switching circuit 122 connects the data bus 151 from the external non-volatile RAM 103 and the internal bus 153 (internal data transfer means) to enable access from the built-in microcomputer 113 and the external work RAM control circuit 112. Yes.

  Next, the operation of the present invention will be described with reference to FIG. The system LSI 101 starts operation by releasing the reset when the power is turned on. In the conventional technique, the initialization operation is started with the operation clock supplied after the reset is released. In the first embodiment, the initial setting control signal is supplied to supply the scan external clock. At this time, the built-in microcomputer 113 remains stopped.

  The access control circuit 123 starts to operate in response to an initial setting control signal. Then, an address given by a predetermined method (designated from the outside or held internally as a fixed value) is output to the external nonvolatile RAM 103 via the address bus 152. The external nonvolatile RAM 103 returns data corresponding to the address to the system LSI 101 via the data bus 151. Then, the external nonvolatile RAM switching circuit 122 outputs the data from the data bus 151 to the scan chain switching circuit 124 via the parallel / serial conversion circuit according to the initial setting control signal.

  The parallel / serial conversion circuit is mounted in accordance with the bus width and the number of scan chains, and does not have to be mounted because it is not directly related to the essence of the present invention.

  The scan chain switching circuit 124 switches between initial setting data and scan test data, and data from the data bus 151 is output to the scan chain 161 in accordance with the initial setting control signal. .

  When the next operation clock is supplied to the scan external clock, the next address is output from the access control circuit 123. As this address, an increment value of the previous address (a value obtained by adding “1” to the previous value) is suitable, but not particularly limited. Following this, the next data is output from the external non-volatile RAM 103 and output to the scan chain 161 in the same manner as before. At this time, the data input to the start point 181 of the scan chain is set while shifting to the data holding element on the scan chain 161.

  In this way, every time the scan external clock is input, the data in the external nonvolatile RAM 103 is held while being shifted to the data holding element in the data processing circuit 114, and the data setting of the necessary data holding element is completed. End with. Thereafter, the initial setting control signal is canceled and the built-in microcomputer 113 is activated.

  Note that since the initialization of the data processing circuit has already been completed at this point, the data processing can be started. As described in the prior art, the built-in microcomputer 113 fetches from the external nonvolatile RAM 103, transfers the program body from the external nonvolatile RAM 103 to the external work RAM 102, and then executes the program body in the external work RAM 102. .

  As described above, according to the present invention, input data can be set directly to each data holding element from the external nonvolatile RAM 103 without going through the external work RAM 102 or the built-in microcomputer 113. Once complete, data processing can begin. For this reason, it is possible to reduce the time required for initialization of the entire system LSI, and particularly the time required to start data processing.

  On the other hand, by connecting the external nonvolatile RAM 103 and the scan chain 161, not only the initial setting when the power is turned on, but also the value of each data holding element when the power is turned off can be recorded in the external nonvolatile RAM 103. This configuration and operation will be described with reference to FIG.

  The end point 191 of the scan chain 161 is connected to the external nonvolatile RAM switching circuit 122 via the scan control circuit 121. Here, when controlled by the initial setting control signal, this data can be output to the data bus 151. Note that the serial / parallel conversion circuit provided in the middle may not be the same as the parallel / serial conversion circuit described above.

  Then, the value of each data holding element is output to the scan control circuit 121 via the end point 191 of the scan chain 161 using scan shift. The scan control circuit 121 outputs the data to the external non-volatile RAM 103 via the external non-volatile RAM switching circuit 122 when the data is held when the power is turned off. By holding this data in the external nonvolatile RAM 103 and then turning on the power and resetting the data holding elements on the scan chain 161, the state when the power is turned off can be reproduced as it is.

  In general, the scan circuit of the system LSI 101 has a plurality of scan chains in order to shorten the inspection time of the system LSI 101, and the scan shift is simultaneously performed on each chain. In the normal scan chain, the type and order of the tuning are determined in consideration of the location of the data holding element on the LSI and the type of clock for normal operation given to the data holding element. If the scan circuit is used only for LSI inspection, there is no problem with such a configuration.

  However, in the present invention, it is assumed that the scan circuit is also used for initial setting. In that case, considering the ease of program development, it is effective to connect a scan chain for each setting group of the data holding elements. This configuration will be described with reference to FIG.

  An external nonvolatile RAM 602 is connected to the system LSI 601. The bus width used for connection is 8 bits as an example in FIG. 6, but it goes without saying that the bus width is not limited to this.

  The system LSI 601 includes an external nonvolatile RAM switching circuit 611, a scan chain switching circuit 612, data holding element groups 613 and 614, and a built-in microcomputer 615.

  The data holding element groups 613 and 614 necessary for setting constitute a circuit that is connected from the built-in microcomputer 615 via the register access bus 651 and is accessible from the built-in microcomputer 615.

  The external nonvolatile RAM 602 is connected to the data holding element group 613 via the external nonvolatile RAM control circuit 611 and the scan chain switching circuit 612.

  The data holding element group 613 is a data holding element that is the head of each of the scan chain groups (eight in this example), and the initial setting value input from the external nonvolatile RAM 602 is the first data holding element group. 613.

  The data holding element groups 613 and 614 and the subsequent data holding element group (not shown) are connected as a scan chain, and the data stored in the data holding element group 613 is scan-shifted according to the scan clock. Go.

  Here, by making the bit definition (bit 0, bit 1, etc.) of this scan chain group coincide with the bit definition when accessing from the built-in microcomputer 615, the built-in microcomputer 615 is externalized in the same manner as the program for initial setting. It can be held in the nonvolatile RAM 602. Thereby, the transparency of the program can be improved.

  By the way, each external terminal of the system LSI 601 is determined by the internal state and operation of the LSI. Normally, at the initial setting stage during reset or after reset release, the external terminal of the system LSI 601 is on the board on which the system LSI 601 is mounted. The circuit is not adversely affected, or the operation during the period is ensured on the substrate.

  In the initial setting and the state holding operation using the scan chain, an unexpected state may occur during the scan shift. At this time, there is no problem because the inside is not operating, but there is a possibility that the circuit on the substrate outside the system LSI is adversely affected. Specifically, when the output of the external terminal of the system LSI becomes an unexpected logical value at an unexpected timing, the peripheral circuit may operate arbitrarily or the display of the device is arbitrarily performed. There is a risk of problems such as this.

  In the present invention, the initial setting and the state holding operation are performed by inputting the initial setting control signal. By using this signal, the state of each external terminal of the system LSI is fixed, thereby avoiding an adverse influence on the outside. can do.

  In the development stage of the system LSI, there is a case where it is desired to check the operation and state inside the system LSI. As an observation method, it is conceivable that a means for outputting the signal at the observation point directly to the terminal or a means for reading it from the built-in microcomputer is provided in the system LSI in advance. However, in the former, the observation points are limited due to the limitation of the number of terminals, and in the latter, there is a disadvantage that the circuit scale for that is increased.

  The present invention does not have the drawbacks described above, and can provide a function of observing the internal state with a small number of additional circuits. The operation principle will be described with reference to FIG.

  An external nonvolatile RAM 702 is connected to the system LSI 701. The system LSI 701 includes a scan control circuit 711, data holding elements 712 to 714, and an external nonvolatile RAM control circuit 715.

  The scan control circuit 711 and the data holding elements 712 to 714 are connected in a ring shape by a scan chain 721. This configuration is the same as the circuit configuration described with reference to FIG. Therefore, it is possible to realize a function of observing the state inside the circuit without requiring a dedicated circuit.

  The data holding elements 712 to 714 hold values at the time when the operation clock is stopped. Therefore, the internal state can be maintained by stopping the operation clock at the timing to be observed. Next, by performing a scan shift operation, data can be output to the external nonvolatile RAM 702 as in the case of recording the value of each data holding element when the power is turned off.

  Here, the scan control circuit 711 scan-shifts and outputs the shift data from the end point 791 of the scan chain 721 to the external nonvolatile RAM 702, while giving the same data to the start point 781 of the scan chain 721, this data Returns to the internal circuit again.

  For example, in the circuit shown in FIG. 7, the data of the three data holding elements 712 to 714 is output to the external nonvolatile RAM 702 by performing the scan shift three times, while the data of the internal data holding elements 712 to 714 is It will return to the original.

  Here, by giving the operation clock that has been stopped again, the operation can be started again from the state where it was stopped. If recorded in the external non-volatile RAM 702, the value can be arbitrarily extracted using a built-in microcomputer or the like.

  Thus, by controlling the operation clock and the scan external clock, the value of the internal data holding element can be observed at an arbitrary timing.

  Next, an invention for increasing the initialization efficiency and further shortening the initialization time will be described with reference to FIGS.

  The time required for initialization of the system LSI is determined by the procedure and amount of initialization, but is also greatly affected by the operation speed of each component or block related to the initial setting. That is, in FIG. 1, an external non-volatile RAM 103 and an external non-volatile RAM control circuit 111 for reading out programs and initial setting values necessary for initialization, an external work RAM 102 and an external work RAM control circuit 112, a built-in microcomputer 113, and a scan control circuit 121. And the operation speed of the scan chain 161 and the like. These operation speeds are determined by various conditions such as selection of parts, overall required performance as a system LSI, and circuit restrictions. In many cases, they do not necessarily have an optimum operation speed for initialization.

  For example, the case where the operation of the external nonvolatile RAM 103 is slow with respect to the speed of the scan chain 161 and the scan chain 161 waits until data to be initially set is actually read out can be considered. This is particularly noticeable when the number of data buses 151 is larger than the number of scan chains.

  Further, since the built-in microcomputer 113 accesses the external nonvolatile RAM 103 and the external work RAM 102 while performing various processes, the RAMs 102 and 103 are not constantly used. As described above, it is considered that each function or component does not use up its performance completely, and in fact, idle time is generated.

  Also in the present invention, the internal microcomputer 113 and the external work RAM 102 are not operating during the initial setting from the external nonvolatile RAM 103 to the data processing circuit 114 by inputting the initial setting control signal. Further, depending on the operation speed, there is a possibility that data reading from the external nonvolatile RAM 103 may be awaited due to the setting in the data processing circuit 114.

  Therefore, an initial setting control circuit 812 is added to the external nonvolatile RAM control circuit 111 as shown in FIG. This circuit is effective when an initial setting control signal is input.

  The external nonvolatile RAM switching circuit 813 normally connects a data bus 851 from the external nonvolatile RAM 811 (103 in FIG. 1) and an internal bus 852 (internal bus 153 in FIG. 1), and has a built-in microcomputer (113 in FIG. 1). ) And an external work RAM control circuit (112 in FIG. 1).

  When the initial setting control signal is input and output to the scan chain 853, the operation of the initial setting control circuit 812 switches the external nonvolatile RAM switching circuit 813, and the signal of the data bus 851 is passed through the scan chain switching circuit 814. It is output to the scan chain 853.

  The parallel / serial conversion circuit is mounted as necessary depending on the bus width of the data bus 851 and the number of scan chains 853, but the description is omitted because it is not the essence of the present invention.

  With this configuration, the external nonvolatile RAM 103 can output data to the external work RAM 102 and the built-in microcomputer 113 via the internal bus 153 while outputting the initial setting data to the scan chain 853. The time required for initialization of the LSI 101 can be shortened.

<Embodiment 2>
FIG. 9 shows a configuration of a system LSI according to the second embodiment of the present invention. As shown in FIG. 9, the system LSI 901 includes an external nonvolatile RAM control circuit 911, an external work RAM control circuit 912, a built-in microcomputer 913, and a data processing circuit 914.

  The external nonvolatile RAM control circuit 911 includes an internal RAM control circuit 921, an external nonvolatile RAM switching circuit 922, and an access control circuit 923.

  The data processing circuit 914 includes internal RAMs 931 to 933 for holding initial setting data and temporary data during processing.

  The external nonvolatile RAM control circuit 911 is connected to the external nonvolatile RAM 903 via a data bus 951 and an address bus 952.

  Since the connection between the external work RAM 902, the external work RAM control circuit 912, and the built-in microcomputer 913 is the same as that in the first embodiment, the description thereof is omitted.

  Next, the operation of the present invention will be described with reference to FIG. The system LSI 901 starts operation by releasing the reset when the power is turned on. Then, after the reset is released, an initial setting control signal is given to operate the access control circuit 923. At this time, the built-in microcomputer 913 remains stopped.

  The access control circuit 923 outputs an address to the external nonvolatile RAM 903 via the address bus 952, while sending the address of the corresponding internal RAM 931 to 933 to the internal RAM control circuit 921 via the address bus 961.

  The external nonvolatile RAM 903 sends data corresponding to the given address to the internal RAM control circuit 921 via the data bus 951 and the bus 962.

  The internal RAM control circuit 921 specifies the target internal RAM 931 to 933 according to the address from the address bus 961 and outputs it to any one of the corresponding enable signals 963 to 965, while sending it to the internal RAM 931 to 933. The address to be written is output to the address bus 966.

  Here, when the initial setting control signal is input, the data of the bus 962 is output to the bus 967 and written to the internal RAMs 931 to 933 selected by the enable signals 963 to 965. As a result, data is set in the internal RAMs 931 to 933 under the control of the address control circuit 923.

  When the setting of the internal RAMs 931 to 933 is completed, the initial setting control signal is released and the internal operation clock is supplied. Thereby, the built-in microcomputer 913 starts operation, and executes the program in the same manner as in the first embodiment.

  Also in the second embodiment, like the initial setting by the scan circuit in the first embodiment, it is possible to reduce the time required for initialization of the entire system LSI, in particular, the time until data processing is started.

  Further, in the data processing circuit 914 in FIG. 9, the function according to the present invention can be realized without adding a large circuit by using the internal RAM direct access system circuit described with reference to FIG.

  Note that the initialization of the internal RAM can be similarly configured with respect to the initialization time reduction by the initial setting control circuit in the first embodiment. Since the principle and operation are the same as those using a scan circuit, description thereof is omitted here.

<Embodiment 3>
FIG. 10 shows a configuration of a system LSI according to the third embodiment of the present invention. As shown in FIG. 10, the system LSI 1001 includes an external nonvolatile RAM control circuit 1011, a built-in microcomputer 1012, and a data processing circuit 1013.

  The external nonvolatile RAM control circuit 1011 includes a scan control circuit 1021, an external nonvolatile RAM switching circuit 1022, an address conversion circuit 1023, and a scan chain switching circuit 1024.

  A plurality of data holding elements (not shown) are arranged in the scan chain 1053. The external nonvolatile RAM control circuit 1011 and the external nonvolatile RAM switching circuit 1022 have an access function with the external nonvolatile RAM as described in the first or second embodiment. Does not affect the function, so the description of the function is omitted.

  Next, the operation of the present invention will be described with reference to FIG. The built-in microcomputer 1012 sends a corresponding address to the address conversion circuit 1023 via the address bus 1052 in order to access an arbitrary data holding element on the scan chain 1053 at an arbitrary timing.

  The address conversion circuit 1023 identifies the scan chain 1053 of the target data holding element and its location (number of stages) according to the received address, and passes the information to the scan control circuit 1021.

  The scan control circuit 1021 stops supplying the operation clock to the data processing circuit at this stage, and supplies the scan clock after switching to the scan mode by turning on the NT terminal of each data holding element.

  Here, when the access from the built-in microcomputer 1012 is read (read), the supply of the scan clock is continued until the data of the target data holding element is output from the end point 1091 of the scan chain 1053. At this time, by supplying data output from the end point 1091 of the scan chain 1053 to the start point 1081, the state of the data holding element at the time of reading can be reproduced.

  When the data of the target data holding element is output, the built-in microcomputer 1012 can read the desired data by outputting the value to the bus 1051 via the external nonvolatile RAM switching circuit 1022.

  After that, the data holding elements in the data processing circuit 1013 can be returned to their original values by continuing to supply the scan clock for the number of stages of the scan chain.

  On the other hand, when the access from the built-in microcomputer 1012 is write (write), the data to be written received from the bus 1051 is sent to the scan chain switching circuit 1024 via the external nonvolatile RAM switching circuit 1022.

  The scan control circuit 1021 continues to supply the scan clock until the value of the target data holding element is output from the end point 1091 of the scan chain 1053. At this time, supplying data output from the end point 1091 of the scan chain 1053 to the start point 1081 is the same as in the case of the above-described reading.

  When the data of the target data holding element is output, the scan chain switching circuit 1024 is switched to replace the data from the bus 1051. After that, the scan path switching circuit 1024 is returned to the original state, and the scan shift is continued by the number of stages of the scan chain, so that only the target data holding element is rewritten with new data, and the other data holding elements are left as they are. Can keep.

  The present invention can shorten the time required to actually start up and start operation of digital devices incorporating a system LSI when the power of these devices is turned on, and further maintains the state when the power is turned off. Since the highly practical effect that the state when the power is turned off can be easily reproduced when the power is turned on is obtained, it is extremely useful and has high industrial applicability.

It is a structural example which uses the scan circuit in Embodiment 1 of this invention for initial stage operation | movement. 10 is a configuration example of a scan circuit in Conventional Example 1. 10 is a configuration example of a direct access RAM inspection circuit in Conventional Example 2. 12 is a configuration example of a circuit related to initialization of a system LSI in Conventional Example 3. It is an example of the procedure regarding initialization of the system LSI in the prior art example 3. 2 is a configuration example of a circuit that unifies bit definitions of a bus and an internal scan chain in Embodiment 1 of the present invention. It is a figure which shows the principle of the internal state observation function using the scan chain in Embodiment 1 of this invention. 2 is a configuration example of a circuit related to initialization of a system LSI in Embodiment 1 of the present invention. It is an example of a structure of the external non-volatile RAM control circuit with the initial setting control circuit in Embodiment 2 of this invention. It is a structural example of the system LSI which can access a data processing circuit from the built-in microcomputer in Embodiment 3 of this invention using a scanning circuit.

Explanation of symbols

101 System LSI (integrated circuit)
102 External work RAM
103 External non-volatile RAM (program storage means)
111 External nonvolatile RAM control circuit (program reading means)
112 External work RAM control circuit (program operation processing means)
113 Built-in microcomputer (data processing means)
114 Data processing circuit (internal inspection means)
121 Scan control circuit (program storage means control means)
122 External nonvolatile RAM switching circuit (program read selection means)
123 Access control circuit 124 Scan chain switching circuit 153 Internal bus (internal data transfer means)
161 Scan chain 601,701,901,1001 System LSI
802 External work RAM
602, 702, 903 External nonvolatile RAM
611, 715, 811, 911, 1011 External nonvolatile RAM control circuit 912 External work RAM control circuit 615, 913, 1012 Internal microcomputer 914, 1013 Data processing circuit 711, 1021 Scan control circuit 813, 922, 1022 External nonvolatile RAM switching Circuit 923 Access control circuit 612, 814, 1024 Scan chain switching circuit 853, 1053 Scan chain 712, 713, 714 Data holding element (flip-flop)
931, 932, 933 Internal RAM
613, 614 Data holding element group 812 Initial setting control circuit 921 Internal RAM control circuit 1023 Address conversion circuit

Claims (12)

Program calculation processing means for calculating a program;
Program reading means for reading a program to be executed from the program storage means in which the program is stored;
Internal data transfer means for sending the read program to the program processing means;
Data processing means for controlling the program calculation processing means to perform predetermined data processing;
Internal inspection that inspects for defects in the circuit by connecting multiple data holding elements that hold predetermined data in a chain and shifting the data held by each data holding element according to the synchronization clock Means,
An integrated circuit comprising at least a clock control means for controlling a clock for operating the internal inspection means,
Program read selection means for reading data from the program storage means via the program reading means and selecting either the internal data transfer means or the internal inspection means as an output destination of the read data;
A program storage means control means for controlling the program storage means when the program read selection means has selected the internal inspection means as an output destination of the data;
An integrated circuit, wherein the data processing means is initialized by sending initial setting data from the program storage means to the internal inspection means. The integrated circuit of claim 1, wherein
A program writing unit for writing data to the program storage unit;
The program storage means control means further has a function of controlling the program writing means to write data output from the internal inspection means to the program storage means,
An integrated circuit characterized in that a held value of a data holding element of the internal inspection means is written into the program storage means via the program writing means. The integrated circuit according to claim 1 or 2,
An integrated circuit, further comprising an internal inspection result confirmation means for determining the presence or absence of a defect in the circuit based on data used for internal inspection and an inspection result output by the internal inspection means. The integrated circuit according to any one of claims 1 to 3,
The integrated circuit according to claim 1, wherein the number of chains in the internal inspection means and the number of data signals in the program reading means coincide. The integrated circuit according to any one of claims 1 to 4,
While initializing the data processing means from the program storage means through the internal inspection means, the value of the input / output terminal of the circuit and the input / output direction are fixed so as to be fixed. An integrated circuit, further comprising input / output terminal control means for controlling a signal. The integrated circuit according to claim 2, wherein
A chain in which the data holding elements in the internal inspection means are connected to each other is configured in a ring shape, and further includes data holding element chain access means for reading or writing data values at arbitrary locations thereof,
The program storage means control means has a function of selecting either the data holding element chain access means or the program writing means and writing data to the program storage means using the selected means. ,
The clock control means has a function of generating a clock by the number of stages of data holding elements connected to the data holding element chain;
An integrated circuit, wherein a holding value of each data holding element at an arbitrary time is written to the program storage means via the data holding element chain access means or the program writing means. Program calculation processing means for calculating a program;
Program reading means for reading a program to be executed from the program storage means in which the program is stored;
Internal data transfer means for sending the read program to the program processing means;
Data processing means for controlling the program calculation processing means to perform predetermined data processing;
Internal data group holding means for holding a set data group necessary for operating the circuit;
An internal circuit comprising: internal data group holding means direct access means for reading and writing arbitrary locations in the data held in the internal data group holding means,
A program reading destination selecting means for connecting the program reading means and the internal data group holding means direct access means;
A program storage means control means for controlling the program storage means when the program reading destination selection means selects the internal data group holding means direct access means;
An integrated circuit characterized in that the internal data group holding means is initialized by sending initial setting data from the program storage means to the internal data group holding means direct access means. The integrated circuit of claim 7, wherein
A program writing unit for writing data to the program storage unit;
The program storage means control means further has a function of controlling the program writing means to write data output from the internal data group holding means direct access means to the program storage means,
An integrated circuit characterized in that the held value of the internal data group holding means is written into the program storage means via the internal data group holding means direct access means and the program writing means. The integrated circuit according to claim 7 or 8,
During the initial setting of the data processing means from the program storage means through the internal data group holding means direct access means, the value of the input / output terminal of the circuit and the input / output direction are fixed to the input / output terminal. An integrated circuit further comprising input / output terminal control means for controlling an internal signal to be connected. The integrated circuit of claim 1, wherein
The program storage means control means detects that data stored in the program storage means is being read to the internal data transfer means via the program read means, and a period other than this data read period The integrated circuit further comprises a function of connecting the program storage means to the internal inspection means. The integrated circuit of claim 1, wherein
It further comprises an address analysis means for analyzing the address information of the data transfer target,
The internal data transfer means has address information for data transfer,
The internal inspection unit has a function of reading or writing data with respect to any data holding element based on the address analyzed by the address analysis unit,
An integrated circuit characterized in that the program operation processing means can access any data holding element at any time. The integrated circuit of claim 7, wherein
The program storage means control means detects that data stored in the program storage means is being read to the internal data transfer means via the program read means, and a period other than this data read period The integrated circuit further comprises a function of connecting the program storage means to the internal data group holding means direct access means.

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