JP2007087176A - Storage element verification method for logic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To advance a simulation cycle by read access to a storage element during data reference to a storage element for preventing excess time consumption for speedup of logic simulation verifying a logic circuit in LSI development. <P>SOLUTION: In this verification method, the storage element is accessed while referring to and updating a list, in which information about the storage element to be verified is registered. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to verification of logic circuits in LSI development.

  Conventionally, the verification method of a memory element using logic simulation in LSI development is that each verification person creates and verifies a test that accesses the memory element according to the verification guideline of the memory element based on the specification to be verified. Was that. The memory element verification guidelines document a data short-circuit verification method, an address short-circuit verification method, and the like.

  A conventional example will be described with reference to FIG.

(Conventional example)
In FIG. 3, 1 is a module A to be verified having a register 1 at address 32'h1000 and a register 2 at address 32'h1004, which is a 32-bit data storage element, and 2 is an address 32'h2000, which is a 32-bit data storage element Module B and 3 to be verified, which have register 3, address 32'h2004 register 4, and address 32'h2008 register 5, issue a bus C transaction and access module A and module B via bus C. CPU bus function model for verification purposes, 4 is module A, module B and bus C connecting CPU bus function model, 5 is module B functional specification, 6 is module A functional specification, 7 is Memory element verification guideline, 8 is module B register 3, register 4 and register that module B verifier B created based on module B specification and storage element verification guideline. Test of Star 5, 9 denotes a register 1 and the test of the register 2 of the staff in charge of verification A is module A specification and module A that was created in the memory element based on the verification guidelines of the module A.

  In the logic verification of LSI development, as a pre-stage for verifying the function specific to the verification target, first, basic verification is performed, that is, verification of the memory element in the verification target.

  Module A verifier A pays attention to module A's storage element from the module A specification, and in accordance with the storage element verification guidelines, module A's register 1 and register 2 storage element tests Create a register test. The contents of the module A register test in 9 are the instructions from the CPU bus function model to the CPU bus function model that issues bus C transactions such as writing to and reading from the module A register, and the values and registers that read the register data. This is verification of the expected value with the data to have. By executing the register test of 9, write and read access is performed to the register 1 and register 2 of the module A from the CPU bus function model, and the memory element register 1 and register 2 of the module A are verified by comparing the expected values. Done.

  Similarly, verifier B of module B creates a register test for module 8 of module B based on the module B specification and storage element verification guidelines separately from verifier A, and the test is a CPU bus function. By issuing an instruction to the model, the CPU bus function model verifies the register 3, the register 4, and the register 5, which are the storage elements of the module B, by accessing the module B and comparing the expected values.

  The memory device verification guideline 7 describes items to be verified, what data is used to verify the items, and what access sequence is performed. Items to be verified include an initial value at the time of reset, data storage short-circuit or address short-circuit.

  An example of a data short-circuit is when a 32-bit data 32'h0000_000F write transaction is performed on the 32-bit module A register 1 from the CPU bus function model, the actual module A register 1 data becomes 32'h000F_0000. is there. An example of an address short circuit is a problem that when a write transaction is performed from the CPU bus function model to the module A register 1 address 32'h1000, the module A register 2 at address 32'h1004 is written instead of the module A register 1.

  The description of the register test is only written according to the sequence in the verification guideline for the instruction to the CPU bus function model and the expected value comparison, and the difference between each register test is only the part depending on the difference in the number of registers and the address. It is.

  In addition, a case where the processing is changed according to the current register setting when performing the logic verification of the module will be described with reference to FIG. In the test No. 8, the data in the register 1 of the module A is read via the bus C, and the processing is changed according to the data. The data is stored in the variable data, and access to the module A via the bus C does not occur when the data is referred to next time. However, if another test writes to the register 1 during the same simulation, it may conflict with the actual register state.

  FIG. 5 shows an example corresponding to such a case. Even when the test A1 of 8 refers to the register 1 for the second time and thereafter, data is read from the register 1 of the module A, thereby avoiding inconsistencies in the system test that performs parallel operation with other tests.

For example, Patent Document 1 can be cited as a conventional example.
JP 10-1111887 A

  As described in the above conventional example, the register test includes many mechanical work aspects of describing the test in accordance with the storage element verification guidelines, and is a basic test before verifying the module specific function. Nevertheless, the test description has a very inefficient problem of requiring a lot of time.

  Further, since each verification person describes the register test to be verified, there is a possibility that the quality may not be sufficient depending on the test due to a description mistake or the like, and the quality may differ between verification persons or between tests.

  Furthermore, when a plurality of tests are operated in parallel, there is a problem that a simulation cycle is advanced by reading from the register every time the test refers to the current register setting, and extra time is consumed.

  In order to solve the above problem, a storage element is verified by a list for registering information of a storage element to be verified, and a device that performs verification by accessing and comparing the storage element while referring to and updating the list. Provide a verification method.

  The elements of the storage element information to be registered in the list are “storage element name”, “address”, “initial value data”, “current data”, “writable”, “readable”, “write” It is an element such as "Is it good?"

  The list is a list in which all the verification persons can arbitrarily update the information of the storage element.

  The method of accessing the storage element and comparing the expected value performed by the verification apparatus follows the verification guidelines for the storage element.

[Action]
By using a verification method for verifying a storage element by a list for registering information of a storage element to be verified according to the present invention, and a device that performs verification by comparing and expecting the storage element while referring to and updating the list The task of the person in charge of verifying each module is only to register the information about the storage element from the module specification in the list, and access to the storage element and the expected value comparison are automatically performed according to the verification guideline of the storage element. .

  Accordingly, it is possible to omit a time-consuming work including many mechanical work aspects of describing a test in accordance with a verification guideline for a storage element. In addition, since the same verification device does not perform the test by each verification person, the quality is not sufficient depending on the test due to a description mistake or the like, and the quality does not differ between verification persons or between tests.

  Further, since the list is updated at the time of writing, it is only necessary to refer to the list when referring to the data in the storage element, and it is not necessary to advance the simulation cycle by accessing the storage element and consume extra time.

  With the verification method of the present invention described above, the storage element can be verified simply by registering the information of the storage element in the list, and the labor of the person in charge of verification can be saved. Can be devoted to. Further, the quality of verification of the memory element as a whole can be improved.

  Further, when referring to the data in the storage element, the simulation cycle is not advanced by accessing the storage element, so that no extra time is consumed, and the simulation speeds up.

  Therefore, by using the verification method of the present invention, it is possible to efficiently perform LSI logic verification, shorten the LSI development period, and develop a high-quality LSI.

Example 1
First, the Example with respect to Claims 1-4 is demonstrated using FIG.

  In FIG. 1, 1 is a module A to be verified having a register 1 at address 32'h1000 and a register 2 at address 32'h1004, which is a 32-bit data storage element, and 2 is an address 32'h2000, which is a 32-bit data storage element Module B, 3 to be verified, having register 3, address 32'h2004, register 4, and address 32'h2008, register 5 issues a bus C transaction to module A and module B via bus C. CPU bus function model for verifying access, 4 is module A, module B and bus C connecting the CPU bus function model, 5 is the memory element verification guidelines, 6 is the functional specification of module A, 7 is Functional specification of module B, 8 is a list for registering information of the storage element to be verified, 9 is a list by accessing the storage element and comparing expected values while referring to and updating the list of 8 Apparatus for performing, 10 is the details of the module A register 1 information registered in the list of 8.

  Issue a CPU model command to perform a register access bus C transaction to verify all registers registered in the 8 storage element information list and compare expected values according to the register verification sequence in the storage element verification guidelines A verification device is provided.

  Each register information registered in the list includes "register name", "address", "initial value data", "current data", "writable", and "readable" as shown in 10 register 1 information , "Is it OK to write" element. Verification is performed using the “initial value data” in the register information as an expected value at reset. When writing to the register from the CPU bus function model, the data to be written is updated to "current data" in the register information. Use as expected value. It is used as a mask value when the register information such as the reserved area of the register is not reflected in the register data depending on the elements of the register information “Writable” and “Readable”. The register information “Would it be okay to write” indicates register data that causes malfunction such as malfunction when a value for verification is written, and is used to indicate that verification is not performed. . The 9 verification devices automatically verify the storage elements based on the register information in the storage element information list and the access sequence in the verification guideline.

  The person in charge of verification of module A pays attention to the register that is the storage element from the module A specification, and only registers the information of register 1 and register 2 in the storage element information list of 8 to verify the storage element of module A. Yes.

  Similarly, the person in charge of verifying module B pays attention to the register that is a storage element from the module B specification, and only registers the information of register 1, register 2, and register 3 in the storage element information list of module B. The memory element can be verified.

(Example 2)
Next, an embodiment corresponding to claim 5 will be described with reference to FIG.

  As shown in FIG. 1, there are two devices that perform verification by accessing the storage element and comparing the expected value while referring to and updating the list of 8 and let them be 9 verification devices A and 9 ′, respectively. Assume that both the verification devices A and B perform read / write access to the register 1 of 8.

  First, when 9 verification devices A write to 1 register 1 in order to set the operation of module A, the “current data” of register 1 information in 8 storage element information lists is updated at the same time. Next, when the verification device B of 9 ′ refers to the data of the register 1 of 1, the actual register 1 is not accessed, and “current data” of the register 1 information of the storage element information list of 8 is read. refer.

It is explanatory drawing of the Example with respect to Claims 1-4 of this invention. It is explanatory drawing of the Example with respect to Claim 5 of this invention. It is explanatory drawing of the prior art example with respect to Claims 1-4. It is explanatory drawing of the prior art example with respect to Claim 5. It is explanatory drawing of the prior art example with respect to Claim 5.

Explanation of symbols

1 Module A
2 Bus function model
4 Bus C
5 Memory element verification guidelines
6 Functional specifications of module A
7 Module B Functional Specification
8 List for registering information on storage elements to be verified
9 Device for verification
10 Module A register 1 information details

Claims (5)

  In a logic simulation for verifying a logic circuit in LSI development, it is necessary to have a list for registering information of a memory element to be verified and a mechanism for accessing the memory element based on the list information and performing verification by comparing expected values. A verification method of a characteristic storage element.   In the information of the storage element in claim 1, the element includes information such as the name, address, initial value data, current data, writeable, readable, or writable as the element. Feature verification method.   2. The verification method according to claim 1, wherein in the list for registering the information on the memory element in the above-mentioned list, the person in charge of the verification can arbitrarily update the information on the memory element to be verified.   2. The verification method according to claim 1, wherein the verification of the storage element includes data short circuit verification, address short circuit verification, reset initial value verification, and the like.   The verification method according to claim 1, wherein in the list for registering information of the storage element, information is extracted from the list instead of extracting information from the storage element.

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