JP2001093933A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate deformation of a solder bump or short-circuiting, as well as contamination on the surface of an LSI through one-time formation using reflow of the solder bump and to improve the reliability. SOLUTION: This manufacturing method for a semiconductor device includes a first step for forming a plurality of electrodes 11 as connection terminals on an LSI board 10 of flip-chip type, and forming a barrier metal layer made of conductive paste on the electrodes 11 and a buffer material layer made of photo resist 13 on the surface of the LSI board excluding the electrodes 11 at the same thickness, a second step for conducting an electric test in which the probe of a measuring device is brought into contact with the barrier metal layer on the respective electrodes and selecting an appropriate LSI, and a third step for forming respectively a solder bump 16 on the barrier metal layer 15 of the selected LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an improved electrode structure and improved reliability of solder bumps, and a method of manufacturing the same.

[0002]

2. Description of the Related Art An electrode structure of a general flip-chip type LSI is disclosed in Japanese Patent Application No. 1-214141. This electrode structure is shown as a cross-sectional view in FIG. That is, an aluminum (Al) or copper pad 11 is provided on a silicon (Si) substrate 10, and a protective film (passivation film) made of polymit or the like is provided around the pad.
12 are formed. On this aluminum pad 11, Ti
A barrier metal layer 20 made of -Cu, Cr-Cu or the like is provided, and a solder bump 16 is formed on the barrier metal layer 20.

[0003] The manufacturing process of this electrode portion is shown in the flow chart of FIG. First, in step S1, aluminum pads 11 are formed on a Si substrate 10 at a predetermined pitch, and are formed so as to cover the periphery thereof with a protective film 12. In this wafer state, in the next step S11, a barrier metal layer 20 is formed on the entire surface by sputtering or the like. Further, in step S12, a photoresist is applied, exposed and developed, and holes 14 are formed on the aluminum pad 11 at a predetermined pitch. Next, step S13
The barrier metal layer 20 on the aluminum pad 11 in the hole 14
The solder is deposited thereon by plating, the photoresist is removed, and unnecessary barrier metal is removed. next,
In step S14, hemispherical solder bumps 16 are formed on the barrier metal layer 20 on which the solder has been deposited by a reflow method.

In step S15, an electrical test (P / W) in a wafer state is performed, and a hemispherical solder bump 16 is formed again by a reflow method. Further, in step S16,
The wafer is formed into pellets (pieces) by dicing, firstly sorted by an electrical test, and burn-in test (BT) for a temperature test and secondly sorted by an electrical test. In this step S17, the shape of the hemispherical solder bumps 16 is adjusted by a reflow method if necessary, and mounted on a motherboard.
To complete.

[0005]

According to the above-described LSI electrode forming method, an electrical test (P / W) is performed in a wafer state after the formation of the hemispherical solder bumps 16, and an electrical test (P / W) is performed in an individual state. Primary screening), BT test, electrical test (2
Since the next sorting is performed, there is a problem that the number of times of reflow increases, and the solder bump 16 is deformed by heating during the BT test, thereby causing a short circuit.

In the conventional LSI, when an electrical test (P / W) is performed by directly applying a probe to the aluminum pad 11 for an electrical test, scratches on the trace of the needle are formed, and a thin film is formed. The formation of a certain barrier metal layer 20 has an adverse effect such as poor adhesion. Therefore, a series of electrical tests are performed after the formation of the solder bumps, and the solder bumps 16 may be deformed or short-circuited.

Further, since the surface of the LSI is not packaged but is covered only with a thin passivation film (protective film), the surface is liable to be contaminated in a physically and chemically unstable state. There is also.

[0008] The object of the present invention is to solve these problems,
An object of the present invention is to provide a semiconductor device in which formation is performed once by reflow of a solder bump to eliminate deformation and short-circuit and contamination of an LSI surface and a method of manufacturing the same.

[0009]

According to the structure of the semiconductor device of the present invention, a plurality of electrodes serving as connection terminals are provided on a flip-chip type LSI substrate, a barrier metal layer is formed on each of these electrodes, and a plurality of electrodes are formed on the electrodes. A buffer material layer made of photoresist is arranged on the substrate surface of the other LSI with the same thickness, and a solder bump is provided on each barrier metal layer on the electrode.

In the present invention, the barrier metal layer may be made of a conductive paste, and a conductive layer may be provided between each electrode on the substrate and the barrier metal layer.

The structure of the method for manufacturing a semiconductor device of the present invention is as follows.
A plurality of electrodes serving as connection terminals are formed on a flip-chip type LSI substrate, a photoresist layer is formed on a substrate including these electrodes, and openings are formed on the respective electrodes of the photoresist layer. The openings of the photoresist layers are filled with a conductive material such as a conductive base, and the filled conductive materials are cured to form barrier metal layers, and solder bumps are formed on each of the barrier metal layers. It is characterized by the following.

According to another aspect of the method of manufacturing a semiconductor device of the present invention, a plurality of electrodes serving as connection terminals are provided on a flip-chip type LSI substrate, and a plurality of electrodes are provided on these electrodes except for a barrier metal layer and the electrodes. A first step of forming a buffer layer made of a photoresist with the same thickness on the substrate surface of the LSI and an electrical test by bringing a probe of a measuring instrument into contact with a barrier metal layer on each of the electrodes. Good L
The method includes a second step of selecting an SI and a third step of forming a solder bump on each of the barrier metal layers of the selected good LSI.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an LSI according to a first embodiment of the present invention.
FIG. 2 is a flow chart showing a manufacturing process of the electrode portion of the LSI shown in FIG. In the present embodiment, a buffer material layer (barrier metal layer) of a conductive paste 15 having a thickness of 50 to 100 μm is formed on an aluminum electrode 11 of a flip-chip type LSI provided on a silicon substrate 10. 50 to 10 on the LSI surface excluding
A buffer layer made of a photoresist 13 having a thickness of 0 μm is formed. As in the present embodiment, as shown in FIG.
3) and providing the barrier metal layer (15) on the electrode 11 can reduce damage to the LSI surface and the electrode.

The manufacturing process of this embodiment is as shown in FIG.
First, in step S1, an aluminum pad 1 is placed on a Si substrate 10.
1 are formed at a predetermined pitch, and are formed so as to cover the periphery thereof with a protective film 12. In this wafer state, the next step S2
Then, a photoresist 13 is applied, exposure and development processes are performed, and holes 14 are formed on the aluminum pad 11 at a predetermined pitch. Next, in step S3, a conductive paste 15 made of an Ag-Pd paste or a Cu paste is supplied onto the aluminum pad 11 in the hole 14 and heat-treated.
5 is cured.

In this embodiment, at this stage S4, an electrical test (P / W) in a wafer state is performed. Further, in the next step S5, the wafer is formed into pellets (pieces) by dicing, subjected to primary screening by an electrical test, and subjected to a burn-in test (BT) of a temperature test and secondary sorting by an electrical test. At the end of the electrical test, at step S6, hemispherical solder bumps 16 are formed on the cured conductive paste 15 by a reflow method, and mounted on a motherboard to complete an LSI.

In the case of this embodiment, since the buffer layer (barrier metal layer) made of the conductive paste 15 is formed on the aluminum electrode 11, an electrical test in a wafer state is performed before the solder bump 16 is formed. (P / W), electrical test in individual state (primary sorting), burn-in test (B
T), electrical test (secondary sorting) can be easily performed,
The damage to the chip surface electrode of the LSI is small, and the solder bump 16 is not damaged. Furthermore, LSI
The reliability of the connection of the solder bumps 16 when the semiconductor device is mounted on a motherboard can be improved, and a highly reliable product can be obtained without contamination of the LSI chip surface.

FIG. 3 is a partial sectional view of an electrode of an LSI according to a second embodiment of the present invention. In the present embodiment, the aluminum electrode 1
1, a conductive layer 17 made of a barrier metal is formed, and a buffer layer (barrier metal layer) made of a conductive paste 15 is formed on the conductive layer 17.

In this embodiment, since the conductive layer 17 made of a barrier metal such as a Cu layer formed by plating or the like is formed on the aluminum electrode 11, the buffering by the conductive paste 15 such as Ag-Pd paste is performed. There is a feature that the reliability of the processing of the material layer is increased, the LSI can be easily handled, and the reliability of the buffer material layer of the conductive paste 15 can be improved.

[0019]

As described above, according to the present invention,
Electrical test and burn-in test can be performed reliably before forming the solder bumps that will become the electrodes of the flip-chip type LSI, thereby improving the connection reliability of the solder bumps and the connection reliability when mounted on the motherboard. And the LSI chip surface is not contaminated,
There is an effect that a highly reliable product can be obtained, and further, an LSI can be easily handled.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a manufacturing process of FIG. 1;

FIG. 3 is a partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a partial cross-sectional view of a conventional semiconductor device.

FIG. 5 is a flowchart illustrating a manufacturing process of FIG. 4;

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 11 Al pad 12 protective film 13 photoresist 14 hole 15 conductive paste 16 solder bump 17 conductive layer 20 barrier metal layer

Claims (6)

[Claims] A plurality of electrodes serving as connection terminals are provided on a substrate of a flip-chip type LSI, a barrier metal layer is provided on each of these electrodes, and a buffer made of photoresist is provided on a surface of the LSI substrate other than the electrodes. And a material layer disposed at the same thickness, and a solder bump provided on each of the barrier metal layers on the electrodes. 2. The semiconductor device according to claim 1, wherein the barrier metal layer is made of a conductive paste. 3. The semiconductor device according to claim 1, wherein a conductive layer is provided between each electrode on the substrate and the barrier metal layer. 4. A plurality of electrodes serving as connection terminals are formed on a substrate of a flip-chip type LSI, a photoresist layer is formed on a substrate including these electrodes, and a photoresist layer is formed on each of the electrodes of the photoresist layer. An opening is formed, and the opening of the photoresist layer is filled with a conductive material such as a conductive base, and the filled conductive material is cured to form a barrier metal layer. A method for manufacturing a semiconductor device, comprising forming a solder bump. 5. A plurality of electrodes serving as connection terminals are provided on a substrate of a flip-chip type LSI, and a barrier metal layer is formed on each of these electrodes and a buffer material made of a photoresist is formed on a surface of the LSI substrate other than the electrodes. A first step of forming a layer with the same thickness, and a second step of selecting a good LSI by performing an electrical test by bringing a probe of a measuring instrument into contact with a barrier metal layer on each of the electrodes. And a third step of forming solder bumps on each of the barrier metal layers of the selected good LSIs, respectively. 6. The semiconductor device according to claim 5, wherein, as the electrical test, an electrical test in a wafer state of the LSI, an electrical test in which individual pieces of the LSI are diced and a burn-in test are performed. Production method.