JP2001085596A - Stepped package - Google Patents

Stepped package

Info

Publication number
JP2001085596A
JP2001085596A JP25988199A JP25988199A JP2001085596A JP 2001085596 A JP2001085596 A JP 2001085596A JP 25988199 A JP25988199 A JP 25988199A JP 25988199 A JP25988199 A JP 25988199A JP 2001085596 A JP2001085596 A JP 2001085596A
Authority
JP
Japan
Prior art keywords
package
substrate
sealing
component
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25988199A
Other languages
Japanese (ja)
Inventor
Masao Saito
昌男 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Avionics Co Ltd
Original Assignee
Nippon Avionics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Avionics Co Ltd filed Critical Nippon Avionics Co Ltd
Priority to JP25988199A priority Critical patent/JP2001085596A/en
Publication of JP2001085596A publication Critical patent/JP2001085596A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To realize a mounting structure in which sealing can be carried out without being impeded by a soldered part requiring no sealing located contiguously to a sealed part and a heavy MCM package can stand impact when a heavy MCM package is operated. SOLUTION: When a package is designed, a step 1A is provided on the boundary of a region for mounting a soldered part 5 and a region to be bonded with a seal ring 2 and the upper end of the soldered part 5 requiring no sealing is set lower than a sealed part 11. A lead connecting pad is not provided on the lowermost layer of a substrate 1 but a step 1B is provided on the outer circumferential part on the bottom face of the substrate 1 substantially flush with the forward end part of the lead 4 so that the package can be bonded to the surface 13 of the substrate through adhesive 14.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はハイブリッドICや
マルチチップモジュール(以下、MCMという。)設
計、製造時の部品実装構造に係り、特に段差式パッケー
ジに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a component mounting structure at the time of designing and manufacturing a hybrid IC or a multi-chip module (hereinafter, referred to as MCM), and more particularly to a step type package.

【0002】[0002]

【従来の技術】従来、ハイブリッドICやMCMを設
計、製造する場合、サブストレートと呼ぶ基板上にIC
等ベアチップ部品および抵抗等チップ部品を搭載し、リ
ード線付き気密封止用パッケージに前記の部品搭載済み
サブストレートを搭載し、金線ボンディングにより結線
し、窒素ガス雰囲気中で気密封止する構造が一般的であ
った。しかしながら、近年の高密度高集積に対応するた
め、サブストレートとパッケージを一体化した構造も多
く使用されるようになってきた。前記一体型パッケージ
の気密封止方法は、予めシールリングをパッケージにロ
ー付けし、シールリングの上面およびシールキャップに
低融点シール材として例えば金めっきを施しておき、窒
素ガス雰囲気中においてシールリングにシールキャップ
を重ね、パラレルシーム溶接の一対のローラ電極を押
圧、水平移動しながらローラ電極間に電流を連続または
間欠的に通電することで低融点シール材である例えば金
の溶融により封止するものである。
2. Description of the Related Art Conventionally, when designing and manufacturing a hybrid IC or MCM, an IC is mounted on a substrate called a substrate.
A chip-mounted component such as a bare chip component and a resistor is mounted.The above-mentioned component-mounted substrate is mounted in a package for hermetic sealing with leads, connected by gold wire bonding, and hermetically sealed in a nitrogen gas atmosphere. Was common. However, in order to cope with recent high density and high integration, a structure in which a substrate and a package are integrated has been often used. The hermetic sealing method of the integrated package is such that a seal ring is previously brazed to the package, and the upper surface of the seal ring and the seal cap are subjected to, for example, gold plating as a low melting point sealant, and the seal ring is sealed in a nitrogen gas atmosphere. A seal cap is placed on top of a pair of parallel seam welded roller electrodes, and a current is continuously or intermittently applied between the roller electrodes while moving horizontally to seal by melting a low melting point sealing material such as gold. It is.

【0003】[0003]

【発明が解決しようとする課題】ここで、信頼性の高い
高密度実装MCMを設計するために、ベアチップ部品だ
けでなく気密封止済みのため封止不要のはんだ付け部品
をベアチップ部品と同一パッケージに混載する構造が望
ましい場合がある。図2はシールリング2取付け済みの
サブストレート一体型パッケージに、ベアチップ部品
6、抵抗等チップ部品7、はんだ付け部品5を搭載し、
シールキャップ10を載置して封止部11に前記パラレ
ルシーム溶接用ローラ電極12を重ねたところを図示し
たものである。しかしながら、図2に示すように、混載
したはんだ付け部品5が封止部11に近接していると、
前記電極12がはんだ付け部品5に当たり、封止作業が
できない場合がある。また、特に高密度実装MCMを設
計する場合、その回路規模からパッケージのサイズが大
きくかつ重くなることが多い。地上で設置型の装置に組
み込む場合は問題にならないが、航空機搭載等の衝撃、
重力加速度に耐えるにはパッケージリード4を基板のパ
ッド15に接続するだけでは重いMCMのパッケージを
支えることができない。
Here, in order to design a highly reliable, high-density mounting MCM, not only bare chip parts but also soldering parts which need not be sealed because they are hermetically sealed are in the same package as the bare chip parts. May be desirable. FIG. 2 shows the mounting of the bare chip component 6, the chip component 7 such as a resistor, and the soldering component 5 on the substrate integrated package with the seal ring 2 attached.
FIG. 3 shows a state where a seal cap 10 is placed and a roller electrode 12 for parallel seam welding is overlapped on a sealing portion 11. However, as shown in FIG. 2, when the mixed soldering component 5 is close to the sealing portion 11,
There is a case where the electrode 12 hits the soldering component 5 and sealing work cannot be performed. In particular, when designing a high-density mounting MCM, the package size is often large and heavy due to the circuit scale. This is not a problem when incorporating it into a device that is installed on the ground.
To withstand the gravitational acceleration, a heavy MCM package cannot be supported simply by connecting the package lead 4 to the pad 15 of the substrate.

【0004】本発明は、上記課題を解決するためになさ
れたもので、封止部に隣接した封止不要はんだ付け部品
に邪魔されることなく封止作業が行える実装構造の実現
および重いMCMのパッケージが装置運用時の衝撃等に
耐えられる搭載構造の実現を目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made to realize a mounting structure capable of performing a sealing operation without being disturbed by a sealing-unnecessary soldering component adjacent to a sealing portion, and to realize a heavy MCM. An object of the present invention is to realize a mounting structure in which a package can withstand a shock or the like during operation of the apparatus.

【0005】[0005]

【課題を解決するための手段】請求項1の段差式パッケ
ージは、要封止チップ部品と封止不要はんだ付け部品と
を同一のサブストレート一体型パッケージに実装する構
造のハイブリッドICやマルチチップモジュールにおい
て、サブストレートの部品実装面に段差を付けることで
要封止チップ部品実装領域より封止不要はんだ付け部品
実装領域の実装面を低くし、封止部高さより封止不要は
んだ付け部品上端高さが高くならないようにすることを
特徴とする。
A step-type package according to claim 1 is a hybrid IC or a multi-chip module having a structure in which a chip component requiring sealing and a soldering component not requiring sealing are mounted on the same substrate integrated package. In this case, the mounting surface of the solderless component mounting area that does not need to be sealed is made lower than the mounting area of the chip component that requires sealing by making a step on the component mounting surface of the substrate. It is characterized in that it does not become high.

【0006】請求項1の段差式パッケージによれば、封
止不要はんだ付け部品がパラレルシーム溶接用ローラ電
極の動きを妨げないため封止前に前記はんだ付け部品も
実装できるので、電気性能評価試験を実施し、該試験合
格品についてのみ封止作業を行うことができる。また、
前記同理由により、要封止チップ部品実装領域と封止不
要はんだ付け部品実装領域を近接して配置することを妨
げない。
According to the step-type package of the first aspect, since the soldering parts that do not require sealing do not hinder the movement of the roller electrode for parallel seam welding, the soldering parts can also be mounted before sealing, so that the electrical performance evaluation test can be performed. And sealing work can be performed only on the products that pass the test. Also,
For the same reason as above, it does not hinder that the sealing chip component mounting area and the sealing unnecessary soldering component mounting area are arranged close to each other.

【0007】請求項2の段差式パッケージは、サブスト
レート一体型パッケージに実装する構造のハイブリッド
ICやマルチチップモジュールにおいて、パッケージ底
面の外周リード接合部を底面より上部になるように段差
を付け、成形された前記リードの先端部と前記パッケー
ジ底面とが略同平面になることを特徴とする。
According to a second aspect of the present invention, in a hybrid IC or a multi-chip module structured to be mounted on a substrate-integrated package, a step is formed by forming a step so that the outer peripheral lead joint on the bottom of the package is higher than the bottom. The tip of the lead and the bottom surface of the package are substantially flush with each other.

【0008】請求項2の段差式パッケージによれば、ハ
イブリッドICやマルチチップモジュールを基板に実装
する際、底面を基板に接着できるので、航空機搭載機器
等の強い衝撃、大きな重力加速度に適合する。
According to the step-type package of the present invention, when the hybrid IC or the multi-chip module is mounted on the substrate, the bottom surface can be adhered to the substrate, so that it is suitable for strong impact and large gravitational acceleration of equipment mounted on an aircraft or the like.

【0009】[0009]

【発明の実施の形態】以下、本発明の実施形態を図1お
よび図2に基づいて説明する。図1は本発明の1実施形
態を示すMCMの側面模式図である。図1において1は
セラミック基材のサブストレートで、MCMがシステム
として機能するように多層配線構造によりボンディング
パッド、はんだ付けパッド、リード接続パッド間を結線
したものである。該サブストレート1の要封止部品(ベ
アチップ部品、抵抗等チップ部品)搭載領域の外周部に
沿ってコバール等の合金製シールリング2を該サブスト
レート1の表面金属箔上にロー付けし、絶縁リードタイ
バー付きリードフレーム3で保持されたリード4をリー
ド接続パッドに接合することで、サブストレート一体型
パッケージを完成させる。ここで、絶縁リードタイバー
付きリードフレーム3は、リードの切り離し無しに電気
性能評価試験ができるので、該試験時にリードの変形を
防止できる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic side view of an MCM showing one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a substrate of a ceramic base material, in which bonding pads, soldering pads, and lead connection pads are connected by a multilayer wiring structure so that the MCM functions as a system. An alloy seal ring 2 made of Kovar or the like is brazed onto the surface metal foil of the substrate 1 along the outer peripheral portion of the mounting area of the substrate 1 where necessary sealing components (bare chip components, chip components such as resistors) are mounted, and is insulated. By joining the leads 4 held by the lead frame 3 with lead tie bars to the lead connection pads, a substrate integrated package is completed. Here, the lead frame 3 with the insulated lead tie bar can perform an electrical performance evaluation test without disconnecting the leads, so that deformation of the leads during the test can be prevented.

【0010】前記一体型パッケージのはんだ付けパッド
にはんだ付け部品5をリフロー等で搭載し、要封止部品
搭載領域内の設計時所定の場所に半導体ベアチップ部品
6および抵抗、キャパシタ等チップ部品7を接着剤8に
より接着し、ボンディングワイヤ(金線)9によりボン
ディングパッド間を接続する。その後、製品としての電
気性能評価試験を実施し、仕様に合格後、窒素ガス雰囲
気中でシールキャップ10により気密封止を行う。
[0010] A soldering component 5 is mounted on the soldering pad of the integrated package by reflow or the like, and a semiconductor bare chip component 6 and a chip component 7 such as a resistor and a capacitor are placed at predetermined locations in a required mounting component mounting area. The bonding pads 8 are used for bonding, and the bonding pads (gold wires) 9 are used to connect the bonding pads. Thereafter, an electrical performance evaluation test as a product is performed, and after passing the specification, hermetic sealing is performed with the seal cap 10 in a nitrogen gas atmosphere.

【0011】前記気密封止は、シーム溶接部11にパラ
レルシーム用ローラ電極12を押圧しながら水平移動さ
せて行うが、図2に示すように、シーム溶接部11近傍
にシーム位置より高いはんだ付け部品5があると前記ロ
ーラ電極12の一部が該はんだ付け部品5にぶつかって
しまう。ぶつからないように該はんだ付け部品5をシー
ム溶接部11から離す設計では高密度設計が阻害されて
しまう。また、シーム溶接後に該はんだ付け部品5を取
りつける方法では、製品としての電気性能評価試験実施
前に封止することになり、封止内部の電気的調整が不可
能になるため現実的でない。そこで、図1に示すよう
に、パッケージ設計時に、サブストレートの上面の該は
んだ付け部品5実装領域とシールリング2接合領域を境
に段差1Aを設ける。段差1Aを設ける方法は、該はん
だ付け部品5実装領域のサブストレート表面層を第1層
から数えてN層目とする。ここでNは、1層当たりの厚
み、はんだ付け部品5高さとシールリング2高さの差を
考慮して、封止部11高さより封止不要はんだ付け部品
5上端高さが高くならないように決める。
The hermetic sealing is carried out by horizontally moving the roller electrode 12 for parallel seam while pressing it against the seam welding portion 11, but as shown in FIG. If there is a part 5, a part of the roller electrode 12 will hit the soldered part 5. In a design in which the soldered component 5 is separated from the seam welded portion 11 so as not to collide, a high-density design is hindered. Further, in the method of attaching the soldering component 5 after seam welding, the sealing is performed before the electric performance evaluation test is performed as a product, and it is not practical because electrical adjustment inside the sealing becomes impossible. Therefore, as shown in FIG. 1, a step 1A is provided at the time of designing the package, at the boundary between the soldering component 5 mounting region and the seal ring 2 joining region on the upper surface of the substrate. In the method of providing the step 1A, the substrate surface layer in the mounting area of the soldered component 5 is counted as the Nth layer from the first layer. Here, N is set so that the height of the upper end of the soldering component 5 that does not need to be sealed is not higher than the height of the sealing portion 11 in consideration of the thickness per layer and the difference between the height of the soldering component 5 and the height of the seal ring 2. Decide.

【0012】また、サブストレート一体型パッケージを
構成するために、リード4をサブストレート1のリード
接続パッド(図では省略)に接合するが、装置への搭載
後の熱ストレスに接続個所が耐える構造として、図2に
示すように、リード4を曲げた形状に成型したものを使
用する。しかしながら、航空機搭載等の衝撃、重力加速
度に耐えるには、装置への搭載時、基板のパッド15へ
のリード接続だけでは重いMCMのパッケージを支える
ことができない。そこで、図1に示すように、リード接
続パッドをサブストレート1の最下層ではなく、サブス
トレート1底面外周部に段差1Bを設け、中間層に該リ
ード接続パッド(図では省略)を形成する。前記サブス
トレート1底面外周部の段差1Bにより、パッケージ底
面とリード4の先端部を略同平面とすることでパッケー
ジを基板の表面13に接着剤14を用いて固着できる構
造にする。
Further, in order to form a package integrated with a substrate, the leads 4 are joined to lead connection pads (not shown) of the substrate 1, but the connection portions withstand thermal stress after mounting on the device. As shown in FIG. 2, a lead 4 formed into a bent shape is used. However, in order to withstand shocks and gravitational accelerations caused by mounting on an airplane or the like, a heavy MCM package cannot be supported only by connecting leads to the pads 15 of the substrate during mounting on an apparatus. Therefore, as shown in FIG. 1, the lead connection pad is not provided at the lowermost layer of the substrate 1, but a step 1B is provided on the outer peripheral portion of the bottom surface of the substrate 1, and the lead connection pad (not shown in the figure) is formed on the intermediate layer. The package 1 can be fixed to the surface 13 of the substrate using the adhesive 14 by making the package bottom surface and the tip of the lead 4 substantially flush with each other by the step 1B at the outer peripheral portion of the substrate 1 bottom surface.

【0013】[0013]

【発明の効果】本発明によれば、封止部11高さより封
止不要はんだ付け部品5上端高さが高くならず、シール
リング2とはんだ付け部品5を近接配置してもシーム溶
接時にはんだ付け部品5がパラレルシーム用ローラ電極
12の移動を妨げることがないので、ベアチップ部品と
封止不要はんだ付け部品の同一パッケージへの混載型ハ
イブリッドIC、MCMを高密度に設計、製造すること
ができる。また、パッケージのリード接続パッドを底面
より上層に設けることでリード先端部とパッケージ底部
を略同平面上にし、パッケージ底部を基板の表面に接着
した上でリードを基板のパッドに接続することができる
ので、該パッケージ搭載装置の対衝撃性、耐振動性が向
上する。従って、航空機搭載等に適合する、リード接続
だけでは耐えられないような大型で重いハイブリッドI
C、MCMの設計を可能にする。更に、パッケージ底部
を基板の表面に接着することで、放熱性の向上が得られ
る。
According to the present invention, the height of the upper end of the solderless part 5 which does not need to be sealed does not become higher than the height of the sealing part 11, and even if the seal ring 2 and the soldered part 5 are arranged close to each other, the soldering is not performed during seam welding. Since the mounting component 5 does not hinder the movement of the roller electrode 12 for parallel seam, it is possible to design and manufacture a hybrid IC and MCM in which a bare chip component and a soldering component that does not require sealing are mounted in the same package in a high density. . Further, by providing the lead connection pads of the package above the bottom surface, the tip of the lead and the bottom of the package can be made substantially coplanar, and the leads can be connected to the pads of the substrate after bonding the bottom of the package to the surface of the substrate. Therefore, the shock resistance and vibration resistance of the package mounting device are improved. Accordingly, a large and heavy hybrid I which is suitable for mounting on an airplane or the like and which cannot be tolerated only by lead connection.
C, enables MCM design. Further, by bonding the bottom of the package to the surface of the substrate, the heat dissipation can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1は本発明の1実施の形態を示す段差式パッ
ケージ構造MCMの側面模式図である。
FIG. 1 is a schematic side view of a step-type package structure MCM showing an embodiment of the present invention.

【図2】図2は段差のないパッケージ構造MCMの側面
模式図である。
FIG. 2 is a schematic side view of a package structure MCM having no steps.

【符号の説明】[Explanation of symbols]

1 サブストレート 1A サブストレート上面に設けた段差 1B サブストレート底面に設けた段差 2 シールリング 3 絶縁リードタイバー付きリードフレーム 4 リード 5 (封止不要)はんだ付け部品 5’はんだ付け部分 6 (要封止)半導体ベアチップ 7 (要封止)抵抗、キャパシタ等チップ部品 8 (チップ固定用)接着剤 9 ボンディングワイヤ(金線) 10 シールキャップ(封止用カバー) 11 シーム溶接部 12 パラレルシーム用ローラ電極 13 基板の表面 14 (パッケージ固定用)接着剤 15 基板のパッド DESCRIPTION OF SYMBOLS 1 Substrate 1A Step provided on the upper surface of substrate 1B Step provided at the bottom of substrate 2 Seal ring 3 Lead frame with insulated lead tie bar 4 Lead 5 (No sealing required) Solder parts 5 'Solder part 6 (Requires sealing) ) Semiconductor bare chip 7 (Seal required) Chip component such as resistor and capacitor 8 (Chip fixing) adhesive 9 Bonding wire (gold wire) 10 Seal cap (sealing cover) 11 Seam welded part 12 Roller electrode for parallel seam 13 Substrate surface 14 Adhesive (for fixing package) 15 Substrate pad

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 要封止チップ部品と封止不要はんだ付け
部品とを同一のサブストレート一体型パッケージに実装
する構造のハイブリッドICやマルチチップモジュール
において、サブストレートの部品実装面に段差を付ける
ことで要封止チップ部品実装領域より封止不要はんだ付
け部品実装領域の実装面を低くし、封止部高さより封止
不要はんだ付け部品上端高さが高くならないようにする
ことを特徴とする段差式パッケージ。
1. In a hybrid IC or a multi-chip module having a structure in which a chip component requiring sealing and a soldering component not requiring sealing are mounted on the same substrate integrated package, a step is formed on a component mounting surface of the substrate. A step characterized by lowering the mounting surface of the solderless component mounting area that does not require sealing than the mounting area of the chip component requiring sealing, so that the top height of the soldering component that does not need to seal does not become higher than the height of the sealing portion. Expression package.
【請求項2】 サブストレート一体型パッケージに実装
する構造のハイブリッドICやマルチチップモジュール
において、パッケージ底面の外周リード接合部を底面よ
り上部になるように段差を付け、成形された前記リード
の先端部と前記パッケージ底面とが略同平面になること
を特徴とする段差式パッケージ。
2. A hybrid IC or multi-chip module having a structure mounted on a substrate-integrated package, wherein a step is formed so that an outer peripheral lead joint on the bottom of the package is higher than the bottom, and a tip of the formed lead is formed. And a bottom surface of the package is substantially coplanar.
JP25988199A 1999-09-14 1999-09-14 Stepped package Pending JP2001085596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25988199A JP2001085596A (en) 1999-09-14 1999-09-14 Stepped package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25988199A JP2001085596A (en) 1999-09-14 1999-09-14 Stepped package

Publications (1)

Publication Number Publication Date
JP2001085596A true JP2001085596A (en) 2001-03-30

Family

ID=17340248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25988199A Pending JP2001085596A (en) 1999-09-14 1999-09-14 Stepped package

Country Status (1)

Country Link
JP (1) JP2001085596A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102837136A (en) * 2012-09-11 2012-12-26 陕西华经微电子股份有限公司 Parallel seam welding process and apparatus of special-shaped structure packaging housing
US9349694B2 (en) 2013-12-13 2016-05-24 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102837136A (en) * 2012-09-11 2012-12-26 陕西华经微电子股份有限公司 Parallel seam welding process and apparatus of special-shaped structure packaging housing
US9349694B2 (en) 2013-12-13 2016-05-24 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device

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