JP2001053606A - Pll synthesizer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily vary the output frequency of a PLL synthesizer circuit. SOLUTION: For frequency variation, a VCO(voltage-controlled oscillator) 6 is controlled by a control system of a subordinate charge pump circuit 13 and it is decided whether or not the difference between pieces of frequency division data before and after the variation is within a specific range. When the difference is not in the specific range, the time constant of a loop filter 5 is made small and the loop filter 5 is forcibly charged in a charge time Tc1 proportional to the difference between the frequency division data. If the difference is still not in the specific range, the difference between the frequency of the VCO 6 and the frequency division data is found and a charge time Tc2 is found from the difference and the last frequency variation quantity of the VCO 6 to charge the loop filter 5. Then the time constant of the loop filter 5 is made large after the frequency control over the VCO 6 is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synthesizer circuit suitable for use in an RDS radio receiver or the like which needs to switch a local oscillation frequency at high speed.

[0002]

2. Description of the Related Art Generally, in a radio receiver called an electronic tuner, a local oscillation signal is converted into a PL signal as shown in FIG.
It is generated from the L synthesizer circuit. The PLL synthesizer circuit is composed of a well-known PLL. Therefore, description of the normal operation of the PLL synthesizer circuit is omitted.

The operation of the PLL when the frequency of the local oscillation signal is changed in order to change the receiving broadcast station will be described. When the frequency division data is changed by the PLL control circuit constituted by the signal processing device, the frequency division number of the programmable divider 1 is changed, and the phase of this output is changed. In the phase comparison circuit 3, the phase of the reference signal and the output phase of the programmable divider are compared for each frequency of the reference signal, and an error signal is generated from the charge pump circuit 4 by the phase difference. The error signal is smoothed to a DC voltage by the loop filter 5 and becomes a control voltage of a VCO (voltage controlled oscillation circuit) 6.
The oscillation frequency of O6 changes. In this manner, the VCO 6 is repeatedly changed so that the output phase of the programmable divider 1 gradually approaches the phase of the reference signal.
Eventually, the two phases match, the PLL circuit is locked, and the oscillation frequency of the VCO is in accordance with the frequency-divided data.

[0004]

In the conventional PLL synthesizer circuit, when the output frequency is to be changed, the phase of the reference signal is compared with the output phase of the programmable divider 1, and an error signal corresponding to the comparison result is output. This operation is repeated several hundred times from the start of the frequency change to the lock of the PLL.
If the reference frequency is 50 KHz, V
Since it takes 20 μsec to change the oscillation frequency of CO,
From the start of the change until the PLL locks (20 μs
ec × several hundred times).

[0005] By the way, in European radio broadcasting,
2. Description of the Related Art Traffic information is multiplexed and transmitted on a normal broadcast. This broadcast is RDS (Radio Data S)
system), and a dedicated tuner is required to receive the RDS broadcast and obtain traffic information.
In such an RDS tuner, various functions using traffic information are added. For example, in the traffic information, there is data indicating whether or not the program is the same. If it is difficult for the currently receiving station to listen to the program, an alternative broadcast station is searched for and received using the data. In this function, an alternative broadcast station is constantly searched while listening to a receiving station to grasp the existence of the alternative broadcast station. In the search for alternative stations,
The frequency of the broadcasting station currently being listened to is quickly changed to the frequency of another broadcasting station, the RDS data of the alternative station and the reception state are checked, and then the operation quickly returns to the current receiving station.

However, in the PLL synthesizer circuit shown in FIG. 3, it takes a long time after the frequency is changed until the PLL is locked. Therefore, the time for changing the frequency to the alternative broadcasting station and the time for changing the frequency to the current broadcasting station are prolonged, and as a result, the current receiving station is interrupted and an unfavorable listening situation is created.

[0007]

According to the present invention, there is provided a PLL circuit for generating a frequency signal corresponding to input data, and a PLL circuit for generating a frequency signal corresponding to input data in accordance with a difference between an output frequency of the PLL circuit and a frequency corresponding to the input data. A frequency changing circuit for changing an output frequency, wherein a time constant of a loop filter in the PLL circuit is switched during control of the frequency changing circuit.

The time constant of the loop filter is switched to a first value after the control of the frequency changing circuit is completed, and is changed to a second value smaller than the first value during the control of the frequency changing circuit. It is characterized by the following.

The PLL circuit includes a voltage-controlled oscillation circuit whose oscillation frequency is controlled in accordance with a control signal, a reference signal generation circuit for generating a reference signal, and an oscillation signal of the voltage-controlled oscillation circuit according to input data. A programmable divider that divides the frequency by a frequency division number, a phase comparison circuit that compares phases of an output signal of the programmable divider and a reference signal, and a main charge pump circuit that outputs a ternary signal according to an output of the phase comparison circuit. A loop filter that generates a control signal of the voltage-controlled oscillation circuit in accordance with an output signal of the main charge pump circuit; and a sub-charge pump circuit that applies a charge to the loop filter in response to an output signal of the frequency change circuit. It is characterized by the following.

Further, the frequency changing circuit includes
A frequency counter for counting the output frequency of the L circuit;
A determining unit that determines whether the count value of the frequency counter and the frequency-divided data match or is within a predetermined range; and determining the PL based on the determination result of the determining unit.
A calculation unit for calculating a change amount of the output frequency of the L circuit, and applying an output signal to the sub charge pump circuit according to the change amount, wherein the control end signal is output according to the determination result of the determination unit. It is characterized by that.

According to the present invention, the charge application time is calculated according to the difference between the divided data to be changed and the divided data before the change or the oscillation frequency of the voltage control circuit counted by the frequency counter. The charge forcibly changes the oscillation frequency of the voltage controlled oscillation circuit. Further, since the time constant of the loop filter in the PLL is changed during and after the control, the oscillation frequency of the voltage controlled oscillation circuit can be quickly changed.

[0012]

FIG. 1 is a block diagram showing an embodiment of the present invention. The present invention includes a frequency changing circuit 9, and the frequency changing circuit 9 includes a frequency counter 10 for counting the frequency of the VCO 6, Determining unit 11 for determining whether the frequency obtained is within a predetermined range, and determining unit 11
And a calculation unit 12 for calculating the amount by which the output level of the loop filter 5 is changed according to the result of (1). Further, the PLL circuit 8 is provided with a sub charge pump circuit 13 that generates an error signal according to the output of the calculation unit 12.

A feature of the present invention resides in that the time constant of the loop filter 5 switches according to the control state of the frequency changing circuit 9.

In FIG. 1, the same circuits as those in the conventional example shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

First, the frequency changing operation of FIG. 1 will be described with reference to the flowchart of FIG. Data input circuit 7
When the frequency-divided data is transferred from the external control circuit, the data input circuit 7 first inputs the frequency-divided data only to the determination unit 11. In this step, input to the programmable divider 1 is prohibited (S1). The data input circuit 7 continues to wait for data until data is input.

The determining unit 11 receives the divided frequency data,
The difference from the frequency division data before the frequency division number change is calculated (S2), and it is determined whether the difference is within a predetermined range or outside the allowable range (S3). When it is determined that the difference between the divided data is within the predetermined range, the changing operation of the frequency changing circuit 9 is stopped, and the divided data held in the data input circuit 7 is input to the programmable divider 1. . Then, the frequency division number of the programmable divider 1 is changed, the oscillation frequency of the VCO 7 is changed so that the phase of the reference signal of the reference frequency generating circuit 2 matches the phase of the output signal of the programmable divider 1, and the PLL circuit 8 is locked. (S4).

If it is determined in step S3 that the difference between the frequency division numbers is outside the predetermined range, a reset signal is generated from the determination unit 11, and the programmable divider 1, the reference frequency generation circuit 2, and the phase comparison circuit 3 Is reset. In addition, a stop signal is generated from the determination unit 11, and the operation of the main charge pump circuit 4 is stopped. Further, although a control end signal is output from the determination unit 11, the control end signal is at the “L” level because the frequency changing circuit 9 is performing the control operation. Switching is performed in a direction in which the time constant of the loop filter 5 becomes smaller based on the control end signal at the “L” level. Accordingly, the control of the loop filter 5 can be quickly controlled.

Further, the calculation unit 12 is activated by the rise of the reset signal. The calculation unit 12 calculates the charge application time to the sub charge pump circuit 13 based on the difference between the frequency division data transferred from the determination unit 11. The first calculation after changing the frequency division number is performed such that a time proportional to the difference between the frequency division numbers is set as the charge application time. That is, the difference between the frequency division numbers is DD, and the charge application time is Tc1.
Then, Tc1 = α × DD, and the charging time Tc1 is calculated by this equation (S5).

When the charge application time Tc1 is calculated,
A charge control signal having a pulse width of time Tc1 is applied to sub charge pump circuit 13. In response, sub charge pump circuit 13 converts the pseudo error signal into loop filter 5.
Output to Due to such forced charging, the output potential of the loop filter 5 changes, and as a result, the oscillation frequency of the VCO 6 changes (S6).

At this time, since the time constant of the loop filter 5 has been switched to a small value, the output voltage of the loop filter 5 quickly becomes a constant level. As a result, the oscillation frequency of the VCO 6 also quickly converges to a constant frequency. And VCO6
Wait until the oscillation frequency of the
0 starts counting the oscillation frequency of the VCO 6 (S
7).

After the frequency counter finishes counting, the process returns to step S2. However, the first comparison operation after the frequency division change is to find the difference between the frequency division data to be changed and the frequency division data before the change. It is to find the difference between the value and the set frequency-divided data. Therefore, the determination unit 11 obtains the difference between the current oscillation frequency of the VCO 6 and the output frequency of the PLL circuit to be set, and determines whether the difference is within a predetermined range.

When the difference between the count value of the frequency counter and the set frequency-divided data is within a predetermined range, the reset signal is released, and the operation of the main charge pump circuit 4 is released to stop the operation of the PLL circuit 8. Lock by restarting. Further, since the control of the frequency changing circuit 9 has been completed, the control end signal is output at "H" level. As a result, the time constant of the loop filter 5 switches to a large value, and returns to the same time constant as the conventional example of FIG.
It contributes to convergence and maintenance of frequency and improvement of C / N characteristics.

On the other hand, when the difference between the count value of the frequency counter and the set frequency-divided data is out of the predetermined range, the charging time Tc2 (or Tc (N)) is calculated based on the difference. As described above, the first calculation after changing the frequency division number is that the time proportional to the frequency division difference is the charge application time Tc1 (or
Tc (N-1)), but in the second and subsequent calculations, the charge time Tc is calculated by the following formula.
2 is calculated. That is, assuming that the previously calculated charging time is Tc (N-1), the oscillation frequency changed by Tc (N-1) is ΔF, and the difference between the count value of the frequency counter and the set frequency dividing data is ΔDa,

[0024]

(Equation 1)

The calculation formula is as follows. According to this formula, the charging time is controlled according to the characteristics obtained by the previous frequency change, and the output frequency of the VCO 6 is controlled more accurately.

When the charge application time Tc2 is calculated,
A charge control signal having a pulse width of time Tc2 is applied to sub charge pump circuit 13. In response, sub charge pump circuit 13 converts the pseudo error signal into loop filter 5.
Output to Then, the output potential of the loop filter 5 changes, and as a result, the oscillation frequency of the VCO 6 changes. Then, after the oscillation frequency of the VCO 6 is stabilized, the frequency counter 10 counts the oscillation frequency of the VCO 6 again. After the count of the frequency counter is completed, the process returns to step S2 again.
Is repeated. During the control of the frequency changing circuit 9, the time constant of the loop filter 5 is switched so that its output voltage quickly becomes a constant level, so that the time until the frequency changing circuit 9 starts frequency counting can be shortened. Can be.

As described above, when changing the frequency, the charge time to the loop filter required for the frequency change can be accurately calculated from the result of the frequency change amount with respect to the previous charge time. Charge application can be performed several times. Therefore, the conventional P which requires several hundred circuits for charge application until the frequency is changed to the set frequency
Compared with the LL circuit, the PLL circuit of the present invention can reduce the time required for changing the frequency.

FIG. 4 is a diagram showing a specific circuit example of the loop filter 5 of FIG. 41 is an operational amplifier having an inverting input terminal, a non-inverting input terminal and an output terminal, 42 and 43 are capacitors and resistors connected in series in the negative feedback path of the operational amplifier 41, and 44 and 45 are transmission gates connected in parallel to the resistor 43 And a capacitor 46, a resistor connected between the inverting input terminal of the operational amplifier 41 and the main charge pump circuit 4; and 47, a resistor connected between the inverting input terminal of the operational amplifier 41 and the sub charge pump circuit 13. .

When the frequency change circuit 9 in FIG. 1 is under control and the control end signal is at “L” level, the transmission gate 44 is turned off, and the capacitor 45 is cut off from the loop filter 5. At this time, in order to increase the oscillation frequency of the VCO 6, an "L" level signal is input from the sub charge pump circuit 13 to the loop filter 5 as shown in FIG. Then, the output level of the loop filter 5 becomes the sum of the bias voltage proportional to the resistance ratio of the resistors 43 and 47 and the charging characteristics of the resistor 47 and the capacitor 42, and gradually increases as shown in FIG. Thereafter, when the output of the sub-charge pump circuit 13 stops and the state of the sub-charge pump circuit 13 becomes high impedance, the output of the loop filter 5 loses the bias voltage. The output of the loop filter 5 is increased by the amount charged in the capacitor 42 as compared with before the output of the sub charge pump circuit 13 is input. At this time, since the capacitor 45 is ignored, no potential difference occurs in the resistor 43, and the output level of the loop filter 5 quickly becomes constant.

When an "H" level signal is output from the sub charge pump circuit 13 as shown in FIG. 5A, the output level of the loop filter 5 becomes a bias voltage proportional to the resistance ratio of the resistors 43 and 47. , Resistor 47 and capacitor 4
5 and gradually decreases as shown in FIG. Thereafter, when the sub charge pump circuit 13 enters the high impedance state, the output of the loop filter 5 loses the amount of the bias voltage. Then, the output of the loop filter 5 is lowered by an amount corresponding to the discharge of the capacitor 42 as compared with before the output of the sub charge pump circuit 13 is input. At this time, since the capacitor 45 is ignored, no potential difference occurs in the resistor 43, and the output level of the loop filter 5 quickly becomes constant.

Next, when the control of the frequency changing circuit 9 of FIG. 1 is stopped and the control end signal is at the “H” level, the transmission gate 44 is turned on and the capacitor 45 is connected to the loop filter 5. At this time, in order to increase the oscillation frequency of the VCO 6, an "L" level signal is input from the sub charge pump circuit 13 to the loop filter 5 as shown in FIG. Then, the output level of the loop filter 5 becomes
The sum of the charging characteristics of the resistor 43 and the capacitor 45 and the charging characteristics of the resistor 47 and the capacitor 42 gradually increases as shown in FIG. As shown in FIG. 6A, the characteristic of the time constant of the capacitor 45 is remarkably exhibited. Thereafter, when the output of the sub charge pump circuit 13 enters a high impedance state,
The output of the loop filter 5 is higher than the output of the sub-charge pump circuit 13 by the amount charged in the capacitor 42, before the output of the sub charge pump circuit 13 is input. At this time, a potential difference is generated in the resistor 43 by the capacitor 45, the output level of the loop filter 5 becomes a discharge characteristic of the resistor 43 and the capacitor 45, and the output level of the loop filter 5 gradually decreases.

When an "H" level signal is output from the sub charge pump circuit 13 as shown in FIG. 6A, the output level of the loop
5 and the discharge characteristics of the resistor 47 and the capacitor 42, and gradually decrease as shown in FIG. Thereafter, when the sub charge pump circuit 13 enters a high impedance state, the output of the loop filter 5 becomes smaller than that of the capacitor 4 before the output of the sub charge pump circuit 13 is input.
2 has dropped by the amount discharged. At this time, a potential difference is generated in the resistor 43 by the capacitor 45, the output level of the loop filter 5 becomes a charging characteristic of the resistor 43 and the capacitor 45, and the output level of the loop filter 5 gradually increases.

According to FIGS. 5 and 6, the output of the loop filter 5 can be quickly made constant by cutting off the capacitor 45 from the loop filter 5.

[0034]

According to the present invention, since the frequency of the PLL can be changed in a short time, the receiving station can be changed in the radio receiver in a short time. In particular, when searching for an alternative broadcast station in the RDS radio receiver, it is possible to quickly change to the alternative broadcast station, so that it is possible to prevent a sense of incongruity in hearing.

In particular, during the control of the frequency changing circuit, the time constant of the loop filter is reduced so that there is no waiting time until the frequency changing circuit starts frequency measurement, thereby shortening the frequency control time. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of FIG.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a circuit diagram showing a specific circuit example of the loop filter 5 of FIG.

FIG. 5 is a characteristic diagram showing input / output characteristics of the loop filter 5 when the time constant is small.

FIG. 6 is a characteristic diagram showing input / output characteristics of the loop filter 5 when the time constant is large.

[Explanation of symbols]

 9 Frequency change circuit 10 Frequency counter 11 Judgment unit 12 Calculation unit 13 Sub charge pump circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J103 AA11 BA02 CB04 DA05 DA16 DA19 DA20 DA31 DA38 FA05 GA07 GA11 GB03 HC06 5J106 AA04 BB04 CC01 CC15 CC33 CC41 CC53 DD17 DD32 EE09 GG07 GG09 GG15 HH08 HH10 KK03 PP03 QQ09 RR

Claims (4)

[Claims] 1. A PLL circuit for generating a frequency signal corresponding to input data, and a frequency changing circuit for changing an output frequency of the PLL circuit according to a difference between an output frequency of the PLL circuit and a frequency corresponding to the input data. Wherein the time constant of a loop filter in the PLL circuit is switched during the control of the frequency changing circuit.
L synthesizer circuit. 2. The time constant of the loop filter is switched to a first value after the control of the frequency changing circuit is completed, and a second constant smaller than the first value is controlled during the control of the frequency changing circuit.
2. The PLL synthesizer circuit according to claim 1, wherein the value of the PLL synthesizer is switched. 3. The PLL circuit includes: a voltage-controlled oscillation circuit whose oscillation frequency is controlled according to a control signal; a reference signal generation circuit that generates a reference signal; and an oscillation signal of the voltage-controlled oscillation circuit as input data. A programmable divider that divides the frequency by an appropriate frequency division number, a phase comparison circuit that compares the phase of an output signal of the programmable divider and a phase of a reference signal, and a main charge pump that outputs a ternary signal according to the output of the phase comparison circuit Circuit, the loop filter for generating a control signal of the voltage controlled oscillation circuit in accordance with an output signal of the main charge pump circuit, and a sub charge pump circuit for applying a charge to the loop filter in accordance with an output signal of the frequency changing circuit 2. The PLL synthesizer circuit according to claim 1, further comprising: 4. The frequency changing circuit, comprising: a frequency counter for counting an output frequency of the PLL circuit; and whether or not the count value of the frequency counter and the frequency-divided data match, or whether or not the frequency data is within a predetermined range. A determination unit for determining whether the output frequency of the PLL circuit is changed based on the determination result of the determination unit; and a calculation unit for applying an output signal to the sub charge pump circuit in accordance with the change amount. 2. The PLL synthesizer circuit according to claim 1, wherein the control end signal is output according to a determination result of the determination unit.