JP2009177259A - Pll circuit, radio terminal device and frequency detection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new and improved PLL circuit detecting the minimum oscillation frequency of a DCO (digital controlled oscillator) and highly accurately converting the control data proportional to a division ratio N into the control data of the DCO. <P>SOLUTION: Provided is the PLL circuit having an oscillation circuit to be controlled by use of a digital value. The PLL circuit includes: a carrier frequency setting section for setting a carrier frequency value; a detecting section for detecting that a carrier frequency value has changed; and a measuring section for transmitting a control signal for causing the oscillation circuit to oscillate at the minimum frequency synchronously with a signal indicating that the carrier frequency value has changed, and for measuring the number of output clocks of the oscillation circuit in one cycle of a reference frequency. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a PLL circuit, a wireless terminal device, and a frequency detection method, and more particularly, to a PLL circuit, a wireless terminal device, and a frequency detection method that convert control data of a digitally controlled oscillator used in a digital control PLL circuit. .

  The wireless communication terminal has a PLL (Phase Locked Loop) circuit to lock the carrier frequency to an accurate frequency. In recent years, with the miniaturization of semiconductor processes, a configuration in which a voltage controlled oscillator (VCO) controlled by an analog voltage is replaced with a digitally controlled oscillator (DCO) is drawing attention.

  In a conventional PLL circuit using a VCO, the phase difference between a reference clock and a clock obtained by dividing the VCO output is compared using a phase comparator. Here, as a general phase comparator, a circuit that converts the phase difference into three-state pulse widths of up, down, and up + down is used, and the current source of the charge pump circuit is controlled using this pulse. Then, the output current is converted into a voltage by a loop filter to control the VCO.

  On the other hand, as shown in FIG. 10 (RBStaszewski et al., “All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13um CMOS, ISSCC2004 Digest), DCO, which has been attracting attention in recent years, was used. In the example of an ADPLL (All-Digital PLL) circuit, a fractional component of a time difference corresponding to a phase difference is converted into a digital value by a time-to-digital converter (TDC) circuit, and an integrator component is converted into a digital value by an accumulator circuit. The digital value corresponding to the phase difference is fed back by various methods to control the DCO digitally.

R.B.Staszewski et al., “All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13um CMOS, ISSCC2004 Digest

  FIG. 7 is an explanatory diagram showing a conventional PLL circuit 10. As shown in FIG. 7, the conventional PLL circuit 10 includes a phase comparator 11, a variable gain amplifier circuit 12, a multiplier 13, and an oscillator 14.

As shown in FIG. 7, the relationship between the frequency division ratio N obtained by dividing the oscillation frequency f by the reference frequency Ref_freq and the oscillation frequency f is as shown in the graph (1) of FIG. Become. Here, as a characteristic of the oscillation circuit, as shown in the graph (2) of FIG. 7, if the relationship between the digital control data D and the oscillation frequency f is a linear curve that passes through the origin and has a slope of k _DCO. The conversion from the frequency division ratio N to the control data D can be realized by multiplying by a coefficient α (= Ref_freq / k _DCO ).

On the other hand, a DCO used for a digital PLL generally has a configuration in which a plurality of variable capacitors arranged as a tank circuit capacitor are controlled by switching with a digital signal. Therefore, the DCO oscillates at the lowest frequency with all the switches turned on and all the capacitors added. That is, as shown in FIG. 8, the relationship between the control data D and the oscillation frequency is such that the Y intercept is the minimum oscillation frequency f _min and the slope is k _DCO as shown in the graph (2) of FIG. A curve can be approximated. In this case, conversion from the frequency division ratio N to the control data D is difficult by simply multiplying by a certain coefficient α ′, and means for at least knowing the minimum oscillation frequency f _min is required.

As shown in FIG. 9, when the control data is D, the minimum variable capacitance value is ΔC, the capacitance value of the variable capacitance when all the switches are turned on is C _max , and the inductance value is L, the oscillation frequency f is This is expressed by Equation 1.

However, in a region where the value of D · ΔC is sufficiently small with respect to C _max , it can be approximated to a linear curve with the Y intercept as f _min , but as shown in the graph (2) in FIG. As the value increases, the error increases, and this error becomes a problem particularly when frequency modulation is directly applied to the DCO.

  Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to acquire the minimum oscillation frequency of the DCO and to be proportional to the frequency division ratio N using the acquired minimum oscillation frequency. It is an object of the present invention to provide a new and improved PLL circuit, wireless terminal device, and frequency detection method capable of accurately converting control data into DCO control data.

  In order to solve the above problems, according to an aspect of the present invention, a PLL (Phase Locked Loop) circuit having an oscillation circuit controlled using a digital value, the carrier frequency holding unit holding a carrier frequency value And a detection unit that detects that the carrier frequency value has changed from the value held by the carrier frequency holding unit, and the oscillation circuit that oscillates at the lowest frequency in synchronization with the change in the carrier frequency value detected by the detection unit. And a measurement unit that measures the number of output clocks of the oscillation circuit within one cycle of the reference frequency. The PLL circuit is provided.

  According to such a configuration, the carrier frequency holding unit holds the value of the carrier frequency in the PLL circuit, and the detection unit detects that the carrier frequency value has changed from the value held by the carrier frequency holding unit. The measurement unit transmits a control signal for causing the oscillation circuit to oscillate at the lowest frequency in synchronization with the change in the carrier frequency value detected by the detection unit, and the number of output clocks of the oscillation circuit within one cycle of the reference frequency Measure. As a result, in the PLL circuit, in synchronization with the change of the set value of the carrier frequency, control data for oscillating the lowest frequency is transmitted to the oscillation circuit, and the number of clocks of the oscillation circuit output within one cycle of the reference frequency is set. By measuring, the minimum oscillation frequency value can be detected as one of the calibration functions.

  In order to solve the above problem, according to another aspect of the present invention, a PLL circuit having an oscillation circuit controlled using a digital value, the carrier frequency holding unit holding the carrier frequency value, A detection unit for detecting that the carrier frequency value has changed from the value held by the carrier frequency holding unit, and a control for causing the oscillation circuit to oscillate at the lowest frequency in synchronization with the change in the carrier frequency value detected by the detection unit. A first measurement unit that transmits a signal and measures the number of clocks of the reference frequency, a setting unit that sets the number of clocks of the reference frequency that is measured by the first measurement unit, and the number of clocks that is measured by the first measurement unit Measured by a second measurement unit that measures the number of output clocks of the oscillation circuit within the reference frequency period equivalent to the second measurement unit within the reference frequency period equivalent to the number of clocks measured by the first measurement unit Oscillator circuit The number of output clock, and averaging unit for averaging in the number of clocks measured by the first measuring unit, characterized in that it comprises a, PLL circuit is provided.

  According to such a configuration, the carrier frequency holding unit holds the value of the carrier frequency in the PLL circuit, and the detection unit detects that the carrier frequency value has changed from the value held by the carrier frequency holding unit. The first measurement unit transmits a control signal for causing the oscillation circuit to oscillate at the lowest frequency in synchronization with the change in the carrier frequency value detected by the detection unit, measures the number of clocks of the reference frequency, and second The setting unit sets the number of clocks of the reference frequency measured by the first measuring unit, and sets the number of output clocks of the oscillation circuit within the reference frequency period equivalent to the number of clocks measured by the first measuring unit. The measurement unit averages the measurement value of the second measurement unit with the measurement value measured by the first measurement unit. As a result, in the PLL circuit, in synchronization with the change of the set value of the carrier frequency, control data for oscillating the lowest frequency is transmitted to the oscillation circuit, and the number of clocks of the oscillation circuit output within one cycle of the reference frequency is set. By measuring, the minimum oscillation frequency value can be detected as one of the calibration functions. Further, by taking a long measurement time and calculating an average value of the number of clocks per cycle, the minimum oscillation frequency value can be detected with higher accuracy.

  In order to solve the above-described problem, according to another aspect of the present invention, a PLL circuit having an oscillation circuit controlled using a digital value, wherein a minimum frequency value is measured or input. And a subtractor for subtracting the value obtained by dividing the minimum frequency value by the reference frequency value from the control data proportional to the frequency division ratio, and a multiplier for multiplying the coefficient corresponding to the value obtained by dividing the reference frequency value by the conversion gain of the oscillation circuit. And a PLL circuit characterized in that the output of the multiplier is used as a control signal for the oscillation circuit.

  As a result, in the PLL circuit, the conversion to the control data of the oscillation circuit having the characteristic that the minimum oscillation frequency value does not become 0 Hz can be approximated to a linear curve.

  The PLL circuit may perform frequency modulation directly on the oscillation circuit. As a result, direct frequency modulation can be performed in the PLL circuit.

  In order to solve the above problem, according to another aspect of the present invention, there is provided a PLL circuit having an oscillation circuit controlled using a digital value, wherein the minimum in the PLL circuit according to claim 1 or 2 is provided. The lowest frequency measurement unit that measures the frequency value, the subtraction unit that subtracts the value obtained by dividing the lowest frequency value by the reference frequency value from the control data proportional to the division ratio, and the reference frequency value divided by the conversion gain of the oscillation circuit And a multiplier that multiplies a coefficient corresponding to the value, and an output of the multiplier is used as a control signal of the oscillation circuit.

  As a result, in the PLL circuit, the conversion to the control data of the oscillation circuit having the characteristic that the minimum oscillation frequency value does not become 0 Hz can be approximated to a linear curve. In addition, in the PLL circuit, in synchronization with the change of the set value of the carrier frequency, control data for oscillating the minimum frequency is transmitted to the oscillation circuit, and the number of clocks of the oscillation circuit output within one cycle of the reference frequency is measured. By doing so, the lowest oscillation frequency value can be detected as one of the calibration functions.

  The PLL circuit may perform frequency modulation directly on the oscillation circuit. As a result, direct frequency modulation can be performed in the PLL circuit.

  In order to solve the above-mentioned problem, according to another aspect of the present invention, a PLL circuit having an oscillation circuit controlled using a digital value, wherein a minimum frequency value is measured or input. From the lowest frequency value and the carrier wave frequency value, a calculation unit for calculating the frequency value corresponding to the Y intercept when the relationship between the control data and the frequency is approximated to a linear curve, and the control data proportional to the frequency division ratio A subtractor for subtracting a value obtained by dividing the frequency value corresponding to the Y intercept by the reference frequency value; and a multiplier for multiplying a coefficient corresponding to a value obtained by dividing the reference frequency value by the conversion gain of the oscillation circuit. Is used as the control signal of the oscillation circuit. A PLL circuit is provided.

  As a result, the PLL circuit has a predetermined slope even in a region where the change in the slope of the oscillation frequency with respect to the control data of the oscillation circuit cannot be ignored when approximating to the linear curve in the conversion to the control data of the oscillation circuit. It can be approximated to a linear curve.

  The PLL circuit may perform frequency modulation directly on the oscillation circuit. As a result, direct frequency modulation can be performed in the PLL circuit.

  In order to solve the above problem, according to another aspect of the present invention, there is provided a PLL circuit having an oscillation circuit controlled using a digital value, wherein the minimum in the PLL circuit according to claim 1 or 2 is provided. A minimum frequency measurement unit that measures a frequency value, a calculation unit that calculates a frequency value corresponding to a Y-intercept when approximating the relationship between control data and frequency to a linear curve from the minimum frequency value and the carrier frequency value; The control data proportional to the frequency division ratio is multiplied by a subtracting unit for subtracting a value obtained by dividing the frequency value corresponding to the Y intercept by the reference frequency value, and a coefficient corresponding to the value obtained by dividing the reference frequency value by the conversion gain of the oscillation circuit. A PLL circuit is provided, characterized in that the output of the multiplier is used as a control signal for the oscillation circuit.

  As a result, the PLL circuit has a predetermined slope even in a region where the change in the slope of the oscillation frequency with respect to the control data of the oscillation circuit cannot be ignored when approximating to the linear curve in the conversion to the control data of the oscillation circuit. It can be approximated to a linear curve. In addition, in the PLL circuit, in synchronization with the change of the set value of the carrier frequency, control data for oscillating the minimum frequency is transmitted to the oscillation circuit, and the number of clocks of the oscillation circuit output within one cycle of the reference frequency is measured. By doing so, the lowest oscillation frequency value can be detected as one of the calibration functions.

  The PLL circuit may perform frequency modulation directly on the oscillation circuit. As a result, direct frequency modulation can be performed in the PLL circuit.

  In order to solve the above problem, according to another aspect of the present invention, there is provided a wireless terminal device including the PLL circuit described above. As a result, it is possible to provide a wireless terminal device having the effect of the PLL circuit described above.

  In order to solve the above problem, according to another aspect of the present invention, there is provided a frequency detection method in a PLL circuit having an oscillation circuit controlled using a digital value, the carrier frequency holding a carrier frequency value. The holding step, the detection step for detecting that the carrier frequency value has changed from the value held in the carrier frequency holding step, and the oscillation circuit oscillates at the lowest frequency in synchronization with the change in the carrier frequency value detected in the detection step. And a measurement step of measuring a number of output clocks of the oscillation circuit within one cycle of the reference frequency.

  As a result, in the frequency detection method in the PLL circuit, in synchronization with the change of the set value of the carrier frequency, control data for oscillating the minimum frequency is transmitted to the oscillation circuit, and the oscillation circuit output within one cycle of the reference frequency By measuring the number of clocks, the minimum oscillation frequency value can be detected as one of the calibration functions.

  In order to solve the above problem, according to another aspect of the present invention, there is provided a frequency detection method in a PLL circuit having an oscillation circuit controlled using a digital value, the carrier frequency holding a carrier frequency value. The holding step, the detection step for detecting that the carrier frequency value has changed from the value held in the carrier frequency holding step, and the oscillation circuit oscillates at the lowest frequency in synchronization with the change in the carrier frequency value detected in the detection step. A first measurement step for transmitting a control signal for measuring the number of clocks of a reference frequency, a setting step for setting the number of clocks of a reference frequency measured in the first measurement step, and a first measurement step A second measuring step for measuring the number of output clocks of the oscillation circuit within a reference frequency period equivalent to the measured number of clocks; An averaging step for averaging the number of output clocks of the oscillation circuit measured in the second measurement step within the reference frequency period equivalent to the number of clocks measured in step 1 with the number of clocks measured in the first measurement step; A frequency detection method is provided.

  As a result, in the frequency detection method in the PLL circuit, in synchronization with the change of the set value of the carrier frequency, control data for oscillating the minimum frequency is transmitted to the oscillation circuit, and the oscillation circuit output within one cycle of the reference frequency By measuring the number of clocks, the minimum oscillation frequency value can be detected as one of the calibration functions. Further, by taking a long measurement time and calculating an average value of the number of clocks per cycle, the minimum oscillation frequency value can be detected with higher accuracy.

  As described above, according to the present invention, the minimum oscillation frequency of the DCO is acquired, and the control data proportional to the frequency division ratio N is accurately converted to the control data of the DCO using the acquired minimum oscillation frequency. It is possible to provide a novel and improved PLL circuit, wireless terminal device, and frequency detection method that can be used.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

(First embodiment)
First, the PLL circuit according to the first embodiment of the present invention will be described. FIG. 1 is an explanatory diagram illustrating a PLL circuit 100 according to the first embodiment of the present invention. Hereinafter, the configuration of the PLL circuit 100 according to the first embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, the PLL circuit 100 according to the first embodiment of the present invention includes a first flip-flop 101, a first comparison circuit 102, an oscillator 103, a reference frequency oscillator 104, 1 cumulative adder 105, second cumulative adder 106, second comparison circuit 107, second flip-flop 108, first switch 109, and second switch 110. Composed.

  The first flip-flop 101 is a D-type flip-flop capable of holding the previous input value, and holds and outputs the set value of the frequency division ratio one clock before the reference frequency oscillator 104. An output from the first flip-flop 101 is input to the first comparison circuit 102.

  The first comparison circuit 102 compares the set value of the division ratio one clock before the reference frequency oscillator 104 output from the first flip-flop 101 and the current set value of the division ratio (PLL setting data). To do. If they match, a LOW level signal is output, and if they are different, a HIGH level signal is output.

  The oscillator 103 outputs a clock signal that oscillates at a predetermined frequency. In the present embodiment, the oscillation frequency is determined by the control data D that is selectively output by the first switch 109.

  The reference frequency oscillator 104 outputs a clock signal having a reference frequency Ref_freq. A signal output from the reference frequency oscillator 104 is input to the first flip-flop 101 and the second switch 110.

  The first cumulative adder 105 performs cumulative addition of the number of output clocks of the oscillator 103 using the rising edge of the output clock of the oscillator 103 as a trigger. The value cumulatively added by the first cumulative adder 105 is reset during a period in which the output of the first comparison circuit 102 is a HIGH level signal, and after the transition to a period in which the output is a LOW level signal, cumulative addition is started. The The number of output clocks of the oscillator 103 cumulatively added by the first cumulative adder 105 is input to the second flip-flop 108.

  The second cumulative adder 106 performs cumulative addition of the number of output clocks of the reference frequency oscillator 104 using the rising edge of the output clock of the reference frequency oscillator 104 as a trigger. Similar to the first cumulative adder 105, the value cumulatively added by the second cumulative adder 106 is reset during a period when the output of the first comparison circuit 102 is a HIGH level signal, and is a LOW level signal. Cumulative addition is started after transition to a certain period. The number of output clocks of the reference frequency oscillator 104 cumulatively added by the second cumulative adder 106 is input to the second comparison circuit 107.

  The second comparison circuit 107 outputs a comparison result between the output of the second cumulative adder 106 and the value “1”. When the output of the second cumulative adder 106 becomes equal to 1, the second comparison circuit 107 outputs a HIGH level signal, and if not, outputs a LOW level signal. The output of the second comparison circuit 107 is input to the second flip-flop 108, the first switch 109, and the second switch 110.

The second flip-flop 108 is a D-type flip-flop capable of holding the previous input value, like the first flip-flop 101, and is the first flip-flop “1” after the output clock of the reference frequency oscillator 104. The cumulative added value of the cumulative adder 105 is held and output. The output from the second flip-flop 108 can obtain the number of clocks within one cycle of the reference frequency, that is, a value obtained by dividing f _min by the reference frequency Ref_freq. The principle will be described in detail later.

  The first switch 109 selectively switches control data supplied to the oscillator 103. The switching of the first switch 109 is performed by an output signal from the second comparison circuit 107. During the period when the output of the second comparison circuit 107 is at the LOW level, the control data D is D = 0, that is, the lowest oscillation frequency is set. It is connected to a control signal to be oscillated, and is connected to a control signal D in a state in which the PLL loop is closed during a HIGH level period.

  The second switch 110 selectively switches the signal supplied to the second cumulative adder 106. Similar to the first switch 109, the second switch 110 is switched by an output signal from the second comparison circuit 107. During the period when the output of the second comparison circuit 107 is at the LOW level, the reference frequency oscillator 104 is connected to a potential that pulls down to a LOW level such as GND during a HIGH level period.

  The configuration of the PLL circuit 100 according to the first embodiment of the present invention has been described above. Next, the operation of the PLL circuit 100 according to the first embodiment of the present invention will be described.

  To change the carrier frequency to be locked, the set value of the frequency division ratio is changed. Therefore, the first flip-flop 101 is used to hold the setting value of the frequency division ratio one clock before the reference frequency oscillator 104.

  Here, when the set value of the division ratio changes, a change in the set value of the division ratio is detected in the first comparison circuit 102, and a HIGH level signal indicating that the division ratio has changed is a first level signal. Output from the comparison circuit 102. The period during which the HIGH level signal is output is one clock of the reference frequency at which the reference frequency oscillator 104 oscillates.

When the HIGH level signal output from the first comparison circuit 102 is input to the first cumulative adder 105, the first cumulative adder 105 resets the value accumulated so far. When a LOW level signal is input to the first cumulative adder 105 after one clock of the reference frequency, the first cumulative adder 105 starts cumulative addition of the number of output clocks of the oscillator 103. Here, the oscillator 103 oscillates at the minimum oscillation frequency f _min because the output of the second comparison circuit 107 is at the LOW level and is connected to the control signal for transmitting the minimum oscillation frequency by the first switch 109. It is in the state.

  When the HIGH level signal output from the first comparison circuit 102 is input to the second cumulative adder 106, the second cumulative adder 106 resets the value accumulated so far. . When a LOW level signal is input to the second cumulative adder 106 one clock after the reference frequency, the second cumulative adder 106 starts cumulative addition of the number of clocks of the reference frequency oscillator 104.

  The second comparison circuit 107 outputs a HIGH level signal when the two inputs are equal. That is, the second comparison circuit 107 outputs a HIGH level signal when the output of the second cumulative adder 106 becomes “1”. That is, the second comparison circuit 107 outputs a HIGH level signal after “1” clocks of the reference frequency oscillated by the reference frequency oscillator 104 after the cumulative addition is started.

The second flip-flop 108 uses the rising edge of the output signal of the second comparison circuit 107 as a trigger. Since the second flip-flop 108 is connected to the output of the first cumulative adder 105, the second flip-flop 108 holds the cumulative added value of the first cumulative adder 105 after “1” clock of the reference frequency. Then, the second flip-flop 108 outputs a cumulative added value of the first cumulative adder 105 within one cycle of the reference frequency, that is, a value obtained by dividing the minimum oscillation frequency f _min by the reference frequency Ref_freq.

When the measurement of the value obtained by dividing the minimum oscillation frequency f _min by the reference frequency Ref_freq is completed, the output signal of the second comparison circuit 107 is held at the HIGH level.

The operation of the PLL circuit 100 according to the first embodiment of the present invention has been described above. As described above, according to the first embodiment of the present invention, the oscillator is controlled to oscillate at the lowest frequency in synchronization with the change in the set value of the frequency division ratio, and the oscillator within one cycle of the reference frequency By counting the number of clocks, it is possible to know the value of the minimum oscillation frequency _fmin . Note that the circuit configuration illustrated in FIG. 1 is an example, and it is needless to say that the same processing can be configured with different circuit configurations.

(Second Embodiment)
FIG. 2 is an explanatory diagram illustrating a PLL circuit 200 according to the second embodiment of the present invention. The configuration of the PLL circuit 200 according to the second embodiment of the present invention will be described below using FIG.

  As shown in FIG. 2, the PLL circuit 200 according to the second embodiment of the present invention includes a first flip-flop 201, a first comparison circuit 202, an oscillator 203, a reference frequency oscillator 204, 1 cumulative adder 205, second cumulative adder 206, second comparison circuit 207, second flip-flop 208, first switch 209, second switch 210, and divider 211 And comprising. Among these, the second comparison circuit 207 and the divider 211 are different from the PLL circuit 100 according to the first embodiment of the present invention. Therefore, here, the second comparison circuit 207 and the divider 211 will be described.

  The second comparison circuit 207 outputs a HIGH level signal when the two inputs are equal. In the first embodiment of the present invention, the second comparison circuit 107 outputs a HIGH level signal when the output of the second cumulative adder 106 is equal to “1”. When the output of the cumulative adder 206 is equal to the predetermined count value N, a HIGH level signal is output. The predetermined count value is a natural number, and an arbitrary value can be set as the count value N. The value of N is desirably 2 or more.

The divider 211 divides the output of the second flip-flop 208 by a predetermined count value N and outputs the result. By setting the count value N to 2 ^m (m is a natural number), the divider 211 can be simplified to bit shift m times.

That is, in the first embodiment of the present invention, the first cumulative adder 105 counts the number of clocks of the oscillator 103 that oscillates at the minimum oscillation frequency f _min within one cycle of the reference frequency, thereby reducing the minimum oscillation frequency. Although f _min has been obtained, in the second embodiment of the present invention, the first cumulative adder 205 counts the number of clocks of the oscillator 203 that oscillates at the minimum oscillation frequency f _min within the reference frequency N period. . Then, the cumulative added value output from the first cumulative adder 205 is divided by a predetermined count value N in the divider 211 to obtain a value obtained by dividing the minimum oscillation frequency f _min by the reference frequency Ref_freq.

The configuration of the PLL circuit 200 according to the second embodiment of the present invention has been described above. As described above, in the second embodiment of the present invention, the number of clocks of the oscillator 203 that oscillates at the minimum oscillation frequency f _min is counted over a longer period than in the first embodiment, and the counted value is calculated. Since the division is performed by the predetermined count value N, a more accurate minimum oscillation frequency f _min can be obtained. Note that the circuit configuration illustrated in FIG. 2 is an example, and it is needless to say that the same processing can be configured with different circuit configurations.

(Third embodiment)
FIG. 3 is an explanatory diagram illustrating the configuration of a PLL circuit 300 according to the third embodiment of the present invention. The configuration of the PLL circuit 300 according to the third embodiment of the present invention will be described below using FIG.

  As shown in FIG. 3, a PLL circuit 300 according to the third embodiment of the present invention includes a phase comparator 301, a variable gain amplifier circuit 302, a subtractor 304, a multiplier 306, an oscillator 307, It is comprised including.

  The phase comparator 301 receives a signal of a reference frequency Ref_freq output from a reference frequency oscillator (not shown) and a signal of an oscillation frequency RF OUT output from the oscillator 307, compares the phases of both, and outputs the result. It is. The phase comparison processing in the phase comparator 301 is performed by subtracting the division ratio converted into a digital value and the digital value of each cumulative addition value of the number of clocks indicated by the decimal point of the oscillation frequency in each cycle of the reference frequency signal. It is done as a process.

  The variable gain amplifier circuit 302 controls the loop gain of the PLL circuit 300, and generates control data proportional to the frequency division ratio N by inputting and amplifying the output of the phase comparator 301. .

The subtractor 304 subtracts a value obtained by dividing the minimum oscillation frequency f _min of the oscillator 307 by the reference frequency Ref_freq from the control data proportional to the frequency division ratio N, and outputs the result.

The multiplier 306 multiplies the output of the subtracter 304 by a conversion coefficient α ′ (α ′ = D / N ′ = Ref_freq / k _dco ) and outputs the result. By multiplying the output of the subtractor 304 by the conversion coefficient α ′, it can be used as the control data D of the oscillator 307.

  The oscillator 307 outputs a signal RF OUT that oscillates at a predetermined oscillation frequency. In the PLL circuit 300 shown in FIG. 3, a signal RF OUT that oscillates at a predetermined oscillation frequency is output by the control data D output by the calculation in the multiplier 306.

  The configuration of the PLL circuit 300 according to the third embodiment of the present invention has been described above. Next, the operation of the PLL circuit 300 according to the third embodiment of the present invention will be described.

  When the signal of the reference frequency Ref_freq output from the reference frequency oscillator and the signal RF OUT of the oscillation frequency output from the oscillator 307 are input to the phase comparator 301, the phase comparator 301 compares the phases of both, The phase difference component is output as a phase difference signal. As described above, the phase comparison process in the phase comparator 301 is performed by calculating the division ratio converted into the digital value and the cumulative addition value of the number of clocks indicated by the decimal point of the oscillation frequency in each cycle of the reference frequency signal. This is performed as a subtraction process with a digital value.

  The phase difference signal output from the phase comparator 301 is sent to the variable gain amplifier circuit 302. In the variable gain amplifier circuit 302, control data proportional to the frequency division ratio N is generated by amplification of the phase difference signal. The control data generated by the variable gain amplifier circuit 302 is sent to the subtractor 304.

In the subtractor 304, a process of subtracting a value f _min / Ref_freq obtained by dividing the minimum oscillation frequency f _min of the oscillator 307 by the reference frequency Ref_freq from the control data generated by the variable gain amplifier circuit 302 is performed. Here, it is necessary to know the minimum oscillation frequency f _min of the oscillator 307. For this _purpose , means for detecting the minimum oscillation frequency f _min by the configuration shown in FIG. 1 or FIG. 2 may be used. The frequency f _min is measured, the value obtained by the measurement is stored in a ROM (Read Only Memory, not shown) or the like, and the stored value is read out at the time of the subtraction process in the subtracter 304. A value of the oscillation frequency f _min may be obtained.

When the subtracting process is performed by the subtractor 304, the multiplier 306 then adds the coefficient α ′ (α ′ = D / N ′ = Ref_freq /) to the frequency division ratio N ′ in the control data after subtraction by the subtractor 304. k _dco ). The output of the multiplier 306 is used as control data D for the oscillator 307. Here, when the oscillation frequency for the control data D of the oscillator 307 is approximated to a linear curve, the following Equation 2 is obtained.

From the conversion coefficient α ′, D is given by Equation 3.

となる。この数式４の両辺をＲｅｆ＿ｆｒｅｑで除算して変形すると、以下の数式５の通りとなる。

Therefore, substituting Equation 3 into Equation 2,

It becomes. When both sides of Equation 4 are divided by Ref_freq and transformed, the following Equation 5 is obtained.

  The graph (1) in FIG. 3 shows the relationship between the frequency division ratio N ′ and the frequency f, and the graph (2) shows the relationship between the control data D and the frequency f. The relationship between the frequency division ratio N ′ and the frequency f has the relationship as shown in the above equation 4, and the relationship between the control data D and the frequency f has the relationship as shown in the above equation 2. is doing. Therefore, it can be seen that the configuration of the PLL circuit 300 as shown in FIG. 3 is correct as the data conversion procedure.

  The operation of the PLL circuit 300 according to the third embodiment of the present invention has been described above. As described above, according to the third embodiment of the present invention, in the PLL circuit, in the conversion to the control data of the oscillation circuit having the characteristic that the minimum oscillation frequency value does not become 0 Hz, the approximation to the primary curve is performed. It becomes possible. In addition, in synchronization with the change in the set value of the carrier frequency, calibration data is transmitted by transmitting control data for oscillating the minimum oscillation frequency to the oscillation circuit and measuring the number of clocks of the oscillation circuit output per cycle of the reference frequency. As one of the function functions, it is possible to detect the minimum oscillation frequency value.

(Fourth embodiment)
FIG. 4 is an explanatory diagram illustrating the configuration of a PLL circuit 400 according to the fourth embodiment of the present invention. The configuration of the PLL circuit 400 according to the fourth embodiment of the present invention will be described below with reference to FIG.

  As shown in FIG. 4, a PLL circuit 400 according to the fourth embodiment of the present invention includes a phase comparator 401, a variable gain amplifier circuit 402, a subtractor 404, a multiplier 406, an oscillator 407, It is comprised including.

  Similarly to the phase comparator 301 shown in FIG. 3, the phase comparator 401 outputs a signal of the reference frequency Ref_freq output from a reference frequency oscillator (not shown) and a signal of the oscillation frequency RF OUT output from the oscillator 407. Input, compare the phases of both, and output. In the phase comparison process in the phase comparator 401, the frequency division ratio converted into the digital value and the decimal point of the oscillation frequency are displayed in each cycle of the reference frequency signal, as in the phase comparator 301 shown in FIG. This is performed as a subtraction process of each cumulative addition value of the clock number with the digital value.

  Similar to the variable gain amplifier circuit 302 shown in FIG. 3, the variable gain amplifier circuit 402 controls the loop gain of the PLL circuit 400. The variable gain amplifier circuit 402 receives and amplifies the output of the phase comparator 401, thereby dividing the gain. Control data proportional to the circumferential ratio N is generated.

The subtractor 404 obtains a value obtained by dividing f _min ′ obtained by correcting the minimum oscillation frequency f _min of the oscillator 407 using the target frequency f _target to be controlled by the reference frequency Ref_freq from the control data proportional to the frequency division ratio N. The output is reduced. A method for calculating the value of f _min ′ will be described later. The value of f _min ′ is a value shown in the following Equation 6. Here, it is necessary to know the minimum oscillation frequency f _min of the oscillator 407. For this _purpose , means for detecting the minimum oscillation frequency f _min by the configuration shown in FIG. 1 or FIG. 2 may be used. The frequency f _min is measured, the value obtained by measurement is stored in a ROM (Read Only Memory, not shown) or the like, and the stored value is read out at the time of subtraction in the subtractor 404, so that the minimum A value of the oscillation frequency f _min may be obtained.

Similar to the multiplier 306 shown in FIG. 3, the multiplier 406 multiplies the output of the subtractor 404 by a conversion coefficient α ′ (α ′ = D / N ′ = Ref_freq / k _dco ) and outputs the result. . By multiplying the output of the subtractor 404 by the conversion coefficient α ′, it can be used as the control data D of the oscillator 407.

The oscillator 407 outputs a signal RF OUT that oscillates at a predetermined oscillation frequency. The oscillation frequency f of the oscillator 407 is expressed as Equation 7 below, where D is the control data, ΔC is the minimum variable capacitance value, C _{max is} the capacitance value when all switches are turned on, and L is the inductance value. The

  The configuration of the PLL circuit 400 according to the fourth embodiment of the present invention has been described above. Next, the operation of the PLL circuit 400 according to the fourth embodiment of the present invention will be described.

As described above, the oscillation frequency f of the oscillator 407 can be expressed as Equation 7. In Equation 7, for the control data D such that the value of D · ΔC is sufficiently smaller than C _max , the minimum oscillation frequency f _{min is set} to the Y intercept as shown in the graph (2) of FIG. Can be approximated to a linear curve. However, as the value of D increases, the error increases, and it becomes impossible to approximate a linear curve with the minimum oscillation frequency f _min as the Y intercept. Therefore, in the subtractor 404, instead of the value obtained by dividing f _min by the reference frequency Ref_freq, the minimum oscillation frequency f _min is corrected to f _min 'using the target frequency f _target to be controlled, and this f _min ' is used as a reference. The value divided by the frequency Ref_freq is subtracted and output.

In the above formula 7, when the derivative for D in f _target is obtained, the following formula 8 is obtained.

Assuming that the Y intercept at the time of approximation with a linear curve having a slope expressed by Equation 8 is f _min ′, f _target needs to satisfy the relationship of Equation 9 below.

となる。これは上述した数式６と同じ数式である。従って、図４に示した構成はこの計算結果を満たすように構成されたものである。すなわち、減算器４０４において、分周比Ｎに比例した制御データからｆ_{ｔａｒｇｅｔ}を用いて、最低発振周波数ｆ_ｍｉｎを補正したｆ_ｍｉｎ’を、基準周波数Ｒｅｆ＿ｆｒｅｑで割った値を減じて出力する。このように構成することで、発振回路の発振周波数に対するｋ_ＤＣＯの変化が無視できない領域においても、図４のグラフ（２）に示したようにｋ_ＤＣＯを傾きに持つ１次曲線に近似することができる。 By transforming Equation 9 and obtaining f _min ′,

It becomes. This is the same equation as Equation 6 described above. Therefore, the configuration shown in FIG. 4 is configured to satisfy this calculation result. That is, in the subtractor 404, the frequency division ratio using the _{f target} from the proportional control data to N, the _{f min} 'obtained by correcting the minimum oscillation frequency _{f min,} by subtracting the value obtained by dividing the reference frequency Ref_freq outputs. With such a configuration, even in a region where the change in k _DCO with respect to the oscillation frequency of the oscillation circuit cannot be ignored, it approximates to a linear curve having k _DCO as a slope as shown in the graph (2) of FIG. Can do.

The operation of the PLL circuit 400 according to the fourth embodiment of the present invention has been described above. As described above, according to the fourth embodiment of the present invention, even in a region where the change of k _DCO with respect to the oscillation frequency of the oscillation circuit cannot be ignored, it approximates to a linear curve having k _DCO as a tangential component as a slope. can do. In synchronization with the change in the set value of the carrier wave frequency, the control data for oscillating the minimum oscillation frequency is transmitted to the oscillation circuit, and the number of clocks of the oscillation circuit output per cycle of the reference frequency is measured, thereby performing calibration. As one of the function functions, it is possible to detect the minimum oscillation frequency value.

(Fifth embodiment)
FIG. 5 is an explanatory diagram illustrating the configuration of a PLL circuit 500 according to the fifth embodiment of the present invention. The configuration of the PLL circuit 500 according to the fifth embodiment of the present invention will be described below with reference to FIG.

  As shown in FIG. 5, a PLL circuit 500 according to the fifth embodiment of the present invention includes a phase comparator 501, a variable gain amplifier circuit 502, a subtractor 504, a multiplier 506, an oscillator 507, And an adder 508. In this configuration, the phase comparator 501, variable gain amplifier circuit 502, subtractor 504, multiplier 506, and oscillator 507 are included in the phase comparator 301 in the PLL circuit 300 according to the third embodiment of the present invention shown in FIG. 3. , Variable gain amplifier circuit 302, subtractor 304, multiplier 306 and oscillator 307, and phase comparator 401, variable gain amplifier circuit 402 in PLL circuit 400 according to the fourth embodiment of the present invention shown in FIG. Since it has the same function as the subtractor 404, the multiplier 406, and the oscillator 407, detailed description is omitted, and the adder 508 newly added from the configuration shown in FIGS. 3 and 4 will be described.

  The adder 508 adds a frequency modulation component to the output of the variable gain amplifier circuit 502 and outputs the result. By adding the frequency modulation component in the adder 508 and outputting it, the PLL circuit 500 can directly perform frequency modulation.

  The configuration of the PLL circuit 500 according to the fifth embodiment of the present invention has been described above. As described above, according to the fifth embodiment of the present invention, the frequency modulation component is added by the adder 508 and output, so that the PLL circuit 500 can directly perform the frequency modulation.

(Sixth embodiment)
FIG. 6 is an explanatory diagram illustrating the configuration of a wireless terminal device 600 according to the sixth embodiment of the present invention. The configuration of the wireless terminal device 600 according to the sixth embodiment of the present invention will be described below using FIG.

  As illustrated in FIG. 6, the wireless terminal device 600 according to the sixth embodiment of the present invention is configured to transmit a signal between a baseband circuit (Base-band BLOCK) 601 that handles a baseband signal and the baseband circuit 601. The transmission / reception module 602 that performs signal processing by exchanging signals, the antenna duplexer 603 that exchanges signals with the transmission / reception module 602, and the antenna 604 that transmits and receives radio waves. The transmission / reception module 602 is divided into a transmission system and a reception system. The transmission system includes a digital PLL 611, an oscillator 612, and an amplifier 613. The reception system includes a digital PLL 621, an oscillator 622, and an amplifier. 623, a down converter 624, a low-pass filter 625, and a variable gain converter 626.

  Here, any of the PLL circuits 300, 400, 500 according to the third to fifth embodiments of the present invention shown in, for example, any of FIGS. 3 to 5 is added to the digital PLL 611, 621 shown in FIG. Can be applied. By applying any of the PLL circuits 300, 400, and 500 to the wireless terminal device 600, the wireless terminal device 600 can have the effects of the above-described embodiments. That is, the radio terminal device 600 according to the sixth embodiment of the present invention acquires the minimum oscillation frequency of the DCO, and uses the acquired minimum oscillation frequency to control the DCO control data from the control data proportional to the frequency division ratio N. It is possible to perform conversion to.

  Note that the configuration of the wireless terminal device 600 illustrated in FIG. 6 is merely an example, and it is needless to say that the configuration is not limited to such an example. A device using a digital PLL can apply the PLL circuit of the present invention. For example, the PLL circuit according to the first to fifth embodiments of the present invention described above is applied as such a PLL circuit. be able to.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

It is explanatory drawing explaining the PLL circuit 100 concerning the 1st Embodiment of this invention. It is explanatory drawing explaining the PLL circuit 200 concerning the 2nd Embodiment of this invention. It is explanatory drawing explaining the PLL circuit 300 concerning the 3rd Embodiment of this invention. It is explanatory drawing explaining the PLL circuit 400 concerning the 4th Embodiment of this invention. It is explanatory drawing explaining the PLL circuit 500 concerning the 5th Embodiment of this invention. It is explanatory drawing explaining the structure of the radio | wireless terminal apparatus 600 concerning the 6th Embodiment of this invention. 1 is an explanatory diagram showing a conventional PLL circuit 10. FIG. 1 is an explanatory diagram showing a conventional PLL circuit 10. FIG. 1 is an explanatory diagram showing a conventional PLL circuit 10. FIG. It is explanatory drawing which shows the example of the ADPLL circuit using the conventional DCO.

Explanation of symbols

100, 200, 300, 400, 500 PLL circuit 101, 201 First flip-flop 102, 202 First comparison circuit 103, 203 Oscillator 104, 204 Reference frequency oscillator 105, 205 First cumulative adder 106, 206 First Two cumulative adders 107, 207 Second comparison circuit 108, 208 Second flip-flop 109, 209 First switch 110, 210 Second switch 211 Divider 301, 401, 501 Phase comparator 302, 402, 502 Variable gain amplifier 304, 404, 504 Subtractor 306, 406, 506 Multiplier 307, 407, 507 Oscillator 508 Adder 600 Wireless terminal device

Claims (13)

A PLL (Phase Locked Loop) circuit having an oscillation circuit controlled using a digital value,
A carrier frequency holding unit for holding a carrier frequency value;
A detection unit for detecting that a carrier frequency value has changed from a value held by the carrier frequency holding unit;
In synchronization with the change in the carrier frequency value detected by the detection unit, a control signal for causing the oscillation circuit to oscillate at the lowest frequency is transmitted, and the number of output clocks of the oscillation circuit within one cycle of the reference frequency is measured. A measuring unit to perform,
A PLL circuit comprising: A PLL circuit having an oscillation circuit controlled using a digital value,
A carrier frequency holding unit for holding a carrier frequency value;
A detection unit for detecting that a carrier frequency value has changed from a value held by the carrier frequency holding unit;
A first measurement unit that transmits a control signal for causing the oscillation circuit to oscillate at a minimum frequency in synchronization with a change in the carrier frequency value detected by the detection unit, and measures the number of clocks of a reference frequency;
A setting unit for setting the number of clocks of the reference frequency measured by the first measuring unit;
A second measuring unit for measuring the number of output clocks of the oscillation circuit within a reference frequency period equivalent to the number of clocks measured by the first measuring unit;
The number of output clocks of the oscillation circuit measured by the second measurement unit within a reference frequency period equivalent to the number of clocks measured by the first measurement unit is averaged by the number of clocks measured by the first measurement unit. The average part
A PLL circuit comprising: A PLL circuit having an oscillation circuit controlled using a digital value,
A minimum frequency setting section for measuring or inputting a minimum frequency value;
A subtracting unit for subtracting a value obtained by dividing the minimum frequency value by a reference frequency value from control data proportional to the frequency division ratio;
A multiplier for multiplying a coefficient corresponding to a value obtained by dividing the reference frequency value by the conversion gain of the oscillation circuit;
A PLL circuit using the output of the multiplication unit as a control signal for the oscillation circuit.   The PLL circuit according to claim 3, wherein frequency modulation is directly performed on the oscillation circuit. A PLL circuit having an oscillation circuit controlled using a digital value,
A minimum frequency measuring unit for measuring a minimum frequency value in the PLL circuit according to claim 1;
A subtracting unit for subtracting a value obtained by dividing the minimum frequency value by a reference frequency value from control data proportional to the frequency division ratio;
A multiplier for multiplying a coefficient corresponding to a value obtained by dividing the reference frequency value by the conversion gain of the oscillation circuit;
A PLL circuit using the output of the multiplication unit as a control signal for the oscillation circuit.   The PLL circuit according to claim 5, wherein the oscillation circuit is directly subjected to frequency modulation. A PLL circuit having an oscillation circuit controlled using a digital value,
A minimum frequency setting section for measuring or inputting a minimum frequency value;
An arithmetic unit for calculating a frequency value corresponding to a Y intercept when approximating the relationship between control data and frequency to a linear curve from the lowest frequency value and the carrier frequency value;
A subtracting unit for subtracting a value obtained by dividing a frequency value corresponding to the Y-intercept by a reference frequency value from control data proportional to the frequency division ratio;
A multiplier for multiplying a coefficient corresponding to a value obtained by dividing the reference frequency value by the conversion gain of the oscillation circuit;
A PLL circuit using the output of the multiplication unit as a control signal for the oscillation circuit.   The PLL circuit according to claim 7, wherein frequency modulation is directly performed on the oscillation circuit. A PLL circuit having an oscillation circuit controlled using a digital value,
A minimum frequency measuring unit for measuring a minimum frequency value in the PLL circuit according to claim 1;
An arithmetic unit for calculating a frequency value corresponding to a Y intercept when approximating the relationship between control data and frequency to a linear curve from the lowest frequency value and the carrier frequency value;
A subtracting unit for subtracting a value obtained by dividing a frequency value corresponding to the Y-intercept by a reference frequency value from control data proportional to the frequency division ratio;
A multiplier for multiplying a coefficient corresponding to a value obtained by dividing the reference frequency value by the conversion gain of the oscillation circuit;
A PLL circuit using the output of the multiplication unit as a control signal for the oscillation circuit.   The PLL circuit according to claim 9, wherein frequency modulation is directly performed on the oscillation circuit.   A wireless terminal apparatus comprising the PLL circuit according to claim 1. A frequency detection method in a PLL circuit having an oscillation circuit controlled using a digital value,
A carrier frequency holding step for holding a carrier frequency value;
A detecting step for detecting that the carrier frequency value has changed from the value held in the carrier frequency holding step;
In synchronization with the change in the carrier frequency detected in the detection step, a control signal for causing the oscillation circuit to oscillate at the lowest frequency is transmitted, and the number of output clocks of the oscillation circuit within one cycle of the reference frequency is measured. Measuring steps to
The frequency detection method characterized by including. A frequency detection method in a PLL circuit having an oscillation circuit controlled using a digital value,
A carrier frequency holding step for holding a carrier frequency value;
A detecting step for detecting that the carrier frequency value has changed from the value held in the carrier frequency holding step;
A first measurement step of transmitting a control signal for causing the oscillation circuit to oscillate at a minimum frequency in synchronization with a change in the carrier frequency value detected in the detection step, and measuring the number of clocks of a reference frequency;
A setting step for setting the number of clocks of the reference frequency measured in the first measurement step;
A second measuring step of measuring the number of output clocks of the oscillation circuit within a reference frequency period equivalent to the number of clocks measured in the first measuring step;
The number of output clocks of the oscillation circuit measured in the second measurement step within a reference frequency period equivalent to the number of clocks measured in the first measurement step is averaged with the number of clocks measured in the first measurement step. The average step to
The frequency detection method characterized by including.

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