JP2001144612A - Pll synthesizer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL synthesizer circuit whose output frequency can quickly be changed and that can prevent occurrence of a noise. SOLUTION: In the case of changing the output frequency of the PLL synthesizer circuit, a control system by a sub charge pump circuit 13 is adopted for the control of a VCO 6 and discriminates whether or not a difference of frequency division data before and after the change is within a prescribed range. When the difference is at the outside of the prescribed range, a loop filter 5 is forcibly charged by a charge time in proportion to the difference between the frequency division data. Furthermore, in the came of changing the frequency, a flip-flop 15 of a system clock stop circuit 14 is reset to allow an OR gate 16 to supply a system clock to a frequency revision circuit 9, and a discrimination section 11 uses an operation end signal to set the flip-flop 15 so as to interrupts transmission of the system clock to the frequency revision circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an RD for changing a receiving broadcast station by switching a local oscillation frequency at high speed.
The present invention relates to a PLL synthesizer circuit suitable for an S radio receiver and the like.

[0002]

2. Description of the Related Art Generally, in a radio receiver called an electronic tuner, a local oscillation signal is converted into a PL signal as shown in FIG.
It is generated from an L (phase locked loop) synthesizer circuit. The PLL synthesizer circuit is composed of a conventionally well-known PLL. Therefore, PLL
Description of the normal operation of the synthesizer circuit is omitted.

The operation of the PLL synthesizer circuit when changing the frequency of the local oscillation signal will be described. First, based on the frequency of the receiving broadcast station,
Divided data on the frequency division ratio is supplied to the programmable divider 1. The frequency division number of the programmable divider 1 is changed by the frequency division data, and the phase of this output changes. In the phase comparison circuit 3, the phase of the reference signal from the reference signal generation circuit 2 and the programmable divider 1
Is compared with the reference signal for each period of the reference signal, and an error signal is generated from the main charge pump circuit 4 according to the phase difference. The error signal is smoothed to a DC voltage by the loop filter 5 to become a control voltage of a VCO (voltage controlled oscillator) 6, and the oscillation frequency of the VCO 6 changes according to the control voltage. In this manner, the output phase of the programmable divider 1 gradually approaches the phase of the reference signal,
The change of the VCO 6 operates repeatedly. Eventually, the two phases match, the PLL circuit locks, and VCO6
The oscillating frequency according to the frequency-divided data, that is, according to the frequency of the receiving broadcasting station.

[0004] The output signal (local oscillation signal) of the VCO 6 is mixed with an RF amplified signal in a mixer to obtain an intermediate frequency (IF) signal. The IF signal is always at a constant frequency, and the local oscillation frequency is changed according to the receiving broadcast station.

[0005]

In the conventional PLL synthesizer circuit, when the output frequency is to be changed, the phase of the reference signal is compared with the output phase of the programmable divider 1, and an error signal corresponding to the comparison result is output. Operation is repeated. Generally, the above operation is performed several hundred times from the start of the frequency change until the PLL is locked. On the other hand, since this operation is performed for each cycle of the reference frequency, when the reference frequency is 50 kHz, one operation (the operation from the phase comparison to the change of the oscillation frequency of the VCO) takes 20 times.
It takes μsec. For this reason, it takes 20 μsec × several hundred times from the start of the change until the PLL is locked.

In European radio broadcasting,
2. Description of the Related Art Traffic information is multiplexed and transmitted on a normal broadcast. This broadcast is RDS (Radio Data S)
system), and a dedicated tuner is required to receive the RDS broadcast and obtain traffic information.
In such an RDS tuner, various functions using traffic information are added. For example, there is data identifying the program in traffic information. Therefore, when the currently receiving station becomes difficult to listen to, there is a function of searching for and receiving an alternative broadcasting station using the data. In order to achieve this function, it is necessary to always search for an alternative broadcast station while listening to the receiving station to grasp the existence of the alternative broadcast station. In this alternative station search, it is necessary to quickly change the frequency of the broadcasting station currently listening to another broadcasting station, check the RDS data of the alternative station and the reception state, and then quickly return to the current receiving station again. There is.

However, in the PLL synthesizer circuit shown in FIG. 3, it takes a long time after the frequency is changed until the PLL is locked. Accordingly, there is a problem that the time for changing the frequency to the alternative broadcasting station and the time for changing the frequency to the current broadcasting station are prolonged, and as a result, the current receiving station is interrupted, resulting in an unfavorable listening situation.

(Related Application) The applicant of the present invention has proposed a PLL synthesizer capable of locking a PLL at high speed in Japanese Patent Application No. 10-335875. This PLL synthesizer has a frequency changing circuit.

This frequency changing circuit determines whether or not a difference between a count value of the frequency counter and the frequency division number data is within a predetermined range, and a frequency counter for counting an output frequency of the PLL circuit. A determination unit, and a calculation unit that counts a change amount of the output frequency of the PLL circuit based on a determination result of the determination unit, and calculates an output signal width applied to the sub charge pump circuit according to the change amount. ing.

[0010] When changing the receiving broadcasting station,
The determination unit compares the count value of the frequency counter corresponding to the output frequency of the VCO in the PLL circuit with the frequency division number data of the receiving broadcast station to be tuned, and
It is determined whether or not the difference between the output frequency and the frequency of the receiving broadcast station is within a predetermined range. And if it is not within the predetermined range,
An output signal corresponding to the calculation result of the calculation unit is applied to the sub charge pump, and the output of the sub charge pump is applied to the VCO via the loop filter. As a result, the oscillation frequency of the VCO is forcibly set to a frequency close to the frequency of the receiving broadcast station. For this reason, when the operation returns to the normal PLL operation thereafter, the frequency difference is small, and the period until the PLL is locked can be greatly reduced.

Here, the frequency counter, the determination unit and the calculation unit of the frequency changing circuit are generally synchronous circuits that operate in synchronization with the same system clock as the PLL circuit and the like. Therefore, the system clock is always input to the frequency changing circuit. That is, the system clock is always input to the frequency change circuit even when the frequency change circuit is not operating to change the frequency. On the other hand, the frequency changing circuit has many flip-flops for counting, storing data, and the like.

[0012] Then, the clock input of these flip-flops always operates by the system clock, and unnecessary noise is generated. Such unnecessary noise due to the clock input of the flip-flop causes deterioration of characteristics of high-frequency related circuits that dislike noise, such as an input amplifier of the PLL circuit and an IF circuit in a radio receiver, or causes malfunction.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a PLL synthesizer that can lock a PLL at high speed and prevent generation of unnecessary noise.

[0014]

According to the present invention, there is provided a PLL circuit for generating an output signal having a frequency corresponding to input data, and a difference between the frequency of the output signal of the PLL circuit and the frequency corresponding to the input data. And a system clock stop circuit for stopping a system clock of the frequency change circuit in accordance with an operation state of the frequency change circuit.

As described above, according to the present invention, since the frequency of the PLL circuit can be changed in a short time, the change of the receiving station in the radio receiver can be performed in a short time. In particular,
At the time of searching for an alternative broadcast station in the RDS radio receiver, it is possible to quickly change to the alternative broadcast station, so that it is possible to prevent a sense of incongruity in hearing. When the frequency changing circuit is not performing the frequency changing operation, the system clock to the frequency changing circuit is cut off to prevent the occurrence of noise. Deterioration of characteristics of a circuit or the like can be prevented.

Further, the frequency changing circuit has a determining unit for determining whether a difference between the frequency corresponding to the input data and the frequency of the output of the PLL circuit is within a predetermined range, and based on the determination result of the determining unit. It is preferable that it is determined whether or not to change the output frequency of the PLL circuit, and the system clock stop circuit stops the system clock when the frequency change circuit does not change the output frequency of the PLL circuit. It is.

Further, the system clock stop circuit includes:
A data change signal output at the time of conversion of control data of the data input circuit in the PLL circuit and a determination signal output from a determination unit in the frequency change circuit are input. It is preferable to include a state holding circuit for holding a control signal for controlling the frequency control circuit, and a control gate for controlling supply or cutoff of a system clock to the frequency changing circuit by an output of the state holding circuit.

[0018]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of Frequency Changing Circuit] In this embodiment, a frequency changing circuit 9 is provided. The frequency changing circuit 9 includes a frequency counter 10 for counting the frequency of the VCO 6, a determining unit 11 for determining whether the counted frequency is within a predetermined range, and an output level of the loop filter 5 according to the result of the determining unit 11. And a calculation unit 12 for calculating an amount by which to change. Further, the PLL circuit 8 includes a sub charge pump circuit 13 that generates an error signal according to the output of the calculation unit 12. In FIG. 1, FIG.
The same reference numerals are given to the same circuits as in the conventional example, and the description is omitted.

First, the frequency changing operation of FIG. 1 will be described with reference to the flowchart of FIG. Data input circuit 7
It is determined whether the frequency division data has been input from the external control circuit (S1). If there is no input, the data input circuit 7 continues to wait for data until data is input. On the other hand, when data is input, first, the data input circuit 7 inputs the frequency-divided data only to the determination unit 11. In this step, input to the programmable divider 1 is prohibited.

The determination unit 11 receives the input frequency-divided data,
The difference from the frequency division data before the frequency division number change is calculated (S2), and it is determined whether the difference is within a predetermined range or outside the allowable range (S3). Note that the determination unit 11 stores the frequency division data input last time as it is, and compares it with the current frequency division data.

When it is determined that the difference between the divided data is within the predetermined range, the changing operation of the frequency changing circuit 9 is stopped, and the divided data held in the data input circuit 7 is transferred to the programmable divider 1. Is entered. Then, the frequency division number of the programmable divider 1 is changed, and then the oscillation frequency of the VCO 6 is changed so that the phase of the reference signal of the reference signal generating circuit 2 matches the output signal of the programmable divider 1, and the PLL circuit is changed. A normal operation is performed so that 8 is locked (S4).

If it is determined that the difference between the frequency division numbers is out of the predetermined range, a reset signal is generated from the determination unit 11, and the reset signal resets the programmable divider 1, the reference signal generation circuit 2, and the phase comparison circuit 3. . Further, a stop signal is generated from the determination unit 11 and the main charge pump circuit 4
Operation is stopped. Further, based on the reset signal from the determination unit 11, the time constant of the loop filter 5 is changed so as to decrease.

The calculation section 12 is activated by the rise of the reset signal. The calculation unit 12 calculates the charge application time to the sub charge pump circuit 13 based on the difference between the frequency division data transferred from the determination unit 11. The first calculation after changing the frequency division number is performed so that a time proportional to the frequency division difference is set as the charge application time. That is, the difference between the frequency division numbers is DD, and the charge application time is Tc1.
Then, Tc1 = α × DD, and the charge application time Tc1 is calculated by this equation (S5).

When the charge application time Tc1 is calculated,
A charge control signal having a pulse width of time Tc1 is applied to sub charge pump circuit 13. In response, sub charge pump circuit 13 converts the pseudo error signal into loop filter 5.
Output to Due to such forced charging, the output potential of the loop filter 5 changes, and as a result, the oscillation frequency of the VCO 6 changes (S6). Thereafter, the frequency counter 10 waits for the oscillation frequency of the VCO 6 to stabilize,
It starts counting the oscillation frequency of O6 (S7).

After the frequency counter 10 finishes counting, the process returns to step S2. However, in step S2, the calculation of the first change frequency after the frequency change is to find the difference between the frequency data to be changed and the frequency data before the change. , Frequency counter 10
Is to determine the difference between the count value and the set frequency-divided data. Therefore, in the determination unit 11, the current VCO
The difference between the oscillation frequency of No. 6 and the output frequency of the PLL circuit to be set is obtained, and it is determined whether or not the difference is within a predetermined range.

Here, the frequency counter 10 counts the number of local oscillation signals from the VCO 6 input during one period of the reference signal from the reference signal generation circuit 2 of the PLL circuit. The PLL circuit 8 divides the local oscillation signal from the VCO 6 in the programmable divider 1 based on the divided data, and operates so that the signal after the division becomes the same as the reference signal. Therefore, when the PLL is locked, the number of local oscillation signals input during one period of the reference signal is equal to the frequency-divided data. Therefore,
In the determination unit 11, the count value of the frequency counter 10
The difference is obtained by comparing the frequency-divided data as it is.

If the difference between the count value of the frequency counter 10 and the set frequency-divided data is within a predetermined range, the reset signal is released, and the operation of the main charge pump circuit 4 is released to stop the operation of the PLL circuit 8. Is locked by resuming.

On the other hand, when the difference between the count value of the frequency counter and the set frequency-divided data is out of the predetermined range, the charging time Tc2 (or Tc (N)) is calculated based on the difference. As described above, the first calculation after changing the frequency division number is that the time proportional to the frequency division difference is the charge application time Tc1 (or
Tc (N-1)), but in the second and subsequent calculations, the charge time Tc is calculated by the following formula.
2 is calculated. That is, assuming that the previously calculated charging time is Tc (N-1), the oscillation frequency changed by Tc (N-1) is ΔF, and the difference between the count value of the frequency counter and the set frequency dividing data is ΔDa,

Tc2 = (TC1 / ΔF) × ΔDa = (Tc (N−1) / ΔF) × ΔDa = Tc (N) (1) According to this formula, the charging time is controlled in accordance with the characteristic obtained by the previous frequency change, and the output frequency of the VCO 6 is controlled more accurately.

When the charge application time Tc2 is calculated,
A charge control signal having a pulse width of time Tc2 is applied to sub charge pump circuit 13. In response, sub charge pump circuit 13 converts the pseudo error signal into loop filter 5.
Output to Then, the output potential of the loop filter 5 changes, and as a result, the oscillation frequency of the VCO 6 changes. Then, after the oscillation frequency of the VCO 6 is stabilized, the frequency counter 10 counts the oscillation frequency of the VCO 6 again. After the counting by the frequency counter is completed, the process returns to step S2 again, but from S2 to S7 until the difference between the count value of the frequency counter 10 and the set frequency-divided data falls within a predetermined range.
Is repeated.

As described above, when changing the frequency, the charge time to the loop filter 5 necessary for the frequency change can be accurately calculated from the result of the frequency change amount with respect to the previous charge time. Can be performed several times. Therefore, the time required for changing the frequency can be reduced in the PLL circuit of the present invention, as compared with the conventional PLL circuit that requires several hundred circuits to apply the charge until the frequency is changed to the set frequency.

In the above-described example, a sub charge pump 13 is provided separately from the main charge pump circuit 4, and the sub charge pump 13 is controlled by the calculation unit 12 so that the VCO
The oscillation frequency of No. 6 was controlled from outside the PLL circuit. However, the signal from the calculation unit 12 causes the main charge pump circuit 4
May be controlled. That is, after the operation of the phase comparison circuit 3 is prohibited, the main charge pump circuit 4 is controlled in the same manner as the control of the sub charge pump circuit described above. Thus, when the frequency difference before and after the change of the local oscillation frequency is large, a voltage corresponding to the value calculated by the calculation unit 12 can be output from the main charge pump 4 instead of the output of the phase comparison circuit 3 of the PLL circuit 8. Therefore, the VCO 6 oscillation frequency is set to the target value (frequency corresponding to the frequency of the changed broadcasting station) at an early stage.
Can be approached. And according to this method,
The sub charge pump circuit 13 becomes unnecessary.

"Description of System Clock Stop Circuit" In the present embodiment, as shown in FIG. 1, a system clock stop circuit for cutting off the system clock of the frequency change circuit 9 according to the operation state of the frequency change circuit 9 14 is provided. Note that the system clock is the PLL circuit 8
Generated by the reference signal generation circuit 2 in
MHz.

The system clock stop circuit 14 includes:
Two signals, a data change signal output when the control data of the data input circuit 7 in the PLL circuit changes, and a determination signal output from the determination unit of the frequency change circuit 9 are input. The system clock stop circuit 14 includes a state holding circuit (D-type flip-flop) 15 that holds a control signal for operating / stopping the system clock according to the state of the two signals, and a frequency changing circuit 9 based on the output of the flip-flop 15.
It comprises a control gate (OR gate) 16 for controlling transmission / cutoff of the system clock. Note that the data change signal is a signal generated in the data input circuit 7 when the frequency-divided data is externally input to the data input circuit 7, and is a signal that is at the H level for a predetermined time. The output of the data change signal corresponds to the output timing of the frequency-divided data to the determination unit 11.

When the data change signal is input to the reset terminal of the flip-flop 15, the output of the flip-flop 15 becomes L level, and the OR gate 16 becomes the PLL circuit 8
Starts to be transmitted to the frequency changing circuit 9. Thus, the frequency changing circuit 9 starts operating.

The operation end signal from the judging section 11 is input to the clock input terminal of the flip-flop 15 in the system clock stop circuit 14, and the data input terminal D of the flip-flop 15 is pulled up to H. ing. Therefore, by the rise of the operation end signal,
The output of the flip-flop 15 becomes H. This operation end signal is NO in the determination of S3 by the determination unit 11.
The signal corresponds to a signal for canceling the reset signal output at the time when the signal has become.

When the flip-flop 15 is set to H, the output of the OR gate 16 is fixed to H, and the system clock to the frequency changing circuit 9 is cut off. For this reason,
No noise is generated from the frequency changing circuit 9.

When the frequency is changed again, the data change signal is output by inputting the frequency data to the data input circuit 7, whereby the output of the flip-flop 15 becomes L, and the system clock is output as described above. Is supplied to the frequency changing circuit 9, and the frequency changing circuit restarts its operation.

[0039]

As described above, according to the present invention,
Since the frequency of the PLL can be changed in a short time, the receiving station can be changed in the radio receiver in a short time.
In particular, when searching for an alternative broadcast station in the RDS radio receiver, it is possible to quickly change to the alternative broadcast station, so that it is possible to prevent a sense of incongruity in hearing. When the frequency changing circuit is not performing the frequency changing operation, the system clock to the frequency changing circuit is cut off to prevent the occurrence of noise. Deterioration of characteristics of a circuit or the like can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a configuration example of a PLL synthesizer circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of the circuit according to the embodiment.

FIG. 3 is a circuit block diagram illustrating a configuration example of a conventional PLL synthesizer circuit.

[Explanation of symbols]

1 programmable divider, 2 reference signal generation circuit,
3 phase comparison circuit, 4 main charge pump circuit, 5 loop filter, 6 voltage controlled oscillation circuit (VCO), 7 data input circuit, 8 PLL circuit, 9 frequency change circuit,
10 frequency counter, 11 determination unit, 12 calculation unit,
13 sub charge pump circuit, 14 system clock stop circuit, 15 flip-flop, 16 OR gate.

Continued on the front page F term (reference) 5J106 AA04 BB04 CC01 CC21 CC32 CC33 CC41 DD17 DD32 DD42 EE09 EE15 GG07 HH03 JJ09 KK03 KK24 PP03 QQ06 QQ09 RR10 RR17 RR21 5K020 DD05 DD26 GG04 GG09 GG10 GG12 JJ01 LL07

Claims (3)

[Claims] 1. A PLL circuit for generating an output signal having a frequency corresponding to input data, and an output frequency of the PLL circuit according to a difference between a frequency of an output signal of the PLL circuit and a frequency corresponding to the input data. And a system clock stop circuit for stopping a system clock of the frequency change circuit in accordance with an operation state of the frequency change circuit. 2. The circuit according to claim 1, wherein the frequency change circuit has a determination unit that determines whether a difference between a frequency corresponding to the input data and a frequency of an output of the PLL circuit is within a predetermined range, It is determined whether or not to change the output frequency of the PLL circuit based on the determination result of the determination unit. The system clock stop circuit determines whether the frequency change circuit has not changed the output frequency of the PLL circuit. , Stopping the system clock
LL synthesizer circuit. 3. The circuit according to claim 2, wherein the system clock stop circuit includes: a data change signal output when converting control data of a data input circuit in the PLL circuit; and a determination unit in the frequency change circuit. And a state holding circuit for holding a control signal for controlling the operation or stop of the system clock according to the state of these signals, and the output of the state holding circuit outputs the system clock to the frequency changing circuit. And a control gate for controlling supply or cutoff.