JPH0793576B2 - Frequency synthesizer - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a frequency synthesizer having a phase locked loop circuit for performing a phase locked process at high speed.

[Conventional technology]

In order to realize a mobile phone, it is necessary to reduce its power consumption, and among them, the low power consumption of a frequency synthesizer is an important issue. For that purpose, not only low power consumption in terms of circuit configuration but also low power consumption in terms of circuit operation such as intermittent operation is indispensable.

However, the conventional intermittent control frequency synthesizer has a drawback in that, in intermittent operation, the frequency varies when the power supply is switched from off to on.

Conventionally, some circuits have been proposed for suppressing this fluctuation. However, these circuits only keep the frequency fluctuation low, so they are not suitable when you want to obtain a stable signal by intermittently operating the phase synchronization control like the intermittent PLL operation described later. There was an insufficient aspect as an application to.

The prior art will be described in detail below.

FIG. 1 is a block diagram showing the basic configuration of a conventional frequency synthesizer for intermittent operation.

As shown in the figure, the voltage-controlled oscillator 51 (VC
The output of (O) is divided by the variable frequency divider 52, and the phase of the output signal is compared with the phase of the output signal of the reference oscillator 53.
54, and the phase error signal is smoothed by the loop filter 55 and is input to the voltage controlled oscillator 51.

In this configuration, the phase-locked loop (PLL) is
, The phase error signal is controlled to be small, and an output signal with a stable frequency can be obtained from the voltage controlled oscillator.

The types of intermittent operation of such a circuit are classified into the following two types.

Intermittent PLL operation: The operation of the voltage controlled oscillator 51 continues, and the other circuits are controlled by the control circuit 58 controlling the power switch 59 (indicated as SW in the figure) to intermittently supply power from the power source 57. Perform intermittent operation.

Intermittent signal operation: The control circuit 58 controls the power switch 59 to intermittently supply power to all circuits including the voltage controlled oscillator.

The intermittent operation control method is the same as the above two. The procedure is shown in FIG.

First, when turning off the power of each circuit, loop filter 55
In order to hold the control voltage of the voltage controlled oscillator 51 charged in the phase comparator 54, the signal from the phase comparator 54 is cut off by the switch circuit 56 provided between the loop filter 55 and the phase comparator 54. Next, the power supply is turned off for a certain period. If the power supplies other than the voltage controlled oscillator 51 are turned off during this period, it becomes an intermittent PLL operation, and if the power supplies of all circuits including the voltage controlled oscillator 51 are turned off, it becomes an intermittent signal operation.

Next, after the power is turned on, the switch circuit 56 is closed and the signal from the phase comparator 54 is transmitted to the loop filter 55.
At this time, the phase of the output signal of the variable frequency divider 52 and the reference oscillator
If there is a phase difference between the output signal of 53 and the phase of the output signal of 53, when the switch circuit 56 is closed, the control voltage of the voltage controlled oscillator 51 charged in the loop filter 55 is changed by the phase error signal.

Therefore, it is necessary to match the phase of the output signal of the variable frequency divider 52 with the phase of the output signal of the reference oscillator 53 before closing the switch circuit 56.

There are mainly the following two types of this method.

That is, one is a method of detecting that the phases match and closing the switch circuit 56, and the other is a method of controlling a phase shift circuit for matching the phases to close the switch circuit.

Since it is difficult for the former method to detect the moment when the phases match, a certain allowable phase error is given to make it easier to obtain the detection signal.

As an actual example, the 800 MHz band frequency synthesizer (the phase comparison frequency is 25 kHz) can match the phases within an allowable error range of about 6 nsec.

On the other hand, the latter method is a method of releasing the reset of the variable frequency divider 52 and starting the frequency dividing operation at the edge of the output signal of the reference oscillator 53, for example. In this case, the phase error is one cycle of the input signal, so it is about 800MHz band frequency synthesizer.
It is 1.3 nsec. However, in this method, when the control circuit is delayed, the delay is added to the phase error. In order to cancel this phase error, there is a method of controlling the frequency division number of the variable frequency divider after reset release.

[Problems to be solved by the invention]

FIG. 3 is a time chart showing a conventional control for controlling the frequency division number of the variable frequency divider after reset release in order to cancel the above-mentioned phase error.

In the figure, when the falling edge of the reference signal (output signal of the reference oscillator) is detected, the reset of the variable frequency divider is released and the frequency dividing operation is started. At this time, only the first cycle of the output signal of the variable frequency divider is divided by the frequency division number n capable of canceling the delay amount, and the second and subsequent cycles are divided by the channel setting frequency division number N.

According to this method, if the frequency division number n that can operate the delay amount is set regardless of the delay amount, the phase can be matched with the accuracy of one cycle of the input signal. However, this delay amount may change due to product variations, temperature fluctuations, and voltage fluctuations. Therefore, if the frequency division number n is set to a constant value, the phase error becomes large and the frequency fluctuates. .

An object of the present invention is to solve the above-mentioned drawbacks in the conventional frequency synthesizer, to establish the phase synchronization at the time of reforming the phase locked loop extremely quickly, and to provide a frequency synthesizer in which the frequency fluctuation is reduced. There is.

[Means for solving problems]

According to the invention, the above mentioned objects are achieved by means of the patent claims.

That is, the frequency synthesizer according to the present invention: (i) blocks a phase error signal between the phase of the output signal of the reference oscillator and the phase of the output signal of the variable frequency divider from being transmitted to the loop filter, A function to hold the control voltage of the voltage controlled oscillator charged in the inside, and (ii) Phase difference detection to detect the phase difference between the phase of the output signal of the reference oscillator and the phase of the output signal of the variable frequency divider. Functions and (iii) After resetting the internal state of the variable frequency divider, the edge of the output signal of the reference oscillator is detected and the reset of the variable frequency divider is released to perform the n ₁ frequency division operation only in the first cycle. , Second
From the cycle onward, the frequency is divided by N over a constant period, and during this division, the phase difference detection circuit detects the phase difference of the N divided output phase of the variable frequency divider with respect to the output phase of the reference oscillator. , the frequency division number n _i of the variable frequency divider according to the result
Phase difference detection operation to set n ₂ , and (iv) after the phase error signal from the phase comparator is cut off and the control voltage of the voltage controlled oscillator is held in the loop filter,
The phase difference detection operation described in (iii) is repeated until the phase difference between the phase of the output signal of the reference oscillator and the phase of the output signal of the variable frequency divider becomes smaller than the specified value, and the final phase difference detection operation is performed. Immediately after, that is, when the phase difference becomes equal to or less than a predetermined value, the switch circuit is connected and a function of controlling to detect a closed loop is provided.

As described above, the frequency synthesizer of the present invention has a phase difference detection operation with the conventional frequency synthesizer, and the phase of the output signal of the reference oscillator and the output signal of the variable frequency divider are obtained by the phase difference detection operation. 2 is different in that it has a function of controlling the phase difference of 1 below a specified value.

〔Example〕

FIG. 4 is a block diagram of an embodiment of the present invention.
Is a voltage controlled oscillator (denoted as VCO in the figure), 2 is a variable frequency divider, 3 is a reference oscillator, 4 is a phase comparator, 5 is a loop filter, 6 is a switch circuit, 7 is a phase difference detection circuit,
Reference numeral 8 represents a control circuit, 9 represents a power supply, and 10 represents a power switch (denoted as SW in the drawing).

The variable frequency divider 2 has a reset function of performing the frequency dividing operation with n _i only in the first cycle after reset release and performing the N frequency dividing operation in the second and subsequent cycles. The phase difference detection circuit 7 is a circuit that detects a phase difference between the phase of the output signal of the reference oscillator 3 and the phase of the output signal of the variable frequency divider 2.

FIG. 5 is a time chart showing an example of the operation of the embodiment shown in FIG.

The operation will be described below with reference to FIGS. 4 and 5.

When the switch circuit 6 is closed to form a loop in the circuit of this embodiment, the control voltage of the voltage controlled oscillator 1 corresponding to the output oscillation frequency is held in the loop filter 5.
This can also be achieved by externally charging the voltage control, or by forming the phase locked loop once and then opening the loop to hold the control voltage.

Next, before closing the loop, in the first phase difference detection operation, n ₁ is set as the frequency division number n _i to reset the internal state of the variable frequency divider 2 and then the edge of the output of the reference oscillator 3 is set. Upon detection, the reset of the variable frequency divider 2 is released, the n ₁ frequency division operation is performed only in the first cycle, and the N frequency division operation is performed for a fixed period after the second cycle. The period here is a period of the variable frequency divider output signal.

During this frequency division operation, the phase difference detection circuit 7 detects the phase difference between the output frequency of the reference oscillator 3 and the N frequency-divided output phase of the variable frequency divider 2. If the phase difference is equal to or larger than the specified value, the frequency division number n _i of the variable frequency divider ₂ is reset to n ₂ , and then the second phase difference detection operation is performed.

That is, after resetting the variable frequency divider 2 again,
Perform the same operation as the first time. If the phase difference is equal to or greater than the specified value, the frequency divider n _i of the variable frequency divider 2 is set to n ₃ and the same operation is performed.

The above operation is repeated until the phase difference between the phase of the output signal of the reference oscillator 3 and the phase of the output signal of the variable frequency divider 2 becomes smaller than the specified value, and immediately after the final phase difference detection operation, the switch is operated. The circuit 6 is closed to form a closed loop.

In the final phase difference detection operation, the phase difference becomes one cycle or less of the input signal of the variable frequency divider 2. Therefore, if a closed loop is formed immediately after that, the phase locked loop is established with almost no frequency fluctuation. . In the subsequent intermittent operation of the power supply, the frequency division number n of the variable frequency divider holds the value of the last phase difference detection operation unless the phase difference output of the phase difference detection circuit 7 becomes larger than the specified value.

FIG. 6 (a) shows an example of the configuration of the variable frequency divider 2 that performs the frequency dividing operation only in the first cycle after the reset is released with n _i and then performs the frequency dividing operation in the second cycle and thereafter. A time chart for explaining the operation is shown in (b).

In FIG. 9A, the variable frequency divider 12 reads the frequency division number set in the frequency division number data terminal 11 into the frequency divider at the rising edge of the output signal. Therefore, if the frequency division number n is set in the frequency division number data terminal 11 before the reset is released, the frequency division output signal rises at the first input clock after the reset is released, and at the same time the frequency division number n is divided. Read in. Then, in the first cycle, the frequency division operation of n is performed. At this time, this first
If the frequency dividing number N for channel setting is set in the frequency dividing number data terminal 11 after the rising of the frequency dividing output signal of the second cycle, the variable frequency divider 12 reads the frequency dividing number N at the rising of the second cycle. After that, the frequency dividing operation is performed.

An example of the phase difference detection circuit used here is shown in FIG. This is a known circuit, which is composed of nine NAND circuits 13 and compares the phases of the input signals A and B,
The state is output.

For example, when the phase of the input signal A leads the phase of the input signal B, a signal is output to the terminal X as shown in FIG. 8 (a), and when it is delayed, as shown in FIG. 8 (b). Then, the delay signal is output to the terminal Y.

Further, when the phases of both are the same, neither signal is output.

This circuit converts the output signal of the reference oscillator into the input signal A,
When the output signal of the variable frequency divider is used as the input signal B, it is possible to detect whether the phase of the output signal of the variable frequency divider is ahead or behind the phase of the output signal of the reference oscillator.

Therefore, when this is used in the present invention, after the frequency division number n _i of the variable frequency divider is set to an arbitrary frequency division number n ₁ in the first phase difference detection operation, the second phase difference detection operation is performed. in the case it is detected that the phase of the output signal of the variable frequency divider is advanced compared to that of the reference oscillator, to set a large n ₂ than n ₁ in n _i. On the other hand, if it is detected that there is a delay, then n _{1 is added} to n ₁
Set a smaller n ₂ .

As a method of setting n _i, a method of gradually increasing or decreasing n or a method of changing the amount of change to speed up the convergence of n _i can be considered. In either case, if the next n is controlled between the leading phase n and the trailing phase n, the value converges to a unique value.
At this time, the actual phase difference becomes one cycle or less of the input signal of the variable frequency divider. Approximately 1.3n for 800MHz band frequency synthesizer
sec.

In setting n, even if a tolerance of ± 1 is given to the setting of n in order to speed up the convergence time, the phase difference is sufficiently small and the frequency fluctuation hardly occurs. In addition, as a result of performing a convergence experiment of n _i using this phase difference detection circuit, it was confirmed that it converges to only one n.

The switch circuit 6 can be realized by using a known circuit in which a phase comparator 14 and a charge pump 15 are combined as a phase comparator as shown in FIG.

For example, as shown in (a), a control circuit 16 is inserted between the phase comparator 14 and the charge pump 15 to make the output of the charge pump 15 into high impedance, or as shown in (b) with a reset function. A method of using the phase comparator 17 to reset the internal state of the phase comparator so that the output signal of the charge pump 15 has a high impedance can be considered.

In order to confirm the operation of this embodiment, an experiment of intermittent operation was performed with an 80 MHz band frequency synthesizer.

FIG. 10 is a diagram for explaining the experimental results and shows the frequency fluctuation when the intermittent PLL operation in which the power source of the variable frequency divider and the reference oscillator is intermittently operated.

When this embodiment is not used, the frequency fluctuates greatly when the power is supplied as shown in FIG. 7A, but when this embodiment is used, there is almost no frequency fluctuation as shown in FIG. Not not.

Thus, it can be seen that the present invention operates as originally intended.

FIG. 11 shows an example of repeatedly turning on / off the power supply using this embodiment.

When the loop is continuously opened and closed, the switch circuit is first opened to hold the control voltage of the voltage controlled oscillator immediately before the loop is opened in the loop filter. When the power supply is intermittently operated, the power supply of the circuit is turned off for a certain period during this period. Next, before the switch circuit is connected and the loop is closed, the phase difference detection operation described in the explanation of the operation of the previous embodiment is performed one or more times to set the frequency division number n of the variable frequency divider. In the subsequent loop opening / closing operation, the same operation as described above is performed so that the phase difference between the output phase of the reference oscillator and the output phase of the variable frequency divider is always smaller than the specified value.

In particular, after the last n is set and the intermittent operation is started, there is a phase difference of a specified value or more between the phase of the output signal of the reference oscillator and the phase of the output signal of the variable frequency divider due to temperature fluctuations or voltage fluctuations. When it occurs, the phase difference is controlled as shown in this example so that the phase difference is always below the specified value.

〔The invention's effect〕

As described above, the present invention, when forming a loop,
The control voltage of the voltage controlled oscillator corresponding to the output oscillation frequency is held in the loop filter, and before the loop is closed, the frequency division number n _i of the variable frequency divider is set to n ₁ After resetting the state, the edge of the output of the reference oscillator is detected, the reset of the variable frequency divider is released, and the n ₁ frequency dividing operation is performed only in the first cycle, and after the second cycle, a constant cycle is performed. In the frequency synthesizer which operates the frequency division by N and closes the loop immediately after that, the phase difference between the output phase of the reference oscillator and the frequency division N of the variable frequency divider by the phase difference detection circuit during the operation of N frequency immediately after the reset is released. And the frequency division number of the variable frequency divider according to the result
After setting n _i to n ₂ and then resetting the variable frequency divider as the second phase difference detection operation, the same operation as the first time is performed, and even thereafter, the output phase of the reference oscillator is The same operation is performed until the phase difference of the output phase of the variable frequency divider becomes smaller than a specified value, and a closed loop is formed immediately after the final phase difference detection operation. A detection operation is performed so that the phase difference is always below a specified value.

Therefore, even if a temperature fluctuation or a voltage fluctuation occurs, the phase-locked process of the phase-locked loop is always established at an extremely high speed, and the frequency fluctuation is small.

That is, this is a practical method for intermittently operating the frequency synthesizer, and low power consumption of the frequency synthesizer can be achieved.

Also, while the input to the loop filter from the phase comparator is cut off, the loop filter is charged at high speed with the control voltage of the voltage controlled oscillator corresponding to another oscillation frequency, and the variable divider corresponding to that frequency is charged. High-speed channel switching is possible by setting the frequency division number N.

In addition, since the control circuit of the present invention can be configured by a digital IC, there is an advantage that it can be easily integrated into an LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic configuration of a conventional frequency synthesizer for intermittent operation, FIG. 2 is a diagram showing the procedure of intermittent operation, FIG. 3 is a time chart showing conventional control, and FIG. 4 is the present invention. FIG. 5 is a block diagram of an embodiment of the present invention, FIG. 5 is a time chart showing an example of operation of the embodiment, FIG. 6 is a time chart showing an example of a variable frequency divider configuration and its operation, and FIG. 7 is a phase difference detection circuit. Fig. 8 is a diagram showing an example of the configuration of Fig. 8, Fig. 8 is a diagram showing the relationship between the input signal and the output signal of the phase difference detection circuit, Fig. 9 is a diagram showing an example of the configuration of the switch circuit, and Fig. 10 is an experiment of intermittent operation. FIG. 11 is a diagram showing the resulting frequency fluctuation, and FIG. 11 is a diagram showing a control method when the power source of the embodiment of the present invention is repeatedly turned on / off. 1 ... Voltage controlled oscillator, 2,12 ... Variable frequency divider, 3 ... Reference oscillator, 4,14 ... Phase comparator, 5 ... Loop filter, 6 ... Switch circuit, 7 ... Phase difference detection Circuit, 8,16
...... Control circuit, 9 ... Power supply, 10 ... Power switch, 11 ...
… Division number data terminal, 13 …… NAND circuit, 15 …… Charge pump, 17 …… Phase comparator with reset function

Claims (1)

[Claims] 1. A voltage controlled oscillator and, the second period subsequent to receiving the output performs the dividing operation in the first period only the frequency division number n _i of the divided output after reset release of the voltage controlled oscillator N A variable frequency divider that performs a frequency division operation, a phase comparator that compares the phase of the output signal of the variable frequency divider and the phase of the output signal of the reference oscillator, and the voltage control that smooths the output of the phase comparator. An output of the variable frequency divider for controlling the loop, which is formed by a loop filter input to the oscillator and a switch circuit that cuts off the phase error signal of the phase comparator input to the loop filter. A phase difference detection circuit for detecting a phase difference between the phase of the signal and the phase of the output signal of the reference oscillator, opening the loop by disconnecting the switch circuit, and the power supply of all or part of the circuit Stop the supply, To restart the supply, the control voltage of the voltage-controlled oscillator corresponding to the oscillation frequency output held in the loop filter, before closing the loop, the division number n _i as a phase difference detection operation of the first n After setting ₁ to reset the internal state of the variable frequency divider, the edge of the output of the reference oscillator is detected, the reset of the variable frequency divider is released, and the n ₁ frequency division operation is performed only in the first cycle, From the second cycle onward, the frequency division operation is performed over a constant period by N, and during the frequency division operation, the phase difference detection circuit causes the position of the N division output phase of the variable frequency divider with respect to the output phase of the reference oscillator. The phase difference is detected, the frequency division number n _i of the variable frequency divider is set to n ₂ according to the result, and then the variable frequency divider is reset as the second phase difference detection operation. Do the same, and then do the same Carried out the operation,
A frequency synthesizer which forms a closed loop when the phase difference between the output phase of the reference oscillator and the output phase of the variable frequency divider becomes smaller than a specified value.