JP2001053260A - Solid-state image pickup element and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable enhancement of the sensitivity of a MOS slid-state image pickup element, complete transfer of the element at a low voltage and the like. SOLUTION: A solid-state image pickup element, formed by arraying pixels having a P-N junction sensor part 21 and at least a transistor 22 for readout is constituted into a structure, where a second conductivity charge storage region 62 constituting the sensor part 21 and a second conductivity source and drain regions 61 of the transistor 22 are formed in the side of the surface of a second conductivity semiconductor region 55, which is encircled by a first conductivity semiconductor well region 52 provided on the position of a prescribed depth from the surface of a substrate and a second first conductivity semiconductor well region 54 under an element isolating layer 53, holding a gate 57 of the transistor 22 between them and a first conductivity semiconductor region 71 is formed under the regions 61 (or under the source-drain regions, under the gate and under the region 62).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state image pickup device, particularly to a MOS type solid-state image pickup device and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a solid-state image pickup device, each unit pixel is constituted by having a sensor unit composed of a photodiode and a switching element, and reads out signal charges accumulated in the sensor unit by photoelectric conversion and converts the signal charges into a voltage or a current. 2. Description of the Related Art A so-called MOS type solid-state imaging device that converts and outputs a signal is known. In the MOS solid-state imaging device, for example, a MOS transistor is used as a switching element for selecting a pixel, a switching element for reading a signal charge, and the like. In addition, MOS transistors are used in peripheral circuits such as a horizontal scanning circuit and a vertical scanning circuit, and there is an advantage that manufacturing can be performed using a series of configurations with a switching element.

Conventionally, in a MOS type solid-state imaging device using a pn junction photodiode in a sensor section, each pixel has an element isolation layer formed by selective oxidation, a so-called LOCO.
S (local oxidation of sill)
(icon) layer to separate pixels in an XY matrix.

FIG. 12 shows a cross-sectional structure of a sensor section constituting a pixel of a conventional MOS type solid-state imaging device and a readout transistor as a switching element. This solid-state imaging device 1 has, for example, a p-type silicon semiconductor substrate 2
After the formation of the semiconductor well region 3 of the type, an element isolation layer (LOCOS layer) 4 is formed by selective oxidation.
A p-type channel stop region 5 is formed below,
A gate electrode 7 made of, for example, polycrystalline silicon is formed in a pixel region surrounded by the element isolation layer 4 with a gate insulating film 6 interposed therebetween, and an n-type is formed in one of the p-type semiconductor well regions 3 with the gate electrode 7 interposed therebetween. A semiconductor region 8 is formed to form a sensor section 9 by a photodiode, and an n-type source / drain region 10 of a read transistor is formed in the other region.

[0005]

Incidentally, in the above-mentioned conventional MOS type solid-state image pickup device 1, the n-type semiconductor region 8 constituting the sensor section (photodiode) 9 is provided.
Is the source / drain region 1 of the read transistor
Since the n-type impurity ions are formed by bombarding the p-type semiconductor well region 3 having a concentration as high as 0, it must be formed at a high concentration.

For this reason, the following problems have been encountered. (I) Complete depletion is difficult, and signal charges (electrons) in the sensor unit cannot be completely transferred at a low voltage. (Ii) The concentration of the n-type semiconductor region 8 in the sensor section 9 varies greatly, and a manufacturing margin cannot be obtained. (Iii) Since the n-type semiconductor region 8 of the sensor section 9 can be made only shallow, the sensitivity to red light is low.

[0007] In view of the above, the present invention provides an improvement in sensitivity,
An object of the present invention is to provide a solid-state imaging device which achieves complete transfer at a low voltage, easiness of manufacture, and the like, and a method of manufacturing the same.

[0008]

According to the present invention, there is provided a solid-state imaging device comprising: a first first conductivity type semiconductor well region at a predetermined depth position; and a second first conductivity type semiconductor well region below a device isolation layer. A second conductivity type charge accumulation region of the sensor unit and a second conductivity type source / drain region of the readout transistor are formed in the second conductivity type semiconductor region surrounded by. And the charge storage region,
A first conductivity type semiconductor region is formed below the gate and between the source / drain region and the second conductivity type semiconductor region.

[0009] The solid-state imaging device according to the present invention includes a first semiconductor well region surrounded by a first first conductivity type semiconductor well region at a predetermined depth and a second first conductivity type semiconductor well region below an element isolation layer. A second conductivity type charge accumulation region of the sensor unit and a second conductivity type source / drain region of the readout transistor are formed in the two conductivity type semiconductor region with the gate of the readout transistor interposed therebetween. A first conductive type semiconductor region is formed below and configured.

[0010] The solid-state imaging device according to the present invention includes a first semiconductor well region surrounded by a first semiconductor well region at a predetermined depth and a second semiconductor well region below an element isolation layer. A second conductivity type charge accumulation region of the sensor unit and a second conductivity type source / drain region of the read transistor are formed in the two conductivity type semiconductor region with the gate of the readout transistor interposed therebetween. It is formed by forming a one conductivity type semiconductor region.

According to the solid state imaging device of the present invention, one of the photoelectrically converted charges is accumulated in the charge accumulation region of the sensor unit. A second first conductivity type semiconductor well region is formed between the first first conductivity type semiconductor well region and the element isolation layer, and the sensor portion includes a charge accumulation region and a second conductivity type semiconductor region. Since the two-conductivity-type region is formed, the position of the pn junction formed between the second-conductivity-type region and the first first-conductivity-type semiconductor well region is deepened, and the spreading depth of the depletion layer is large. As a result, the photoelectric conversion efficiency in the sensor unit increases, and the sensitivity of red light increases.

[0012] By forming a charge storage region and a source / drain region with a gate interposed therebetween in a second conductivity type semiconductor region surrounded by the first and second first conductivity type semiconductor well regions, light is emitted. No matter where the light is incident on the sensor portion, under the source / drain region, or under the gate, if one of the charges is photoelectrically converted in the second conductivity type semiconductor region above the first first conductivity type semiconductor well region, Are collected in the charge accumulation region of the sensor unit, and the sensitivity can be improved. Since the charge accumulation region of the sensor portion is formed in the second conductivity type semiconductor region, the impurity concentration of the charge accumulation region can be reduced,
It is easy to completely deplete, and it is possible to completely transfer the signal charge of the sensor unit at a low voltage.

In a configuration in which the first conductivity type semiconductor region is formed under the charge storage region, under the gate, and between the source / drain region and the second conductivity type semiconductor region, the state in which the gate is closed by the first conductivity type semiconductor region is provided. , Leakage current between the charge storage region and the source / drain region is prevented, and the operation as a read transistor can be ensured. The first conductivity type semiconductor region is set to an impurity concentration that can be depleted, so that the charge photoelectrically converted in the second conductivity type semiconductor region below the first conductivity type semiconductor region is collected in the charge accumulation region. Becomes possible.

In the configuration in which the first conductivity type semiconductor region is formed below the source / drain regions, the second conductivity type semiconductor region is not provided below the charge storage region and the gate of the sensor unit, and thus the second conductivity type semiconductor region is not provided. The area of the semiconductor region is increased, and the sensitivity can be further improved.

In addition, the first conductivity type semiconductor region below the source / drain region prevents a leak current between the charge accumulation region and the source / drain in a state where the gate is closed, and secures the operation as a read transistor. it can. In this case, the impurity concentration of the first conductivity type semiconductor region is:
It can be set regardless of the depletion of the sensor section.

In the configuration in which the first conductivity type semiconductor region is formed under the gate, when the gate is closed, the first conductivity type semiconductor region separates the interface between the gate insulating film and the charge accumulation region of the sensor section. Therefore, the charge generated at the gate insulating film interface does not enter the charge accumulation region of the sensor portion but flows into the source / drain region side, and the dark current can be reduced.

With the first conductivity type semiconductor region under the gate,
It is difficult for the charge to flow out of the charge storage region to the source / drain region, the saturation potential of the charge storage region decreases, and the number of saturated charges increases. In addition, the charge accumulation region and the source / drain region are separated by the first conductivity type semiconductor region below the gate, so that the gate length can be shortened and miniaturization becomes possible.

A method for manufacturing a solid-state imaging device according to the present invention comprises:
After forming an element isolation layer of an insulating layer on a semiconductor substrate of the second conductivity type, the first first conductivity type semiconductor well region at a predetermined depth position in the semiconductor substrate and the first first semiconductor well region below the element isolation layer are formed. A second first conductivity type semiconductor well region reaching the conductivity type semiconductor well region; and a second first conductivity type semiconductor well region at a predetermined depth in the second conductivity type semiconductor region surrounded by the first and second first conductivity type semiconductor well regions. A first conductivity type semiconductor region is formed, and then a second conductivity type source / drain region reaching the first conductivity type semiconductor region across the gate electrode and a second conductivity type charge storage region of the sensor portion are formed. .

The method for manufacturing a solid-state imaging device according to the present invention comprises:
After forming an element isolation layer of an insulating layer on a semiconductor substrate of the second conductivity type, a first well of the first conductivity type semiconductor at a predetermined depth position in the semiconductor substrate and a first first region below the element isolation layer are formed. A first first conductive type semiconductor well region reaching the conductive type semiconductor well region, and a first conductive type semiconductor well region surrounded by the first and second first conductive type semiconductor well regions.
Forming a conductive type semiconductor region, and then forming a second conductive type source / drain region and a first conductive type semiconductor region below the source / drain region in one region with the gate electrode interposed therebetween, and forming the second conductive type semiconductor region in the other region. A charge accumulation region of the second conductivity type of the sensor unit is formed.

According to the method of manufacturing a solid-state imaging device according to the present invention, each region constituting a pixel can be formed in a self-aligned manner.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state imaging device according to the present invention has p
A solid-state imaging device in which an n-junction sensor portion and pixels having at least a readout transistor are arranged, wherein a first first conductivity type semiconductor well region at a predetermined depth position and a second under a device isolation layer are provided. A second-conductivity-type charge storage region constituting a sensor section with a gate of the read-out transistor interposed therebetween, on the surface side of the second-conductivity-type semiconductor region surrounded by the first-conductivity-type semiconductor well region; A first conductive type source / drain region, a gate lower region, and a charge storage region; and a first conductive type semiconductor region between the second conductive type semiconductor region and the second conductive type semiconductor region.
The structure is such that a conductive semiconductor region is formed.

A solid-state image pickup device according to the present invention is a solid-state image pickup device in which a pn-junction sensor section and pixels having at least a readout transistor are arranged, wherein the first first conductivity type at a predetermined depth position is provided. A sensor section is formed on the surface side of the second conductivity type semiconductor region surrounded by the semiconductor well region and the second first conductivity type semiconductor well region below the element isolation layer with the gate of the read transistor interposed therebetween. A charge accumulation region of the second conductivity type and a source / drain region of the second conductivity type of the read transistor are formed, and a semiconductor region of the first conductivity type is formed below the source / drain region.

The solid-state image pickup device according to the present invention is a solid-state image pickup device in which a pn junction type sensor section and pixels having at least a readout transistor are arranged, wherein the first first conductivity type at a predetermined depth position is provided. A sensor section is formed on the surface side of the second conductivity type semiconductor region surrounded by the semiconductor well region and the second first conductivity type semiconductor well region below the element isolation layer with the gate of the read transistor interposed therebetween. A charge accumulation region of the second conductivity type and a source / drain region of the second conductivity type of the reading transistor are formed, and a semiconductor region of the first conductivity type is formed below the gate. In this solid-state imaging device, the first conductivity type semiconductor region can be formed below the source / drain region of the readout transistor.

In each of the solid-state imaging devices described above, the first conductivity type semiconductor region can be formed on the surface of the second conductivity type charge storage region.

A method for manufacturing a solid-state imaging device according to the present invention
Forming a device isolation layer of an insulating layer on the surface of the second conductivity type semiconductor substrate; forming a first first conductivity type semiconductor well region at a predetermined depth position in the semiconductor substrate; Forming a second first conductivity type semiconductor well region so as to reach the first first conductivity type semiconductor well region;
Forming a first conductivity type semiconductor region at a predetermined depth position in the second conductivity type semiconductor region surrounded by the second first conductivity type semiconductor well region; Forming a second conductivity type source / drain region and a second conductivity type charge accumulation region constituting a sensor portion so as to reach the semiconductor region;

A method for manufacturing a solid-state image pickup device according to the present invention comprises:
Forming a device isolation layer of an insulating layer on the surface of the second conductivity type semiconductor substrate; forming a first first conductivity type semiconductor well region at a predetermined depth position in the semiconductor substrate; Forming a second first conductivity type semiconductor well region so as to reach the first first conductivity type semiconductor well region;
Forming a first conductivity type semiconductor region over the entire surface of the second conductivity type semiconductor region surrounded by the second first conductivity type semiconductor well region; Forming a source / drain region of the first type and a semiconductor region of the first conductivity type below the source / drain region, and forming a charge storage region of the second conductivity type constituting the sensor section in the other region.

FIG. 1 shows a configuration of an example of a MOS solid-state imaging device according to an embodiment of the present invention.

The solid-state imaging device 20 includes a photodiode (that is, a pn junction type sensor unit) 21 for performing photoelectric conversion and a vertical selection switch element (for example, a MOS) for selecting a pixel.
Transistor) 23 and readout switch element (for example, MOS transistor) 22, an imaging area in which a plurality of unit pixels 24 are arranged in a matrix, and control electrodes (so-called gates) of vertical select switch element 23 for each row. vertical scanning pulse .phi.V [.phi.V ₁ to the vertical selection line 25 electrodes) are commonly connected, ‥‥ φV _m, ‥‥
φV _{m + k} , ‥‥], a vertical signal line 27 to which the main electrode of the readout switch element 22 is commonly connected for each column, and a vertical selection switch element for each column. Read pulse line 28 connected to the main electrode 23
And a horizontal switch element (for example, a MOS transistor) 3 having a main electrode connected to the vertical signal line 27 and the horizontal signal line 29.
0, a control electrode (so-called gate electrode) of the horizontal switch element 30, a horizontal scanning circuit 31 connected to the read pulse line 28, and an amplifier 32 connected to the horizontal signal line 29.

In each unit pixel 24, one main electrode of the readout switch element 22 is connected to the photodiode 21, and the other main electrode is connected to the vertical signal line 27. Further, one main electrode of the vertical selection switch element 23 is connected to a control electrode (so-called gate electrode) of the read switch element 22, and the other main electrode is connected to the read pulse line 28 and its control electrode (so-called control electrode). (Gate electrode) is connected to the vertical selection line 25.

The horizontal scanning pulse .phi.H to the control electrode (so-called gate electrode) of each horizontal switch element 30 from the horizontal scanning circuit 31 _{[φH 1, ‥‥ φH n, φH} n + 1, ‥‥ ] with is supplied, the horizontal readout pulse .phi.H ^R [.phi.H ^R ₁ to the read pulse line _{^{28, ‥‥ φH R n, φH}} R n + 1,
‥‥] is supplied.

The basic operation of the solid-state imaging device 20 is as follows. The vertical scanning pulse φV from the vertical scanning circuit 26
_m and the read pulse φH ^R _n from the horizontal scanning circuit 31
The vertical selection switch element 23 which receives the, the pulses .phi.V _m, making the pulse of the product of .phi.H ^R _n, by controlling the control electrode of the read switching element 22 by the pulse of this product, photoelectric photodiode 21 The converted signal charge is read out to the vertical signal line 27. This signal charge is supplied to the horizontal scanning pulse φH from the horizontal scanning circuit 31 during the horizontal video period.
_The signal is output to a horizontal signal line 29 through a horizontal switch element 30 controlled by _n, and is converted into a signal voltage by an amplifier 32 connected thereto and output.

The configuration of the unit pixel 24 is not limited to the above example, and various configurations such as those shown in FIGS. In FIG. 2, the unit pixel 24 includes the photodiode 21 and the readout MOS transistor 2 connected to the photodiode 21.
The other main electrode of the read MOS transistor 22 is connected to the vertical signal line 27, and its gate electrode is connected to the vertical selection line 25.

In FIG. 3, the unit pixel 24 includes the photodiode 21, the read MOS transistor 35, and the F
D (floating diffusion) amplifier MOS transistor 36 and FD reset MOS transistor 37
And a vertical selection MOS transistor 38.
Then, one main electrode of the read MOS transistor 35 is connected to the photodiode 21 and the other main electrode is connected to one main electrode of the FD reset MOS transistor 37.
7 and the vertical selection MOS transistor 38
FD amplifier MOS transistor 36 between one main electrode of
Is connected, and the gate electrode of the FD amplifier MOS transistor 36 is connected to the FD which is the connection point between the read MOS transistor 35 and the FD reset MOS transistor 37.
(Floating diffusion) section. The gate electrode of the read MOS transistor 35 is connected to the vertical read line 41, the other main electrode of the FD reset MOS transistor 37 is connected to the power supply VDD, and the gate electrode is connected to the horizontal reset line 42, for vertical selection. The other main electrode of MOS transistor 38 is connected to vertical signal line 43, and its gate electrode is connected to vertical selection line 4.
4 is connected.

FIG. 4 shows a pixel 24 in the solid-state imaging device 20 of FIG.
One embodiment of a region including a transistor 22 is shown.
The pixel 241 according to the present embodiment has a first conductivity type, for example, an n-type silicon semiconductor substrate 51 at a predetermined depth position in the silicon semiconductor substrate 51.
A first semiconductor well region 52 of conductivity type, for example, p-type is formed, and an element isolation layer (so-called LOCOS layer) 53 is formed on the surface of the semiconductor substrate 51 by selective oxidation for pixel isolation. A second p-type semiconductor well region 54 that reaches below the first p-type semiconductor well region 52
Is formed. The concentration of the n-type semiconductor substrate 51 is, for example, 1
0 ¹⁴ ~10 ¹⁶ cm ^-3 or so, the concentration of the first p-type semiconductor well region 52, for example 10 ¹⁶ ~10 ¹⁸ cm ^-3 or so, the second
The concentration of the p-type semiconductor well region 54 is, for example, 10 ¹⁶ to
It can be about 10 ¹⁸ cm ^-3 .

The second p-type semiconductor well region 54 is formed so as to partially extend into a pixel region (a so-called active region) surrounded by the element isolation layer 54. That is, the second p-type semiconductor well region 54 is formed in a lattice shape so as to exclude a portion corresponding to the pixel region.

First and second p-type semiconductor well regions 52
And 54, on the n-type semiconductor region 55, which is the same low concentration as the semiconductor substrate 52,
For example, a gate electrode 57 of the read MOS transistor 22 is formed via a gate insulating film 56 made of, for example, SiO ₂ . Reference numeral 58 denotes a side wall formed of, for example, SiO ₂ on the side wall of the gate electrode 57.

Then, a low-concentration p-type semiconductor region 60 is formed at a predetermined depth position in the n-type semiconductor region 55 so as to cover the entire pixel region, and is in contact with the p-type semiconductor region 60. An n-type source / drain region 61 of the read MOS transistor 22 is formed on one side of the surface of the n-type semiconductor region 55 with a gate electrode 57 interposed therebetween, and an n-type semiconductor region 62 forming the sensor section 21 on the other side.
Is formed. The concentration of the p-type semiconductor region 60 is, for example, 1
It can be about 0 ¹⁵ to 10 ¹⁶ cm ^-3 .

The source / drain region 61 is formed at a normal high concentration. N-type semiconductor region 62 of sensor unit 21
Becomes a substantial charge storage region. The impurity concentration of the n-type charge storage region 62 is set lower than that of the source / drain region 61 and higher than that of the low-concentration n-type semiconductor region 55. The concentration of the source / drain region 61 is, for example, 10 ¹⁹
cm ⁻³ or more, the concentration of the n-type semiconductor region 62 of the sensor unit 21 can be, for example, about 10 ¹⁷ cm ⁻³ . In the sensor section 21, the low-concentration n-type semiconductor region 55 and the first p-type
A pn junction j is formed between the p-type semiconductor well regions 52, so that the depletion layer of the sensor section 21 extends to the first p-type semiconductor well region 52 during operation.

The p-type semiconductor region 60 separates the source / drain region 61 and the charge storage region 62 from the low-concentration n-type semiconductor region 55 when the gate is closed and in the off state. When the photoelectrically converted signal charges are stored in the memory cell 62, the density is controlled to be low enough to be completely depleted.

Under the gate electrode 57, the p-type semiconductor region 60
Is formed in the low-concentration p-type semiconductor region 63 by impurity diffusion from the substrate. Note that the p-type semiconductor region 63 can be positively formed at a desired concentration by ion implantation. further,
In the sensor section 21, a p-type semiconductor region 64 having a relatively high concentration, for example, about 10 ¹⁸ cm ⁻³ is preferably formed on the surface of the n-type charge storage region 62, that is, at the interface with the insulating film 56. .

FIGS. 6 and 7 show a method of manufacturing the pixel 241 of FIG. First, as shown in FIG. 6A, a low-concentration n-type semiconductor substrate 51 is prepared, and an element isolation layer 53 is formed on the surface by selective oxidation.

Next, as shown in FIG. 7B, the element isolation layer 5 is formed.
3, a first p-type semiconductor well region 52 is formed at a predetermined depth position of the semiconductor substrate 51 by ion-implanting p-type impurities into the entire surface including the pixel region partitioned by the element isolation layer 53. A second p-type semiconductor well region 54 reaching the first p-type semiconductor well region 52 is formed below the element isolation layer 53 except for the pixel region, and further, the first and second p-type semiconductor well regions 52 and N-type semiconductor region 55 surrounded by 53
A low concentration p-type semiconductor region 60 is formed by ion-implanting a p-type impurity at a predetermined depth position in the inside. This area 60
May be overlapped with the region 54 because of low density, and strict mask alignment is not required.

Next, as shown in FIG. 7C, for example, S is formed on the n-type semiconductor region 55 on the surface side of the p-type semiconductor region 60.
A gate electrode 57 made of, for example, polycrystalline silicon is formed via a gate insulating film 56 made of iO ₂ or the like, and then a p-type impurity is ion-implanted in a self-aligned manner and selectively with the gate electrode 57 interposed therebetween to form a p-type An n-type source / drain region 61 and an n-type charge storage region 62 are formed so as to reach the region 60.

Next, as shown in FIG. 7D, the gate electrode 5
An insulating side wall 58 made of, for example, SiO ₂ or the like is formed on the side wall 7. Then, the n-type charge storage region 62
A high concentration p-type semiconductor region 64 is formed in a self-aligned manner by ion-implanting a p-type impurity into the surface of the substrate.

According to the solid-state imaging device including the pixel 241 according to the present embodiment, one of the electric charges photoelectrically converted by the light incident on the pixel 241, in this example, the electron which becomes the signal electric charge The charge is stored in the n-type charge storage region 62. The signal charge stored in the charge storage region 62 is read to the source / drain region 61 when the gate of the read MOS transistor 22 is turned on at the time of reading.

In the sensor section 21, a so-called n-type region including a charge storage region 62 and a low-concentration n-type semiconductor region 55 is provided.
P formed between first p-type semiconductor well region 52
Since the position of the n-junction j is deepened, the depth of the depletion layer is increased, the photoelectric conversion efficiency in the sensor unit 21 is increased, and the sensitivity of red light is increased.

Since the charge storage region 62 of the sensor section 21 is formed in the low-concentration n-type semiconductor region 55, the charge storage region 62 can be made to have a low concentration, and it is easy to completely deplete. 21 can be completely transferred to the source / drain region 61. Therefore, an image with little noise and no afterimage can be obtained.

Since the charge storage region 62 can be formed at a low concentration, a manufacturing margin can be widened and the manufacturing becomes easy.

Since the low-concentration p-type semiconductor region 60 is formed below the charge storage region 62 and the source / drain regions,
When the gate is off, a leak current between the charge storage region 62 and the source / drain region 61 can be prevented, and the operation as the read MOS transistor 22 can be performed.

In the sensor section 21, the n-type charge storage region 6
When the high-concentration p-type semiconductor region 64 is formed on the surface of the semiconductor device 2, electrons generated at the interface between the sensor portion 21 and the insulating film 56 are recombined in the p-type semiconductor region 64 and enter the charge storage region 62. There is no. When the channel region 63 under the gate is of p-type, the gate insulating film 56
Electrons generated at the interface with the semiconductor do not enter the charge storage region 62,
It flows into the source / drain region 61. Therefore, the dark current can be reduced.

According to the manufacturing method of this embodiment, p
Since each of the regions 61, 62, and 64 can be formed by selectively and self-aligning ion implantation of the n-type and n-type impurities, and strict mask alignment is not required for the region 60, FIG. Can be accurately and easily manufactured with the MOS type solid-state imaging device having the pixel 241 shown in FIG.

In the above-described pixel 241, since the low-concentration p-type semiconductor region 60 is formed in the n-type semiconductor region 55 constituting the sensor section 21, the pixel 241 is located on the line AA in FIG. 5), the barrier 6 against electrons e in the p-type semiconductor region 60 as shown in FIG.
A potential distribution 67 having 6 is obtained. Therefore, electrons e generated by photoelectric conversion at a deep position in the n-type semiconductor region 55 are unlikely to enter the charge storage region 62. Although the sensitivity of the sensor unit 21 of the pixel 241 can be improved as compared with the related art, it is desired to improve the barrier 66 to further improve the sensitivity.

FIG. 8 shows another embodiment of the solid-state imaging device 20 shown in FIG. 1 in which the pixel 24, in particular, the sensor unit 21 and the readout MOS transistor 22 are included.

As described above, the pixel 242 according to the present embodiment has a first conductivity type, for example, a p-type first pixel at a predetermined depth position in a second conductivity type, for example, an n-type silicon semiconductor substrate 51.
Is formed, and an element isolation layer (so-called LOCOS layer) 53 is formed on the surface of the semiconductor substrate 51 by selective oxidation for pixel isolation, and a first p-type semiconductor well is formed under the element isolation layer 53. The second reaching area 52
Is formed. Also in this case, the second p-type semiconductor well region 54 is
It is formed so as to extend into a pixel area (so-called active area) surrounded by 3. The concentration of the n-type semiconductor substrate 51 is, for example, about 10 ¹⁴ to 10 ¹⁶ cm ⁻³ , the concentration of the first p-type semiconductor well region 52 is, for example, about 10 ¹⁶ to 10 ¹⁸ cm ⁻³ , and the second p-type semiconductor well region is The concentration of 54 is, for example, 1
It can be about 0 ¹⁶ to 10 ¹⁸ cm ^-3 .

First and second p-type semiconductor well regions 52
And the same low-concentration n-type semiconductor as the substrate 51 surrounded by
On the body region 55, for example, SiO_TwoGate insulation
For reading using, for example, polycrystalline silicon through the film 56
A gate electrode 57 of the MOS transistor is formed. 5
8 is, for example, SiO 2 formed on the side wall of the gate electrode 57. _Two
And the like. n-type semiconductor region
55 is the concentration of the substrate 51 except for a little diffusion from the surroundings.
Is the same as

In this embodiment, the gate electrode 57
The n-type source / drain region 6 of the read MOS transistor is provided in one region of the n-type semiconductor region 55 with the
1 is formed, a p-type semiconductor region 71 is formed below the source / drain region 61, and an n-type semiconductor region constituting a sensor unit (photodiode) is formed in the other region of the n-type semiconductor region 55, that is, a charge. An accumulation region 62 is formed. The concentration of the n-type source / drain region 61 is, for example, 1
0 ¹⁹ cm ⁻³ or more, the concentration of the p-type semiconductor region 71 is, for example, 1
The density of the charge storage region 62 can be set to, for example, about 10 ¹⁷ cm ^−3, for example, about 0 ¹⁶ to 10 ¹⁸ cm ⁻³ .

A p-type semiconductor region 64 having a high concentration, for example, about 10 ¹⁸ cm ⁻³ is formed on the surface of the charge storage region 62. Furthermore, preferably the gate electrode 57
Below the desired concentration, ie a relatively low concentration, for example 10 ¹⁶ c
A p-type semiconductor region 63 of about m ⁻³ is formed. As shown, the n-type charge storage region 62 is formed so as to be partially connected to the p-type semiconductor region 63.

9 to 11 show a method of manufacturing the pixel 242 shown in FIG. First, as shown in FIG. 9A, a low-concentration n-type semiconductor substrate 51 is prepared, and an element isolation layer 53 is formed on the surface thereof by selective oxidation.

Next, as shown in FIG. 9B, the element isolation layer 5
3 and a first p-type semiconductor well region 52 is formed by ion implantation at a predetermined depth position of the semiconductor substrate 51 over the entire surface including the pixel region partitioned by the element isolation layer 53, and excluding the pixel region. A second p-type semiconductor well region 54 reaching the first p-type semiconductor well region 52 is formed below the isolation layer 53 by ion implantation. Further, an element is formed on the surface of the pixel region partitioned by the element isolation layer 53. P-type semiconductor region 6 having a relatively low concentration by ion implantation in a self-aligned manner using isolation layer 53 as a mask.
Form 3 First and second p-type semiconductor well regions 5
2 and 54 and the same low-concentration n-type semiconductor region 5 as the semiconductor substrate 51 so as to be surrounded by the p-type semiconductor region 63 on the surface.
There are five.

Next, as shown in FIG. 10C, a gate electrode 57 made of, for example, polycrystalline silicon is formed on the pixel region, that is, on the p-type semiconductor region 63 via a gate insulating film 56 made of, for example, SiO _2. .

Next, as shown in FIG. 10D, the element isolation layer 5 is formed in one of the pixel regions with the gate electrode 57 interposed therebetween.
The n-type high-concentration source / drain region 61 of the read MOS transistor and the p-type semiconductor region 71 thereunder are formed by ion implantation in a self-aligned manner using the gate electrode 3 and the gate electrode 57 as a mask, and the other region of the pixel region is formed. An n-type charge storage region 62 constituting the sensor unit 21 is formed in a self-aligned manner by ion implantation using the element isolation layer 53 and the gate electrode 57 as a mask.

Next, for example, an SiO ₂ film is deposited on the entire surface and etched to form an insulating sidewall 58 on the side wall of the gate electrode 57 as shown in FIG. 11E.

Next, as shown in FIG. 11F, the side wall 58 is formed on the surface of the other region of the pixel region with the gate electrode 57 interposed therebetween so as to reach the n-type charge storage region 62.
A p-type semiconductor region 64 having a higher concentration than the p-type semiconductor region 63 under the gate is formed by ion implantation in a self-aligned manner using the element isolation layer 53 as a mask.

According to the solid-state imaging device having the pixel 242 according to the present embodiment, as described above, one of the charges photoelectrically converted by the light incident on the pixel 242, in this example, the electron serving as the signal charge. Is stored in the n-type charge storage region 62 of the sensor section 21. The signal charge stored in the charge storage region 62 is read to the source / drain region 61 when the gate of the read MOS transistor 22 is turned on at the time of reading.

In the sensor section 21, a so-called n-type region including a charge storage region 62 and a low-concentration n-type semiconductor region 55 is provided.
P formed between first p-type semiconductor well region 52
Since the position of the n-junction is deep, the depth of the depletion layer is large, the photoelectric conversion efficiency in the sensor unit 21 is increased, and the sensitivity of red light is increased.

Further, light is emitted below the source / drain region 61,
Irrespective of whether the light is incident on the sensor section 21 or under the gate, if the photoelectric conversion is performed in the low-concentration n-type semiconductor area 55 on the deep first p-type semiconductor well area 52, the electrons serving as the signal charges are converted to the sensor section. 21 are collected in the charge storage region 62.
Therefore, the sensitivity is further improved.

Since the p-type semiconductor region 71 is formed below the n-type source / drain region 61 of the read MOS transistor 22, the charge accumulation region 62 and the source / drain region of the sensor section 21 are turned off when the gate is off. 6
The leakage current between 1 is suppressed, and the operation as the read MOS transistor 22 can be performed.

The p-type semiconductor region 60 shown in FIG.
Since it is also formed below the sensor section 21, it is necessary to make the density extremely low, so that strict density control is required. However, the p-type semiconductor region 71 of this example is
Since it is formed only below the drain region and is not formed on the sensor section 21 side, the concentration is only required to prevent leakage current, and it is not particularly necessary to strictly control the concentration. Therefore, the manufacturing margin is widened.

Since the p-type semiconductor region 71 is formed only below the source / drain region 61, n
The type region becomes large, and electrons generated by photoelectric conversion at a deep position in the n-type semiconductor region 55 also easily enter the charge storage region 62, so that the sensitivity can be further improved as compared with the pixel 241 of FIG.

Since the low-concentration p-type semiconductor region 63 is formed under the gate, the potential of the sensor section 21, that is, the charge storage region 62 of the photodiode can be lowered, and the voltage can be reduced. That is, if the gate is open during light reception, electrons leak from the charge storage region 62 of the sensor unit 21. Therefore, unless the potential of the charge storage region 62 is increased by the amount of leakage (for example, about 0.5 V), Cannot be accumulated. However, since the p-type semiconductor region 63 is formed under the gate, the gate is closed at the time of light reception, and electrons are accumulated in the sensor unit without leaking. Until the voltage is small, for example, 0
Electrons can be stored up to a position close to V. Therefore, the voltage of the charge storage region 62 can be reduced, and for example, even at about 1 V, it can function as a photodiode.
Low voltage is possible. That is, if the potential under the gate is, for example, about 0.5 V, electrons can only be stored in the photodiode up to 0.5 V. However, if the bottom of the gate is closed to 0V, the photodiode
Can store up to electrons. Therefore, the potential depth of the photodiode to store the same number of electrons is 1.5 V in the former, but only 1.0 V in the latter. The closer to 0V, the larger the capacitance, so
Even with the same amplitude of 1 V, more electrons are accumulated.

The threshold voltage _{Vth of the} gate can be freely controlled by the p-type semiconductor region 63. And
The read gate voltage can be reduced, and operation can be performed at a low voltage.

When the gate is off, the gate insulating film interface under the gate (so-called channel region)
And the charge accumulation region 62 of the sensor unit 21
Generated from the interface between the gate insulating film under the gate and the sensor section 2,
1 does not enter the charge accumulation region 62 but flows into the source / drain region 61. Therefore, dark current can be reduced.

The presence of the p-type semiconductor region 63 makes it difficult for electrons to flow out of the charge storage region 62 of the sensor section 21 to the source / drain region 61, so that the charge storage region 62
The saturation potential of the sensor unit 2
1 increases, and the number of accumulated saturated electrons can be increased. Charge storage region 62 of sensor unit 21
Can reduce the depletion potential, thereby reducing white spots and increasing the yield.

Since the source / drain region 61 and the charge storage region 62 are separated from each other by the p-type semiconductor region 63 having an appropriate concentration, the depletion layer from both the regions 61 and 62 is prevented from extending to cause punch-through. The gate length can be shortened, and the pixel can be miniaturized.

Since the high-concentration p-type semiconductor region 64 is provided on the charge storage region 62 of the sensor section 21, electrons generated at the interface between the p-type semiconductor region 64 and the insulating film are generated in the p-type semiconductor region 63. It is recombined and disappears, and dark current can be reduced.

The n-type charge accumulation region 62 in the sensor section 21 is a low-concentration n-type semiconductor region 5 of the same level as the substrate 51.
5, it can be formed stably at a low concentration.
Therefore, it is easy to completely deplete the charge storage region 62, and the signal charge can be completely transferred at a low voltage. Therefore, an image with little noise and no afterimage can be obtained.

Since the charge storage region 62 can be formed at a low concentration, a manufacturing margin can be widened and manufacturing becomes easy.

In the structure of FIG. 8, the p-type semiconductor region 63 under the gate and the p-type semiconductor region 6 on the charge storage region 62
Even when the step 4 is omitted, effects such as an increase in sensitivity, a reduction in voltage, and an increase in a manufacturing margin of the p-type semiconductor region 71 below the charge storage region 62 and the source / drain region 61 are obtained. Note that even if the p-type semiconductor region 63 under the gate is not actively formed, the impurity diffusion from the p-type semiconductor region 71 can be diffused to below the gate, and the region under the gate can be made p-type. By forming the p-type under the gate, the p-type semiconductor region 6 is formed.
The same effect as in the case of forming No. 3 can be expected.

According to the manufacturing method of the present embodiment, each of the regions 61, 62, 63, 64, 71 is formed with the element isolation layer 53,
Since the gate electrode 57 and the sidewall 58 can be formed by ion implantation in a self-aligned manner using the mask as a mask,
A CMOS solid-state imaging device including the pixel 242 shown in FIG. 8 can be manufactured accurately and easily.

In addition, the present invention can be applied to all kinds of pixels of the MOS type solid-state imaging device using the readout switch element.

[0081]

According to the solid-state imaging device of the present invention, the first well of the first conductivity type semiconductor at a predetermined depth and the second well of the first conductivity type under the element isolation layer are surrounded. Forming, on the surface of the second conductive type semiconductor region, a charge storage region of the second conductive type and a source / drain region of the second conductive type of the readout transistor, with the gate interposed therebetween, thereby forming the sensor unit. , The depth of depletion of the depletion layer increases, the photoelectric conversion efficiency increases, and the sensitivity of red light can be improved. At the same time, the whole second conductivity type semiconductor region surrounded by the first conductivity type semiconductor well region becomes one of the second conductivity type regions constituted by the photodiode serving as the sensor portion, thereby further improving the sensitivity. Can be.

When the first conductivity type semiconductor region is formed between the charge storage region, the region under the gate and the source / drain region, and the second conductivity type semiconductor region, the leakage current between the charge storage region and the source / drain region And the operation of the read transistor is ensured.

When the first conductivity type semiconductor region is formed only under the source / drain region, a leak current between the charge storage region and the source / drain is prevented, and the operation of the read transistor is ensured. In addition, since the first conductivity type semiconductor region is not provided under the charge storage region, the area of the second conductivity type semiconductor region is further increased, so that the sensitivity can be further improved. Further, when the first conductivity type semiconductor region is formed only under the source / drain regions, the concentration of the first conductivity type semiconductor region can be set only in consideration of the prevention of leakage current. This facilitates manufacturing, increases the manufacturing margin, and facilitates manufacturing.

When the first conductivity type semiconductor region is formed under the gate, when the gate is off, the first conductivity type semiconductor region separates the interface between the gate insulating film under the gate and the charge storage region from each other. As a result, the charge generated from the gate insulating film interface does not enter the charge accumulation region but flows to the source / drain region side, so that the dark current can be reduced.

By providing the first conductivity type semiconductor region under the gate, when the gate is in the off state, it is difficult for signal charges to flow from the charge storage region of the sensor section to the source / drain regions, and the saturation potential of the charge storage region is reduced. The saturation charge number can be increased by increasing the capacitance. Since the depletion potential of the charge storage region can be reduced, white spots are reduced, and the yield can be improved.

The threshold voltage _Vth can be controlled by the first conductivity type semiconductor region under the gate, and the read gate voltage can be reduced, so that operation can be performed at a low voltage. Since the charge accumulation region and the source / drain region of the sensor section are separated by the first conductivity type semiconductor region under the gate, there is no punch-through, the gate length can be reduced, and the pixel can be miniaturized.

When the first conductivity type semiconductor region is formed on the second conductivity type charge accumulation region of the sensor portion, charges generated at the interface of the insulating film in the sensor portion recombine in the first conductivity type semiconductor region. Since it does not enter the charge accumulation region of the sensor unit, the dark current can be reduced.

When the charge accumulation region of the second conductivity type has a low concentration
Since the charge accumulation region is formed in the conductive semiconductor region, the charge accumulation region can be formed stably at a low concentration, can be easily completely depleted, and can completely transfer signal charges at a low voltage. . Therefore, an image with little noise and no afterimage can be provided.

According to the method of manufacturing a solid-state imaging device according to the present invention, a solid-state imaging device having the above characteristics can be manufactured easily and with high precision in a self-aligned manner.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a configuration diagram showing another example of a unit pixel applied to the solid-state imaging device of the present invention.

FIG. 3 is a configuration diagram showing another example of a unit pixel applied to the solid-state imaging device of the present invention.

FIG. 4 is a cross-sectional view showing one embodiment of a pixel portion of the solid-state imaging device according to the present invention.

FIG. 5 is a potential distribution diagram on the line AA in FIG. 4;

6A to 6B are manufacturing process diagrams of the solid-state imaging device of FIG. 4;

7A to 7D are manufacturing process diagrams of the solid-state imaging device of FIG. 4;

FIG. 8 is a cross-sectional view showing another embodiment of the pixel portion of the solid-state imaging device according to the present invention.

9A to 9B are manufacturing process diagrams of the solid-state imaging device of FIG. 8;

10A to 10D are manufacturing process diagrams of the solid-state imaging device of FIG. 8;

11A to 11F are manufacturing process diagrams of the solid-state imaging device of FIG. 8;

FIG. 12 is a cross-sectional view of a pixel portion of a conventional solid-state imaging device.

[Explanation of symbols]

20 ‥‥ MOS type solid-state imaging device, 21 ‥‥ sensor unit (photodiode), 12 ‥‥ readout MOS transistor, 13 ‥‥ vertical selection MOS transistor, 1
4, 141, 142 unit pixels, 51 n-type semiconductor substrate, 52 first p-type semiconductor well region, 53
Element isolation layer (LOCOS layer), 54 ‥‥ second p-type semiconductor well region, 55 ‥‥ n-type semiconductor region, 56 ‥‥ gate insulating film, 57 ‥‥ gate electrode, 60 ‥‥ p-type semiconductor region, 61 ‥‥ n-type source / drain region, 62 ‥‥ n-type charge storage region, 63 ‥‥ p-type semiconductor region, 64 ‥‥ p-type semiconductor region, 71 ‥‥ p-type semiconductor region

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Ryoji Suzuki 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Takahisa Ueno 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F term (reference) 4M118 AA01 AA03 AA05 AB01 BA14 CA04 CA18 EA01 EA06 EA07 EA14 EA15 FA06 FA26 FA28 FA33 5C024 AA01 CA12 CA16 CA31 FA01 FA11 GA31

Claims (9)

[Claims] 1. A solid-state imaging device in which a pn-junction sensor unit and pixels having at least a readout transistor are arranged, comprising: a first first conductivity type semiconductor well region at a predetermined depth position;
A second conductive layer forming the sensor section on the surface side of the second conductive type semiconductor region surrounded by the second first conductive type semiconductor well region below the element isolation layer with the gate of the read transistor interposed therebetween. A charge storage region, and a second conductivity type source / drain region of the readout transistor. The charge storage region, the gate and the source / drain region, the second conductivity type semiconductor region, A solid-state imaging device comprising a first conductivity type semiconductor region formed therebetween. 2. The solid-state imaging device according to claim 1, wherein a first conductivity type semiconductor region is formed on a surface of the second conductivity type charge accumulation region. 3. A solid-state imaging device in which a pn junction sensor unit and pixels having at least a readout transistor are arranged, a first well of a first conductivity type semiconductor at a predetermined depth position,
A second conductive layer forming the sensor section on the surface side of the second conductive type semiconductor region surrounded by the second first conductive type semiconductor well region below the element isolation layer with the gate of the read transistor interposed therebetween. A charge storage region of a first conductivity type, a source / drain region of a second conductivity type of the read transistor, and a semiconductor region of a first conductivity type formed below the source / drain region. Imaging device. 4. The solid-state imaging device according to claim 3, wherein a first conductivity type semiconductor region is formed on a surface of the second conductivity type charge storage region. 5. A solid-state imaging device in which a pn junction sensor unit and pixels having at least a readout transistor are arranged, comprising: a first first conductivity type semiconductor well region at a predetermined depth;
A second conductive layer forming the sensor section on the surface side of the second conductive type semiconductor region surrounded by the second first conductive type semiconductor well region below the element isolation layer with the gate of the read transistor interposed therebetween. A solid-state imaging device, comprising: a charge storage region of a first conductivity type; a source / drain region of a second conductivity type of the readout transistor; and a first conductivity type semiconductor region below the gate. 6. The solid-state imaging device according to claim 5, wherein a first conductivity type semiconductor region is formed on a surface of said second conductivity type charge storage region. 7. The source of said read transistor
The solid-state imaging device according to claim 5, wherein a first conductivity type semiconductor region is formed below the drain region. 8. A step of forming an element isolation layer by an insulating layer on a surface of a semiconductor substrate of a second conductivity type; and forming a first well of a first conductivity type semiconductor at a predetermined depth position in the semiconductor substrate. Forming a second first conductivity type semiconductor well region under the element isolation layer so as to reach the first first conductivity type semiconductor well region;
Forming a first conductivity type semiconductor region at a predetermined depth position in a second conductivity type semiconductor region surrounded by the first conductivity type semiconductor well region; and the first conductivity type semiconductor region with a gate electrode interposed therebetween. Forming a source / drain region of the second conductivity type and a charge accumulation region of the second conductivity type constituting the sensor section so as to reach the above-mentioned condition. 9. A step of forming an element isolation layer of an insulating layer on a surface of a semiconductor substrate of a second conductivity type; and forming a first well of a first conductivity type semiconductor at a predetermined depth position in the semiconductor substrate. Forming a second first conductivity type semiconductor well region under the element isolation layer so as to reach the first first conductivity type semiconductor well region;
Forming a first conductivity type semiconductor region over the entire surface of the second conductivity type semiconductor region surrounded by the first conductivity type semiconductor well region; and forming a second conductivity type source in one of the regions with the gate electrode interposed therebetween.・
Forming a drain region and a semiconductor region of a first conductivity type below the source / drain region, and forming a charge accumulation region of a second conductivity type constituting a sensor section in the other region; A method for manufacturing an image sensor.