JP2001053184A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the connection strength of a metal post and a wiring pattern and the reliability of electrical connection by resin-sealing a second insulating layer, which is closely brought into contact with the wiring pattern on a side except for the tip face of a metal post for outer connection on the wiring pattern connected to the electrode of a semiconductor element to the exposed tip face, and by disposing an outer connection terminal. SOLUTION: A first insulating layer 5 in almost the same shape is formed on a passivation film 4, where an electrode 3 formed in a semiconductor element 2 is exposed. Metal posts for outer connection 9 are formed in prescribed positions on a wiring pattern 7 (wiring layer) connected to the electrode 3 on the first insulating layer 5. A side except for the tip face of the metal post 9 is coated, and a second insulating layer 8 which is closely brought into contact with a wiring pattern and the first insulating layer 5 is formed. The semiconductor element is sealed by a sealing resin 10, so that the tip face of the metal post 9 is exposed. Thus, priority is given to the adhesion of the second insulating layer to the posts 9 at a part lower than the tips of the posts 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device called a chip size package (CSP) having a wiring layer formed on a semiconductor element and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of electronic devices, semiconductor devices incorporated (mounted) in electronic devices have been mounted at a high density. It is required to be small. As a technology that meets this demand, there is a chip size package (hereinafter referred to as CS).
P), BGA (ball grid array), and the like. The CSP can be approximately the same size as a semiconductor element (IC chip), and can be said to be an effective means for reducing the size of a semiconductor device. Various structures and forms of the CSP have been proposed. A general CSP form will be described below with reference to the drawings schematically showing the structure of the CSP.

FIG. 6 is a sectional explanatory view schematically showing an example of a conventional semiconductor device 61 (CSP).

As shown in FIG. 6, an electrode made of aluminum or the like is used.
An electrode is formed on the semiconductor element 62 on which 63 (connection pad) is formed.
A passivation film 64 is formed to expose 63. Next, a first insulating layer 65 made of an insulating resin or the like is formed on the passivation film 64 so as to expose the electrode 63. Further, on the first insulating layer 65, a wiring pattern 67 (wiring layer) connected to the electrode 63 is formed.
A metal post 69 made of copper or the like is provided on 67. In the example of FIG. 6, the metal barrier layer 66 is formed below the wiring pattern 67. Next, a second insulating layer 68 is formed on the wiring pattern 67 and the first insulating layer 65 so as to expose the metal posts 69. In addition, resin sealing is performed with a sealing resin 70 so as to expose the metal posts 69.

In the case where a plurality of semiconductor elements 62 are formed on one Si (silicon) wafer by imposing them, the steps up to the formation of the second insulating layer 68 on the Si wafer are performed, and thereafter, If the wafer is diced and cut into individual semiconductor elements 62, a semiconductor device 61 (CSP) having substantially the same size as the individual semiconductor elements 62 can be obtained.

The metal post 69 is electrically connected to the electrode 63 via the wiring pattern 67. The metal post 69 electrically connects the semiconductor device 61 to the outside, for example, the electrical connection between the semiconductor device 61 and a mounting substrate on which the semiconductor device 61 is mounted. The electrical connection is made via a metal post 69. If necessary, as shown in FIG.
69 Solder (solder) balls 71 on the upper surface as external connection terminals 74
Etc. may be formed.

The metal post 69 and the outside (for example, a mounting board)
In many cases, the connection with the solder is made by thermocompression bonding using solder,
At that time, if the temperature becomes high, for example, about 180 ° C. to 250 ° C., a part of the metal post 69 will be dissolved and lost in the solder. Considering this dissolution and disappearance, the height of the metal post 69 is 3
It is common to set it to about 50 μm.

However, in the semiconductor device having such a structure, the connection strength between the metal post 69 and the wiring pattern 67 is insufficient, so that the reliability of the semiconductor device is low.
That is, when the semiconductor device is mounted on the mounting substrate, stress is applied to the semiconductor device due to a difference in thermal expansion coefficient between the semiconductor device and the mounting substrate, and cracks, disconnections, and the like occur in the semiconductor device.

Incidentally, the inventors of the present invention have conducted a temperature cycle test (one cycle by changing the temperature from -40.degree. C. to + 125.degree. C.) on a substrate on which a conventionally used semiconductor device is mounted, and repeat this temperature change a plurality of times. Test), the metal post 69 in about 50 to 200 cycles
And the wiring pattern 67 was peeled off to cause disconnection.

In consideration of the manufacturing cost of the semiconductor device, it is desirable that the thickness of each of the first insulating layer 65 and the second insulating layer 68 is about 10 μm or less. When an insulating layer having such a thickness is formed, and a solder ball 71 is formed on a metal post 69 and then an external connection is made, a stress such as a thermal stress is applied to the external connection terminal 74 of the semiconductor device 61 over time. And the insulating layer near the solder ball 71 is cracked, and a break occurs near the solder ball 71.

In order to solve such a problem, attempts have been made to form the second insulating layer 68 to a thickness of, for example, about 100 μm and to set the height of the metal post 69 to 100 μm. That is, by increasing the height of the metal posts 69, the stress applied to the semiconductor device due to the difference in the coefficient of thermal expansion from the mounting substrate is reduced.

However, using the semiconductor device having such a configuration causes a new problem. That is, in forming the metal posts 69, it is common to use a plating method.
Forming the metal post 69 having a height of μm increases the manufacturing cost of the semiconductor device and lowers the manufacturing yield. Further, it is not desirable from the viewpoint of manufacturing cost to form the second insulating layer 68 as thick as, for example, about 100 μm.

Further, in forming the metal posts 69 by plating, the metal posts 69 are formed in the openings of the second insulating layer 68 using the second insulating layer 68 as a plating mask. For this reason, when it is intended to form a metal post 69 that is thicker than the thicker second insulating layer 68, the metal post 69
The height of the 69 varies, and the quality of the metal post 69 tends to deteriorate. For this reason, when an electrical connection with the outside is made, a connection failure may partially occur, which may cause a reduction in the reliability of the electrical connection. In addition, the deterioration of the quality of the metal post means that voids (voids) associated with an electrical defect such as disconnection partially occur in the metal post. In addition, if the height of the metal post 69 varies and the size and shape of the solder ball 71 become uneven, the difference in the pressure applied to the solder or the solder ball during thermocompression bonding between the semiconductor device and the mounting board is reduced. Arises
There is also a problem that a connection failure or breakage of the semiconductor device occurs.

When a resin is used as the insulating layer, the first insulating layer 65 on which the wiring pattern 67 has been formed is covered with a second insulating layer 68, and then cured (burned) for a second time. The insulating layer 68 is cured. During the heating performed in the step of forming the second insulating layer 68, gas is generated from the first insulating layer 65,
The insulating layer swells due to bubbles caused by the gas, and the wiring pattern 67 is disconnected.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a high connection strength between a metal post and a wiring pattern, a high reliability of electrical connection with the outside, and a gas from an insulating layer. It is an object of the present invention to provide a highly reliable chip size package type semiconductor device which does not cause disconnection of a wiring pattern even when the semiconductor device is generated, and a method of manufacturing the same.

[0016]

Means for Solving the Problems The present inventors have conducted intensive studies in order to achieve the above-mentioned object, and have reached the present invention. That is, in claim 1, a first insulating layer having substantially the same shape as the passivation film is formed on a passivation film formed on the semiconductor element by exposing an electrode formed on the semiconductor element, A wiring pattern connected to the electrode of the semiconductor element is formed on the insulating layer, a metal post for external connection is formed on the wiring pattern, and wiring is performed so as to cover a side surface of the metal post except for a tip end surface of the metal post. A second insulating layer that is in close contact with the pattern is formed, is sealed with a sealing resin so as to expose the front end surface of the metal post, and an external connection terminal is provided on the front end surface of the metal post. The semiconductor device is characterized by the following.

According to a second aspect of the present invention, the height of the surface of the second insulating layer excluding the side surface region of the metal post is set to a position lower than the front end surface of the metal post. This is a semiconductor device.

According to a third aspect of the present invention, the external connection terminal is configured such that a conductive material is disposed on a surface of a holder having a hollow portion opened to the outside. In which the semiconductor device is described.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the holding body has a cylindrical shape having a hollow portion opened to the outside.

According to a fifth aspect of the present invention, the external connection terminal has a structure in which a conductive material is disposed on a surface of a cylindrical holder having no hollow portion. A semiconductor device according to the present invention.

According to a sixth aspect of the present invention, the holding member constituting the external connection terminal is made of polyimide, polyamide imide, polyether imide, thermoplastic polyimide, polyamide,
Polyacetal, polybutylene terephthalate, polyethylene terephthalate, polystyrene, syndiotactic polystyrene, polyphenylene sulfide, polyether ketone, liquid crystal polymer, polyether nitrile, fluororesin, polycarbonate, modified polyphenylene ether, polysulfone, polyether sulfone,
And engineered plastic comprising a resin selected from polyarylate and polyallylate.
A semiconductor device according to 4 or 5.

According to a seventh aspect of the present invention, the conductive material constituting the external connection terminal may be a dispersion of fine particles of graphite, carbon or metal, a simple substance of gold, silver, copper, aluminum or nickel, or two or more kinds of the metal. 7. The semiconductor device according to claim 3, wherein the alloy includes a low melting point alloy containing tin or lead as a main component.

Further, according to claim 8, a step of forming a first insulating layer on a passivation film formed to expose an electrode formed on a semiconductor element so as to expose the electrode, and a step of forming the first insulating layer. Forming a wiring pattern connected to the electrode thereon, forming a metal post for external connection at a predetermined position at a predetermined position on the wiring pattern, and insulating resin so as to include the metal post. After applying, a step of removing the insulating resin from the tip end surface region of the metal post connected to the outside to form a second insulating layer;
3. The method according to claim 1, further comprising a step of resin-sealing with a sealing resin so as to expose a front end face of the metal post, and a step of disposing an external connection terminal on the front end face of the metal post. According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device as described in 3, 4, 5, 6 or 7.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth aspect, the means for removing the insulating resin from the front end surface region of the metal post connected to the outside is formed by photolithography. And
In a tenth aspect, the method of manufacturing a semiconductor device according to the eighth or ninth aspect is characterized in that the means for applying the insulating resin as the second insulating layer is a spin coating method.

In the eleventh aspect, after the semiconductor element on which the second insulating layer is formed is attached to a heat sink for cooling, the tip of the metal post and the cooling face on the side opposite to the surface on which the semiconductor element is attached are provided. 11. The method according to claim 8, wherein an external connection terminal is mounted on a tip end surface of the metal post after resin sealing to expose a heat sink surface. .

According to a twelfth aspect of the present invention, after forming the second insulating layer on the plurality of imposed semiconductor elements at once, the semiconductor elements are separated into individual semiconductor elements by dicing.
Thereafter, the semiconductor device is attached to a cooling heat sink.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. Semiconductor device 1 of the present invention (CS
In P), as shown in FIG. 1, on the passivation film 4 formed to expose the electrode 3 formed on the semiconductor element 2, a passivation film 4 having substantially the same shape as the passivation film 4 so as to expose the electrode 3 is formed. One insulating layer 5 is formed. Next, a wiring pattern 7 (wiring layer) connected to the electrode 3 is formed on the first insulating layer 5.
A metal post 9 having a height of about 3 μm to 50 μm for external connection is formed at a predetermined upper position. Next, a second insulating layer 8 is formed so as to cover the side surfaces of the metal post 9 except for the tip end surface of the metal post 9 and is in close contact with the wiring pattern 7 and the first insulating layer 5. Next, the semiconductor element is sealed with a sealing resin 10 so as to expose the tip end surface of the metal post 9, and the external connection terminals 14 are provided on the metal post 9.

The semiconductor device 1 of the present invention has a structure in which the adhesiveness between the second insulating layer 8 and the metal post 9 is prioritized below the tip of the metal post 9 (in the direction of the semiconductor element). That is, the second insulating layer 8 is formed so as to cover the side surface of the metal post 9 excluding the tip. Thereby, the adhesion between the second insulating layer 8 and the metal post 9 is reinforced, and accordingly, the connection strength between the metal post 9 and the wiring pattern 7 is improved, and the disconnection between the metal post 9 and the wiring pattern 7 is prevented. it can.

Further, the surface of the second insulating layer 8 is made of metal so as not to hinder the mounting of the external connection terminals 14 and the outside (for example, a mounting board). The post 9 is formed at a position lower than the front end surface.

In a semiconductor device such as a CSP or BGA, it is necessary to seal a main part including a semiconductor element with a resin for the purpose of improving the reliability of a package and maintaining mechanical strength. As shown in FIG. 6, in a normal semiconductor device, a metal post 69 having a height of, for example, about 3 μm to 50 μm is formed, and an external connection terminal 74 is formed on the metal post 69.
In consideration of the thickness of the second insulating layer 68, the thickness of the semiconductor device 61 after resin sealing becomes unnecessarily thick. The surface of the sealing resin 70 is a metal post.
If the external connection terminal 74 is formed at a position relatively higher than the front end surface of the terminal 69, it may cause problems when the external connection terminal 74 is disposed by thermocompression bonding (for example, soldering). And a second insulating layer
Since the material 68 is made of a relatively expensive material, it is uneconomical to form the second insulating layer 68 thickly because it increases the manufacturing cost of the semiconductor device. The present inventors propose to optimize the height of the second insulating layer and the metal posts for the purpose of improving the workability of thermocompression bonding of the external connection terminals.

That is, as shown in FIG. 1, the second insulating layer 8 except for the portion covering the side surface of the metal post 9 is located at a position lower than the height of the tip end surface of the metal post 9. It is proposed to form a layer 8.
This will be described below. As shown in FIG. 8, which is a partially enlarged view of a conventional semiconductor device, when the surface of the second insulating layer 68 is equal to or higher than the height of the tip end surface of the metal post 69, it is formed on the second insulating layer 68. The height of the surface of the sealing resin 70 is higher than the tip surface of the metal post 69. For this reason, the metal post 69 exposed from the opening of the sealing resin 70
Even if an attempt is made to dispose the external connection terminals 74 (for example, solder balls) on the front end surface, the external connection terminals 74 are obstructed by the sealing resin 70, and a gap is formed between the front end surface of the metal post 69 and the external connection terminals 74.
Poor electrical connection between the metal post 69 and the external connection terminal 74 occurs.

However, as shown in FIG. 7 which is a partially enlarged view of the semiconductor device of the present invention, the height of the second insulating layer 8 excluding the portion covering the side surface of the metal post 9 is
If the height is lower than the height of the front end surface, the surface of the sealing resin 10 and the front end surface of the metal post 9 can be close to each other, and the sealing resin 10 does not interfere. No gap is formed between the distal end face 9 and the external connection terminal 14, and poor electrical connection between the metal post 9 and the external connection terminal 14 can be prevented.

Here, the material used for the first insulating layer 5 is:
There is no particular limitation as long as it has good heat resistance and good adhesion and does not affect the semiconductor element 2, but a substance having high purity is preferable in terms of contact with the semiconductor element 2. In addition, a material having a low dielectric constant is preferable, but polyimide can be said to be preferable in that a high-purity material can be obtained, and a photosensitive polyimide material or a photosensitive polyimide siloxane composition is preferable from a manufacturing viewpoint. is there. Further, the lower the coefficient of thermal expansion is, the better, approximately 60 ppm (60 × 10
Exp-6 in / in / ° C) or less is practically desirable.

Next, as the material of the second insulating layer 8, a resin having a lower purity than that used for the first insulating layer 5 is used because the second insulating layer 8 does not directly contact the semiconductor element 2. No problem. For example, in addition to the above-mentioned polyimide, an epoxy resin, an acrylic resin, or a resin obtained by modifying these resins with silicone can be used.

Next, the material of the wiring pattern 7 is preferably a material having good conductivity, for example, copper, silver, aluminum,
These alloys or other good conductor metals can be used. When copper, silver, or the like is used as the material of the wiring pattern 7, a metal barrier layer 6 made of TiW alloy, TiN, TaN, W, Cr, or the like is formed as an undercoat layer before forming the wiring pattern 7. Thereafter, it is desirable to form the wiring pattern 7 on the metal barrier layer 6.

Next, as a feature of the semiconductor device 1 of the present invention, as shown in FIG. 1, an external material (for example, a mounting device) having a shape in which a conductive material is disposed on the surface of a holding member having a hollow portion opened to the outside. External connection terminals for electrical connection with the board
14 is provided at the tip of the metal post 9. That is, the stress applied to the semiconductor device due to the difference in the coefficient of thermal expansion between the mounting substrate and the semiconductor device after mounting is reduced, as shown in FIGS. 1, 2 and 3, to a holder 15 having a hollow portion opened to the outside.
It is characterized in that it is relaxed by the external connection terminal 14 in which the conductive material 16 is disposed on the surface. 2 is a side view of an example of the external connection terminal 14 according to the present invention, and FIG. 3 is a top view of a cross section taken along line AA ′ of FIG. 2 (for example, as viewed from the mounting board side). FIG.

The above points will be described. As described above, when the semiconductor device 1 is mounted on a mounting board, the semiconductor element 2 made of silicon or the like (for example, having a coefficient of thermal expansion of about 3
ppm) and a mounting board (for example, a printed board made of an epoxy resin: a coefficient of thermal expansion of about 40 to 200 ppm,
However, a stress (stress) generated due to a difference in thermal expansion coefficient between the semiconductor device 1 and the semiconductor device 1 is higher than the Tg point. Conventionally, to mount a semiconductor device such as a CSP or a BGA on a mounting board such as a printed board, for example, 200 to 4
It has been simple and practical to form a solder ball having a diameter of about 00 μm as an external connection terminal on a metal post, and thermocompression-bond it to a mounting board via the solder ball.

However, a stress (stress) generated due to a difference in the coefficient of thermal expansion is applied to the solder ball, and cracks are generated in a resin substrate such as a semiconductor device or a printed board due to the stress (stress) transmitted through the solder ball. The wires tended to break relatively easily in the apparatus.

To prevent this, the present inventors have made intensive studies. As a result, if the external connection terminal 14 is provided with a stress relaxation function, the stress (stress) caused by the difference in the coefficient of thermal expansion is reduced. It has been found that it is alleviated by the external connection terminals 14 and that cracks and breaks in the semiconductor device 1 can be prevented. That is, the external connection terminal 14 according to the present invention is formed by forming a conductive material 16 on the surface of a hollow holding body 15 to have a stress relaxation function. Since the hollow holding member 15 has a flexible structure, even if the mounting substrate connected to the external connection terminals 14 repeats a considerable amount of thermal expansion and contraction, the generated stress (stress) can be absorbed and the stress can be reduced. This can prevent the occurrence of cracks at the interface between the insulating layer and the sealing resin and the external connection terminal 14 and the disconnection due to the cracks.

It is desirable that the hollow portion of the holder 15 be open to the external atmosphere so that air in the external atmosphere can freely enter and exit the hollow portion. This point will be described. As will be described later, it is desirable that the holder 15 be formed of a resin, but the resin easily absorbs water, and the resin containing water is easily hydrolyzed and deteriorated. However, if the hollow portion of the holding body 15 is opened to the outside atmosphere and air (air) of the outside atmosphere can freely enter and leave the hollow portion, the moisture contained in the holding body 15 can be reduced to the outside atmosphere. And the deterioration of the resin can be prevented. Further, if the hollow portion of the holder 15 is open to the external atmosphere, when heated at the time of mounting, the steam in which the moisture in the holder 15 evaporates and the expanded air are released to the external atmosphere, and the holder 15 is heated. Rupture can be prevented. Furthermore, even if heat is applied to the semiconductor device after mounting, the moisture in the holder 15 is released to the outside atmosphere, so that the holder 15 can be prevented from rupture or deterioration.

Here, the outer shape of the holding body may be cylindrical, quadrangular prism, hexagonal prism, octagonal prism, abacus ball, or the like. A self-alignment effect can be expected due to the surface tension of the solder, and in consideration of the availability of the material, a cylindrical shape (cylindrical shape) as shown in FIGS. In addition, if the environment in which the semiconductor device 1 is used is one in which the thermal change is small and the stress generated between the semiconductor device 1 and the mounting substrate is small, the shape of the holder 15 is a cylinder having no hollow portion. It does not matter.

Semiconductor devices such as CSP and BGA are generally mounted by thermocompression bonding using solder, a low-melting alloy, an anisotropic conductive film, or the like when mounted externally (for example, on a mounting board) and electrically connected. is there. For this reason, the material of the holding body 15 constituting the external connection terminal 14 according to the present invention is preferably engineered plastic having heat resistance. Here, engineering plastic means that the heat resistance is 100 ° C. or more and the strength is 49MP.
a and a plastic having a flexural modulus of 2.4 Gpa or more. As materials satisfying the above conditions, polyimide, polyamide imide, polyether imide, thermoplastic polyimide, polyamide, polyacetal, polybutylene terephthalate, polyethylene terephthalate, polystyrene, syndiotactic polystyrene, polyphenylene sulfide, polyether ketone, liquid crystal polymer, polyether Nitrile, fluororesin, polycarbonate, modified polyphenylene ether,
Examples include resins such as polysulfone, polyethersulfone, and polyarylate. Further, it may be a polymer alloy of the above engineering plastic.

Next, the semiconductor device 1 of the present invention performs fixing and electrical connection to the outside (for example, a mounting board) via the external connection terminals 14, and is provided on the surface of the holder 15 constituting the external connection terminals 14. Is provided with a conductive material 16. Conductive material
16 must be fixed to the outside and be capable of electrical connection. The conductive material 16 that satisfies such conditions
Examples thereof include graphite, carbon or metal fine particle dispersion, gold, silver, copper, aluminum, or nickel alone, or an alloy containing two or more of the above metals, and a low melting point alloy containing tin or lead as a main component. It is desirable to select from the above.

Examples of the low melting point alloy include those using metals such as mercury, gallium, and indium. From the viewpoint of manufacturing cost and the like, solder (solder) mainly containing tin or lead is used. Alloys are preferred. As the solder alloy, eutectic solder or high melting point solder with an increased ratio of lead can be applied.If necessary, bismuth, cadmium, antimony, zinc, manganese, indium, tin,
Silver or the like may be added. As shown in the examples of FIGS. 2 and 3, prior to disposing the conductive material 16 in order to improve the adhesion between the holder 15 and the conductive material 16,
An adhesive layer 17 may be formed on the surface of the substrate.

As an example of the external connection terminal 14 according to the present invention, for example, a cylindrical polyimide having an outer diameter of 100 μm to 1000 μm having a hollow portion is used as the holding member 15, and a conductive material 16 is formed on the surface of the holding member 15 as a conductive material 16. An external connection terminal 14 is formed by applying a solder alloy having a thickness of several tens of μm.
Prior to the application of the conductive material 16, an adhesive metal layer may be formed as the adhesive layer 17 on the surface of the tube. Further, the thickness of the conductive material 16 may be made larger as necessary, and the length and diameter of the holder 15 may be appropriately set in accordance with the specifications of the semiconductor device 1 or the like.

Next, the above-mentioned claim 8 proposes a method of manufacturing the semiconductor device 1 of the present invention. That is, the electrode 3 for electrical connection with the outside, which was obtained by a conventionally known manufacturing method shown in FIG. 4A, was formed, and the passivation film 4 exposing the electrode 3 was formed on the surface. After a first insulating layer 5 having substantially the same shape as the passivation film 4 is formed on the semiconductor element 2 so as to expose the electrode 3, a wiring having a predetermined shape connected to the electrode 3 is formed on the first insulating layer 5. FIG. 4B shows a step of forming the pattern 7 to form the state shown in FIG. 4B and forming a metal post 9 for external connection at a predetermined position of the wiring pattern 7 at a predetermined height (about 3 μm to 50 μm). c) and after applying an insulating resin on the first insulating layer 5 including the metal post 9, the insulating resin is removed from the tip region of the metal post 9 connected to the outside, and the second insulating Step of forming the layer 8 into the state shown in FIG. Fig. 4 (e)
And a step of arranging the external connection terminals 14 and providing a step shown in FIG. 4F. In the example of FIG. 4, prior to the formation of the wiring pattern 7, the metal barrier layer 6
Is formed.

As described above, after the metal post 9 is formed, the second insulating layer 8 is formed with the insulating resin applied and formed. At this time, the second insulating layer 8 excluding the side surface of the metal post 9 is formed. Is formed at a position lower than the height of the front end face of the metal post 9. Therefore, it is preferable to use a photolithography method in which the insulating resin is made of a photosensitive material and coating, pattern exposure, development, and the like are performed to remove unnecessary portions of the insulating resin.

For the application of the insulating resin for forming the second insulating layer 8, a known coating means such as a spin coating method, a curtain coating method, a screen printing method, and a slit and spin coating method may be used. However, when considering that the height of the second insulating layer 8 excluding the side surface of the metal post 9 is formed at a position lower than the height of the front end surface of the metal post 9, the spin coating method is preferable. That is, if the insulating resin is applied by spin coating after the formation of the metal posts 9, the excess insulating resin is removed outside the semiconductor element. Therefore, by appropriately setting the application conditions, the insulating resin can be applied with a thickness smaller than the height of the front end surface of the metal post 9 in the region excluding the side surface portion of the metal post 9, and the side surface of the metal post 9 can be applied. Can also apply an insulating resin. The removal of the insulating resin remaining on the tip surface of the metal post 9 may be selectively removed by laser, dry etching, reverse sputtering, or the like, in addition to the above-described photolithography method.

Next, a semiconductor device 1 having a cooling heat sink 12 for cooling the semiconductor element 2 may be required. The invention according to claim 11 proposes a method of manufacturing a semiconductor device having a heat sink 12 for cooling. That is, after attaching the cooling heat sink 12 to the semiconductor element 2 formed up to the second insulating layer 8 shown in FIG.
The resin is sealed with a sealing resin 10 so as to expose the surface of the cooling heat sink 12 on the side opposite to the side on which the semiconductor element 2 is attached, and the state shown in FIG. Thereafter, an external connection terminal 14 is mounted on the tip end surface of the metal post 9 to obtain the semiconductor device 1 shown in FIGS. 1 and 4 (f).

Next, the semiconductor element 2 is often formed in a state where a plurality of semiconductor elements 2 are imposed on one plate-shaped silicon wafer. The invention according to claim 12 proposes a manufacturing method for obtaining individual semiconductor devices 1 from a silicon wafer having a plurality of semiconductor elements 2 formed by imposition. That is, after performing the above-described process up to the formation of the second insulating layer 8 on a silicon wafer having a plurality of semiconductor devices 2 mounted thereon, the semiconductor device 2 is separated into individual semiconductor devices 2 by dicing. A cooling heat sink 12 is attached to each of the semiconductor elements 2 thus manufactured.

[0051]

Embodiments of the present invention will be described below with reference to the drawings. <Embodiment> FIG. 4A shows a semiconductor element 2 incorporated in a semiconductor device 1 of the present invention and obtained by a conventionally known means. An electrode 3 made of aluminum is formed on a semiconductor element 2 using a silicon wafer as a base material, and a passivation film 4 is formed on the semiconductor element 2 so as to expose the electrode 3.
Are formed. In this embodiment, a plurality of semiconductor elements 2 are mounted on one silicon wafer, but one semiconductor element 2
Is illustrated.

Next, a photosensitive polyimide (trade name “Pimel” manufactured by Asahi Kasei Corporation) is applied onto the semiconductor element 2, and the electrode 3 is formed by a known photo-etching method of performing pattern exposure, development, and the like. An exposed first insulating layer 5 having a thickness of about 10 μm was formed. Then, a 2000 nm thick TiN layer and a 5000 mm thick Cu
The layers were sequentially laminated on the first insulating layer 5. Next, the TiN layer and the Cu layer were patterned using a known photoetching method to obtain a wiring pattern 7 electrically connected to the electrode 3 (FIG. 4B). The TiN layer between the first insulating layer 5 and the wiring pattern 7 is formed as a barrier metal layer 6.

Next, as shown in FIG. 4C, after a metal post 9 is formed on the wiring pattern 7, a photosensitive polyimide (trade name "Asahi Kasei Kogyo Co., Ltd.," Pymel ") was applied by spin coating, and then excess polyimide excluding the upper surface and side surfaces of the metal posts 9 was removed by photoetching to obtain a second insulating layer 8 (FIG. 4D). As shown in FIG. 4D, the second insulating layer 8 exposes the upper surface of the metal post 9 and covers the side surface of the metal post 9, and has a thickness of 10 μm so as to be lower than the upper surface of the metal post 9 in other portions. And In forming the metal posts 9, a mask plating method is used, and the steps of the mask plating method will be described below. That is, after obtaining FIG. 4B, a photosensitive resist layer having a film thickness of 20 μm is formed on the first insulating layer 5 and the wiring pattern 7, and the wiring at the metal post formation site is formed by using a known photo-etching method. Plating mask exposing pattern 7
13 was formed (FIG. 5A). Next, a metal post 9 (15 μm in height) made of copper was formed on the wiring pattern 7 exposed from the plating mask 13 by electrolytic plating (FIG. 5D). Next, the plating mask 13 is stripped off, and FIG.
(C).

Next, as shown in FIG. 4D, dicing is performed on the silicon wafer on which the semiconductor element 2 is mounted, and the semiconductor element 2 is divided into individual pieces. A heat sink 12 made of a Cu plate was attached to the surface opposite to the surface on which the heat treatment was performed. Next, resin molding was performed with the sealing resin 10 so that the upper surface of the metal post 9 and the heat sink 12 were exposed (FIG. 4E).

Next, an external connection terminal is placed on the metal post 9.
The semiconductor device 1 was obtained by mounting the semiconductor device 14 (FIG. 4F). The external connection terminals 14 used in the present embodiment are formed by forming eutectic solder as a conductive material 16 on the surface of a hollow holder 15 made of thermoplastic polyimide as shown in FIG. Obtained. That is, first, the inner diameter is 0.15 mm and the thickness is 5
A 0 μm hollow thermoplastic polyimide tube was purchased in a long form. Next, metal chromium and copper were sequentially laminated on the tube surface (outer surface). The metal chromium and copper serve as the adhesive layer 17 when the conductive material is laminated, and are formed by sputtering so that the thickness of the metal chromium is 0.2 μm and the thickness of the copper is 0.4 μm. Filmed.
After forming the adhesive layer 17, the conductive material 16 is formed to a thickness of about 20
A μm eutectic solder was plated. Next, after the formation of the eutectic solder, each of the long thermoplastic polyimide tubes was cut to a length of about 0.3 mm, and FIG. 2 and FIG.
The external connection terminal 14 shown in FIG.

The semiconductor device 1 obtained in this example was mounted on a printed circuit board. The mounting was performed by heating and pressing (solder) at 220 ° C. for 8 seconds. At the time of the thermocompression bonding, the external connection terminal 14 having the hollow holding member 15 absorbs the pressure applied at the time of thermocompression bonding, so that the mounting connection can be performed at a pressure lower than conventionally required. By the way, in the semiconductor device 1 according to the present embodiment, the mounting connection can be performed at a pressure of about 5 grams per one external connection terminal 14, which is about half of the pressure conventionally required. Further, even when the thickness of the printed circuit board and the height of the metal posts 9 vary and become non-uniform, the non-uniformity is absorbed by the hollow holder 15 which is easily deformed during mounting. The mounting was possible without causing a connection failure between the device 1 and the printed circuit board.

The reliability was evaluated by performing a temperature cycle test at -45 ° C. to + 125 ° C. on the printed circuit board on which the semiconductor device 1 according to the present embodiment was mounted, and the reliability was evaluated. Did not occur.

The embodiments of the present invention have been described above.
Embodiments of the present invention are not limited to the drawings and descriptions described above, and it goes without saying that various modifications may be made based on the spirit of the present invention.

For example, in the above description, an example is shown in which the external connection terminal according to the present invention is used for a CSP, but the external connection terminal according to the present invention may be formed in a semiconductor device such as a BGA. In the above description, the sputtering method is used for forming the wiring pattern 7, but a vacuum deposition method, an ion plating method, a CVD method, a sol-gel method, or the like can be applied as the film formation method, and the film formation method is appropriately determined according to the form. A film formation method may be selected. Furthermore, the material and thickness of the insulating layer,
The material and thickness of the conductive material, or the material, diameter and length of the holder may be appropriately selected according to the specifications of the semiconductor device.

Further, instead of chromium, metal oxide, metal nitride, aluminum, or the like may be used as an adhesive layer formed between the holder and the conductive material. Instead of the vacuum film formation such as the sputtering method, an activation treatment with palladium, electroless plating of copper or nickel, electrolytic plating, or the like may be used. Furthermore, the surface of the holder may be subjected to a surface treatment before the film is formed on the holder. As the means, etching means such as plasma etching, ion etching, or wet etching, or sand blast is used. It does not matter.

[0061]

As described above, in the present invention, the mechanical strength of the metal post 9 is improved by reinforcing the side surface of the metal post 9 for external connection with the second insulating layer 8. The second insulating layer 8 is formed only in a necessary part. For this reason, the semiconductor device of the present invention can reduce electrical connection failure due to thermal strain and stress strain. That is, according to the present invention, a highly reliable semiconductor device (CSP)
Can be obtained. Further, the semiconductor device 1 of the present invention
The metal post 9 is excellent in mechanical strength because it is reinforced by the second insulating layer 8, and is applicable to a metal post formed on a flip-chip type semiconductor device, a build-up type multilayer wiring board, or the like. It is possible.

Further, when forming the second insulating layer 8, a spin coating method is used, and a photo-etching method is used for removing unnecessary resin including the upper part of the metal post 9. This makes it possible to form the surface of the second insulating layer lower than the upper surface of the metal post except for the side surface of the metal post 9. Thereby, the thickness of the semiconductor device 1 can be reduced,
Further, it is possible to prevent poor electrical connection between the external connection terminal and the metal post caused by the contact of the sealing resin.

The second insulating layer 8 has a wiring pattern 7
And a region excluding the side surface of the metal post 9 is formed lower than the front end surface of the metal post 9. Thereby, when curing (baking) for forming the second insulating layer 8 is performed (for example, 400 ° C. in a high-temperature oven).
When heating for one hour), even if a residual gas is generated from the resin constituting the first insulating layer 5, the residual gas remains in a portion of the second insulating layer 8 where the film thickness is small (on the wiring pattern 7). Area). For this reason, it is possible to prevent the resin portion from swelling due to bubbles due to the residual gas and disconnecting the wiring pattern 7.

Further, after the second insulating layer 8 is formed and singulated by dicing, a heat sink 12 is adhered to the back surface of the semiconductor element 2 to obtain the semiconductor device 1 having excellent heat dissipation. In addition, since the resin sealing is performed except for the end face of the metal post 9, the device surface and side surfaces are protected by the sealing resin, and a highly reliable semiconductor device having excellent airtightness and no package crack due to moisture absorption is obtained. be able to.

Further, in the semiconductor device 1 of the present invention, the external connection terminal 14 is constituted by the hollow support 15. That is, in the present invention, the external connection terminals 14 obtained by a simple configuration and a simple manufacturing process have a stress relaxation function. Accordingly, when the semiconductor device 1 is mounted on the mounting substrate, the stress applied to the semiconductor device 1 due to the difference in the coefficient of thermal expansion between the semiconductor device 1 and the mounting substrate is absorbed by the external connection terminals 14 having a stress relaxation function, and cracks are generated. Since the occurrence of disconnection or the like can be prevented, a highly reliable semiconductor device can be provided. Conventionally, a BGA has been provided with a stress relieving means called an interposer to relieve an external force applied to the device. However, the size of the stress relieving device becomes large, and there is a limit in reducing the size of the device. However, in the semiconductor device 1 of the present invention, the stress can be relieved by the external connection terminal 14 having a simple configuration, so that the size of the device can be reduced.
In addition, even when the thickness of the printed circuit board and the height of the metal posts 9 are uneven, the external connection terminals 14 having the stress relaxation function can be easily deformed during mounting and absorb the unevenness. This makes it possible to prevent connection failure due to unevenness in the thickness of the printed circuit board and the height of the metal posts.

The holder 15 constituting the external connection terminal 14
Is formed, for example, in a cylindrical shape (cylindrical shape) having a hollow portion opened to the outside, it is possible to improve the reliability of electrical connection when the semiconductor device 1 is mounted. That is, when moisture is present in the holder 15, when heated at the time of mounting, moisture is released from the holder 14, and this moisture causes a failure such as a poor electrical connection. In addition, the moisture in the holder 15 causes the holder 15 to deteriorate. But,
Since the holding member 15 is hollow, moisture escapes from the hollow portion to the outside atmosphere during heating, which can prevent poor electrical connection and the like during mounting. And the deterioration of the holder 15 can be prevented.

[0067]

[Brief description of the drawings]

FIG. 1 is a sectional explanatory view schematically showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is an explanatory view showing an example of an external connection terminal according to the present invention.

FIG. 3 is an explanatory sectional view showing an example of an external connection terminal according to the present invention.

4A to 4F are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the present invention in the order of steps.

FIGS. 5A and 5B are cross-sectional views illustrating an example of a method of forming a metal post in the order of steps.

FIG. 6 is an explanatory cross-sectional view schematically showing an example of a conventional semiconductor device.

FIG. 7 is an enlarged explanatory view schematically showing a main part of an example of the semiconductor device of the present invention.

FIG. 8 is an enlarged explanatory view showing an example of a connection failure in a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 61 Semiconductor device 2, 62 Semiconductor element 3, 63 Electrode 4, 64 Passivation film 5, 65 First insulating layer 6, 66 Barrier layer 7, 67 Wiring pattern 8, 68 Second insulating layer 9, 69 Metal post 10, 70 Sealing resin 11, 71 Solder ball 12 Heat sink 13 Plating mask 14, 74 External connection terminal 15 Holder 16 Conductive material 17 Adhesive layer

Claims (12)

[Claims] A first insulating layer having substantially the same shape as the passivation film is formed on a passivation film formed on the semiconductor element by exposing an electrode formed on the semiconductor element; A wiring pattern connected to the electrode of the semiconductor element is formed thereon, a metal post for external connection is formed on the wiring pattern, and the wiring pattern is formed so as to cover a side surface of the metal post except for a tip surface of the metal post. A second insulating layer that is in close contact with the metal post is formed, is sealed with a sealing resin so as to expose the front end surface of the metal post, and an external connection terminal is provided on the front end surface of the metal post. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the height of the surface of the second insulating layer excluding the side surface region of the metal post is set at a position lower than the front end surface of the metal post. 3. The semiconductor device according to claim 1, wherein the external connection terminal has a structure in which a conductive material is disposed on a surface of a holder having a hollow portion opened to the outside. . 4. The semiconductor device according to claim 3, wherein the holder has a cylindrical shape having a hollow portion opened to the outside. 5. The semiconductor device according to claim 1, wherein the external connection terminal has a structure in which a conductive material is disposed on a surface of a cylindrical holder having no hollow portion. . 6. A holding member constituting an external connection terminal may be made of polyimide, polyamide imide, polyether imide, thermoplastic polyimide, polyamide, polyacetal, polybutylene terephthalate, polyethylene terephthalate, polystyrene, syndiotactic polystyrene, polyphenylene sulfide, or polyphenylene sulfide. An engineered plastic comprising a resin selected from ether ketone, liquid crystal polymer, polyether nitrile, fluororesin, polycarbonate, modified polyphenylene ether, polysulfone, polyethersulfone, and polyarylate. Or the semiconductor device according to 5. 7. The conductive material constituting the external connection terminal may be graphite, carbon or a fine metal particle dispersion, a simple substance of gold, silver, copper, aluminum or nickel, an alloy containing two or more kinds of the above metals, tin or 7. The semiconductor device according to claim 3, wherein the low-melting point alloy containing lead as a main component is selected from the group consisting of: 8. A step of forming a first insulating layer on a passivation film formed on a semiconductor element so as to expose the electrode, and forming the first insulating layer on the first insulating layer so as to expose the electrode. A step of forming a wiring pattern to be connected, a step of forming a metal post for external connection at a predetermined height at a predetermined position of the wiring pattern, and applying an insulating resin so as to include the metal post, Removing the insulating resin from the tip surface area of the metal post to be connected to the outside to form a second insulating layer; sealing the resin with a sealing resin so as to expose the tip face of the metal post; Arranging an external connection terminal on the tip end surface of the slab.
8. The method for manufacturing a semiconductor device according to 5, 6, or 7. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the means for removing the insulating resin from the front end surface region of the metal post connected to the outside is a photolithography method. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the means for applying the insulating resin as the second insulating layer is a spin coating method. 11. A semiconductor device having a second insulating layer formed thereon is attached to a cooling heat sink, and thereafter, a tip end surface of the metal post and a cooling heat sink surface opposite to the surface on which the semiconductor element is attached are exposed. Resin sealing, and then
11. The method for manufacturing a semiconductor device according to claim 8, wherein an external connection terminal is mounted on a front end surface of the metal post. 12. The method according to claim 1, wherein the step of forming a second insulating layer on the plurality of semiconductor elements mounted on the substrate is performed at a time, and the semiconductor elements are separated into individual semiconductor elements by dicing. The method according to claim 11, wherein the method is performed.