JP2001045742A - Power mos drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely change over a drive circuit before a surge voltage is generated by installing a voltage-change detection means which detects the change rate of the gate voltage of a power MOS transistor. SOLUTION: When a power MOS transistor 5 is turned off, the change rate of the gate voltage Vg of the power MOS transistor 5 is detected by a dv/dt detection circuit 6 as a voltage change rate detection means. Then, on the basis of its detection result, a gate driving power changeover operation is performed by a changeover means when the power MOS transistor 5 is turned off. By this constitution, when the power MOS transistor 5 is turned off, an electric charge which is stored in its gate is pulled out, and the gate voltage is lowered once. After that, since the electric charge due to a miller capacitance is pulled out, a period in which the voltage is not changed exists. The period in which the voltage is not changed is detected by the voltage change rate detection means. On the basis of its detection result, the gate voltage is lowered gently, and a gate driving power is reduced by a prescribed amount. As a result, it is possible to suppress the generation of a surge voltage when the power MOS transistor is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOS drive circuit, and detects a rate of change (dv / dt) of a gate voltage at the time of turn-off in order to prevent generation of a surge voltage at the time of turn-off and to shorten a turn-off time. Then, the drive circuit is switched based on the rate of change.

[0002]

2. Description of the Related Art As a conventional drive circuit for a voltage controlled power semiconductor device, for example, there is one as shown in FIGS. 9 and 10 (Japanese Patent Application Laid-Open No. 10-32976). Hereinafter, this is referred to as a first related art. In FIG. 9, a switching circuit including a series circuit of a steady-state gate resistor 27 and a steady-state transistor 23 and a switching circuit including a series circuit of a steady-off gate resistor 29 and a steady-state transistor 25 are provided. Turn-on gate resistor 2 having a larger resistance than steady-state gate resistor 27
A switching circuit composed of a series circuit of a turn-on transistor 6 and a turn-on transistor 22 and a switching circuit composed of a series circuit of a turn-off gate resistance 28 and a turn-off transistor 24 having a larger resistance than the steady-state gate resistance 29 are provided in parallel. . The IGBT 30 is provided with an auxiliary emitter terminal Es for taking out a small auxiliary emitter current proportional to the main collector current, separately from the main emitter terminal Em for flowing the main collector current. The auxiliary emitter terminal Es is connected to the main emitter terminal Em via an inductance 31 for detecting the current change rate of the main collector current. The inductance 31 for detecting the current change rate has a change rate of the main collector current Ic. Generates a voltage signal (di / dt) 106 proportional to. The magnitude Vs of the di / dt signal 106 is Vs = (inductance 31
Of the auxiliary emitter current) × (change rate of the auxiliary emitter current in proportion to the main collector current).

Di / dt at turn-on and turn-off
The signal 106 is input to the switching circuit 21 via the one-shot circuit 32 for turning on and the one-shot circuit 33 for turning off. The switching circuit 21 receives the on / off signal 101, the output signal 102 of the turn-on one-shot circuit 32, and the output signal 103 of the turn-off one-shot circuit 33, and switches the driving of the transistors 22 to 25.

[0004] Referring to the operation waveform diagram of FIG.
The operation at 0, especially at the time of turn-off will be described. The on / off signal 101 input to the switching circuit 21 at time t ₄ is “0”
When the level is switched to the off signal, the switching circuit 21 turns off the steady on transistor 23 and simultaneously turns on the steady off transistor 25, and applies the off power supply 35 to the gate of the IGBT 30 via the steady off gate resistor 29. I do. The steady-state gate resistor 29 is set smaller than the turn-off gate resistor 28 as described above,
The gate input capacitance of the IGBT30 rapidly discharged by the gate voltage V _GE is lowered rapidly, thereby the main collector current Ic at t ₅ when starts falling, also starts to fall at the same time the auxiliary emitter current. As a result, a di / dt signal 106 having a value equal to or higher than the predetermined value composed of the voltage Vs is generated in the inductance 31 for detecting the current change rate. Turnoff one-shot circuit 33 at the falling portion of the front end of the di / dt signal 106 is triggered, the turnoff one-shot circuit 33 for a predetermined time period T _33,
The one-shot signal 103 of “1” level is output.

The switching circuit 21 outputs the one-shot signal 10
During the period in which 3 is present, the steady-off transistor 25 is turned off and the turn-off transistor 24 is turned on. Therefore, the predetermined time T _33, since the gate input capacitance of the IGBT30 is to be discharged in a large turn-off gate resistor 28, the gate voltage V _GE is slowly lowered, even gently falls mainly collector current Ic, the predetermined time period decay to nearly final level at t ₆ when the T ₃₃ elapses. In this way, to alleviate the lowering speed of the gate voltage V _GE of IGBT30 at the time of turn-off, gently off the IGBT30,
The generation of surge voltage at the time of turn-off is suppressed. However, in the first prior art, the timing at which the main collector current starts to fall is detected to operate the switching circuit to switch the switching circuit (drive circuit), so that the time available for switching control of the switching circuit is shortened. Therefore, the switching may not be completed before the surge occurs.

[0006] On the other hand, a method is conceivable in which the gate driving force is controlled by triggering that the gate voltage of the power MOS approaches the vicinity of the threshold. Although this method is unknown, it will be described as a second conventional technique with reference to FIGS. In FIG. 11, a gate drive force switching circuit 1 at the time of turn-off switches a drive signal 2 between a terminal b and a terminal c. b terminal is connected to the gate of the power MOS5 via the main drive circuit 3 and the resistor R _1. The terminal c is a turn-off sub-drive circuit 4 and a resistor R
It is connected to the gate of the power MOS 5 through the gate ₂ .
A turn-off voltage value detection circuit 16 detects the gate voltage Vg of the power MOS 5 at the time of turn-off and feeds it back to the gate drive force switching circuit 1 at the time of turn-off. The resistance values of the resistors R ₁ and R ₂ are R ₁ <R
There are _two relations, the resistance R ₂ in order to suppress the surge voltage at turn-off, so as to provide sufficient weak driving force to cause gradual switching power MOS 5.

This operation will be described with reference to FIG. In the turn-off operation, when the drive signal 2 is turned off, first, the main drive circuit 3 operates to start the turn-off operation of the power MOS 5. Thereafter, when the gate voltage Vg falls to the detected voltage value of the turn-off voltage value detection circuit 16 set near the threshold value, the turn-off gate driving force switching circuit 1 receives the output of the turn-off voltage value detection circuit 16 and outputs the drive signal. 2 is switched from the main drive circuit 3 to the sub drive circuit 4 at the time of turn-off. By this switching, the gate driving force is weakened, and the power MOS 5 is slowly turned off.

[0008]

However, in the first prior art, the drive circuit is switched by detecting the timing at which the main collector current starts to fall, so that it can be used for switching control of the drive circuit. There has been a problem that the time may be shortened and the switching may not be completed before a surge occurs. Further, in the second prior art, since the drive circuit is switched by detecting the gate voltage itself, if the switching voltage is set in consideration of the variation of the threshold voltage, the switching timing becomes faster, and the turn-off time becomes shorter. However, there was a problem that the length was longer.

The present invention has been made in view of such a conventional problem, and it is possible to reliably switch a drive circuit before a surge voltage occurs, and to realize a power MO.
It is an object of the present invention to provide a power MOS drive circuit capable of shortening a turn-off time without being affected by variations in threshold voltage of S.

[0010]

According to a first aspect of the present invention, there is provided a power MOS drive circuit including a drive circuit for driving a gate of a power MOS, wherein the gate of the power MOS is provided. Voltage change rate detection means for detecting a voltage change rate; and the power M by the drive circuit based on the detection result of the voltage change rate detection means.
The gist of the present invention is to have a switching means for switching so as to reduce the gate driving force of the OS by a predetermined amount.

With this configuration, when the power MOS is turned off, the electric charge accumulated in the gate is extracted and the gate potential temporarily drops, but thereafter, there is a period in which the electric potential is not changed because the electric charge by the mirror capacitance is extracted. The period during which the potential does not change is detected by the voltage change rate detecting means, and based on this detection result, the gate voltage is gradually reduced, and the gate driving force is reduced by a predetermined amount. Thereby, generation of a surge voltage at the time of turn-off can be suppressed.

According to a second aspect of the present invention, in the power MOS drive circuit according to the first aspect, a delay circuit for performing a switching operation of the switching means with a predetermined time delay after the detection result of the voltage change rate detecting means. The gist is to have. With this configuration, when the power MOS is turned off,
By setting the timing at which the gate driving force is reduced by a predetermined amount as the detection timing of the rate of change of the gate voltage, it is possible to perform switching to reduce the gate driving force by a predetermined amount with a relatively long margin before the occurrence of a surge voltage. it can. By taking a constant delay time within this relatively marginal time, the turn-off time is optimized and further shortened.

[0013]

According to the first aspect of the present invention, the power M
Voltage change rate detection means for detecting a change rate of the gate voltage of the OS, and switching means for switching so as to reduce the gate driving force of the power MOS by the drive circuit by a predetermined amount based on the detection result of the voltage change rate detection means. Therefore, when the power MOS is turned off, the timing for reducing the gate driving force by a predetermined amount is used as the detection timing of the change rate of the gate voltage, so that the switching can be reliably performed before the generation of the surge voltage. The turn-off time can be shortened without being affected by the variation in the threshold voltage.

According to the second aspect of the present invention, a delay circuit is provided for delaying a predetermined time after the detection result of the voltage change rate detecting means to perform the switching operation of the switching means, so that the turn-off time is optimized. Thus, it can be further shortened.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 to FIG. 4 are views showing a first embodiment of the present invention. First, the configuration of the present embodiment will be described with reference to FIG. In FIG. 1 and FIG. 5 showing a second embodiment to be described later, the same or equivalent components as the circuits and elements in FIG. 11 are denoted by the same reference numerals as those described above, and duplicate description will be omitted. . In the present embodiment,
At the time of turn-off, the rate of change of the gate voltage Vg of the power MOS 5 is determined as dv / d at the time of turn-off as voltage change rate detecting means.
The detection is performed by the t detection circuit 6, and the switching operation of the gate driving force switching circuit 1 at the time of turn-off as switching means is performed based on the detection result. The internal configuration example and operation of each circuit such as the turn-off gate driving force switching circuit 1 in FIG. 1 will be described later.

Next, the operation of the power MOS drive circuit configured as described above, especially at the time of turn-off, will be described with reference to FIG. In response to the off drive signal 2 (FIG. 2A), first, the main drive circuit 3 operates, and the power MOS 5 starts to turn off. Due to the start of the turn-off operation, the electric charge stored in the gate of the power MOS 5 becomes the resistance R ₁
And the gate voltage Vg of the power MOS 5
Gradually decreases. Thereafter, the gate voltage Vg is used to extract the charge due to the mirror capacitance of the power MOS 5,
A period t in which the potential does not change is entered (FIG. 2B). The non-changing period t is detected by the turn-off dv / dt detection circuit 6, and the turn-off dv / dt detection circuit 6
Outputs an "H" level signal as the detection signal (FIG. 2 (c)). The gate drive force switching circuit 1 at the time of turn-off operates according to the "H" level detection signal, and switches the off-drive signal 2 from the terminal b to the terminal a. Due to this switching operation, the operation of the main drive circuit 3 is stopped, and the sub-drive circuit 4 operates at the time of turn-off (FIGS. 2D and 2E). At this time, the electric charge remaining on the gate of the power MOS 5 is the resistance R
Pulled out through _two . Since the resistance R ₂ has a larger resistance value than the resistance R _1, the potential of the gate voltage Vg of power MOS5 moderately downlink, power MOS5 moderately off. Thereby, generation of a surge voltage at the time of turn-off can be suppressed.

Next, referring to FIG. 3 and FIG. 4, each internal configuration example of the gate drive force switching circuit 1 at the time of turn-off, the main drive circuit 3, the sub-drive circuit 4 at the time of turn-off, and the dv / dt detection circuit 6 at the time of turn-off, and The operation will be described. In FIG. 3, a gate driving force switching circuit 1 at the time of turn-off is an inverter (hereinafter, the inverter is also denoted by reference numeral 1).
And the main drive circuit 3 is a three-state IC
(Hereinafter, the three-state IC is also denoted by reference numeral 3).
An OS (hereinafter, also referred to as an nMOS using a reference numeral 4).

At the time of the ON drive signal 2, the three-state I
The input / output of C3 is in the ON state, and the gate of the power MOS 5 is supplied with the "H" level gate voltage Vg.
When the "H" level signal is output from the dv / dt detection circuit 6 at the time of turn-off, the output of the inverter 1 becomes "L" level, and this "L" level signal is input to the control terminal of the three-state IC 3, The input / output of the three-state IC3 turns off, while the nMOS
4 turns on. That is, as described above, the operation of the main drive circuit stops, and the auxiliary drive circuit operates at the time of turn-off. The turn-off dv / dt detecting circuit 6 includes a differentiating circuit 8, a buffer 9, an AND gate 10, a rising edge trigger T-flip flop 11, and an inverter 12. (B), (c), (d) of FIG.
Indicates a voltage signal appearing at each node in the dv / dt detection circuit 6 at the time of turn-off. When the power MOS 5 is turned off, the rising edge trigger type T-flip flop 11 is triggered at each rising of the output of the AND gate 10 (FIG. 4 (d)) to turn off the dv / dt detection circuit 6.
Outputs an "H" level signal as described above (FIG. 4 (e)).

FIGS. 5 to 8 show a second embodiment of the present invention. In the present embodiment, at the time of turn-off dv / d
The rising delay circuit 7 is connected to the next stage of the t detection circuit 6. The rising delay circuit 7 is turned off d
The output of the v / dt detection circuit 6 is delayed for a predetermined time and input to the gate driving force switching circuit 1 at the time of turn-off. The internal configuration example of the rising delay circuit 7 and its operation will be described later.

Next, the operation of the power MOS drive circuit configured as described above, particularly at the time of turn-off, will be described with reference to FIG. First, the main drive circuit 3 operates according to the off drive signal 2 (FIG. 6A), and the power MOS 5 starts a turn-off operation. Due to the start of the turn-off operation, the electric charge stored in the gate of the power MOS 5 becomes the resistance R ₁
And the gate voltage Vg of the power MOS 5
Gradually decreases. Thereafter, the gate voltage Vg is used to extract the charge due to the mirror capacitance of the power MOS 5,
The period t in which the potential does not change is entered (FIG. 6B). The non-changing period t is detected by the turn-off dv / dt detection circuit 6, and the turn-off dv / dt detection circuit 6
Outputs an "H" level signal as the detection signal (FIG. 6 (c)). The "H" level detection signal is input to the rise delay circuit 7, and a signal delayed for a predetermined time from the rise of the "H" level detection signal is output from the rise delay circuit 7 (FIG. 6 (d)). Here, in the first embodiment, the electric charge due to the mirror capacitance is extracted only by the sub-drive circuit 4 at the time of turning off. However, in the present embodiment, by using the rising delay circuit 7, a part of the charge due to the mirror capacitance is extracted by the main drive circuit 3, and the timing of switching to the sub-drive circuit 4 at turn-off by the timer of the rising delay circuit 7. Controlling. By extracting the electric charge due to the mirror capacitance by the main drive circuit 3, an increase in the turn-off time can be further reduced. The rise delay circuit 7 is based on a timer that starts operating by the output of the dv / dt detection circuit 6 at the time of turn-off, and a timer time adjusted so as to be turned off a predetermined time before the power MOS 5 is turned off in accordance with the charge due to the mirror capacitance of the power MOS 5. It is configured. The gate drive force switching circuit 1 at the time of turn-off is operated by the output of the rising delay circuit 7, and the off-drive signal 2 is switched from the terminal b to the terminal a. By this switching operation, the operation of the main drive circuit 3 is stopped, and the sub-drive circuit 4 operates at the time of turn-off (FIG. 6 (e),
(F)). In this case, the charge remaining in the gate of the power MOS5 is withdrawn via a resistor R _2. The resistance R ₂ is
Since the resistance value than the resistance R ₁ is larger, the potential of the gate voltage Vg of power MOS5 moderately downlink, power MOS5
Turns off slowly. Thereby, generation of a surge voltage at the time of turn-off can be suppressed.

Next, an example of the internal configuration of the rising delay circuit 7 and its operation will be described with reference to FIGS. FIG.
, The rising delay circuit 7 includes an AND gate 1
3, a buffer 14 and an integrating circuit 15.
FIG. 8B shows the output of the node 4, that is, the output of the integration circuit 15. The output of the integrating circuit 15 and the dv /
By taking an AND with the output of the dt detection circuit 6, the rising delay circuit 7 outputs dv / dt at turn-off.
A signal delayed for a predetermined time from the rise of the "H" level detection signal of detection circuit 6 is output (FIG. 8C).

As described above, according to the present embodiment,
Since the period during which the potential of the gate voltage Vg does not change is detected, the timing of switching the gate driving force is determined by the power MO.
It does not depend on the variation of the threshold voltage of S5. Further, a time that can be used for feedback control from the detection of the trigger timing by the dv / dt detection circuit 6 at the time of turn-off to the switching of the drive circuit by the switching operation of the gate driving force switching circuit 1 at the time of turn-off is secured with a margin with respect to the timing of occurrence of surge. be able to. If this time is short, the feedback control operation cannot be performed in time, and there is a possibility that the feedback control cannot be performed before the occurrence of the surge. This will be further explained by a numerical example. The time difference from the detection of the trigger timing to the surge peak occurrence timing is about 200 nsec in the first related art, but is about 800 nsec in the present embodiment. The generation of surge can be suppressed with sufficient time margin. Further, by providing a delay time in the rising delay circuit 7, it is possible to minimize an increase in the period during which the gate driving force is weakened during this extra time. This shortens the turn-off time with the optimized time and the switching time.

[Brief description of the drawings]

FIG. 1 is a power MOS according to a first embodiment of the present invention.
It is a block diagram of a drive circuit.

FIG. 2 is a waveform chart of signals and the like for explaining the operation of the first embodiment.

FIG. 3 is a circuit diagram showing an example of an internal configuration of each circuit in FIG. 1;

FIG. 4 is a waveform chart for explaining the operation of the internal configuration circuit of FIG. 3;

FIG. 5 is a block diagram of a second embodiment of the present invention.

FIG. 6 is a waveform chart of signals and the like for explaining the operation of the second embodiment.

FIG. 7 is a circuit diagram showing an example of an internal configuration of a rising delay circuit in FIG. 5;

FIG. 8 is a waveform chart for explaining the operation of the delay circuit.

FIG. 9 is a circuit diagram showing a first related art of a power MOS drive circuit.

FIG. 10 is a waveform chart for explaining the operation of the first conventional technique.

FIG. 11 is a block diagram showing a second conventional technique.

FIG. 12 is a waveform chart for explaining the operation of the second conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Gate drive force switching circuit at the time of turn-off (switching means) 3 Main drive circuit 4 Sub-drive circuit at the time of turn-off 5 Power MOS 6 dv / dt detection circuit at the time of turn-off (voltage change rate detection means) 7 Rise delay circuit (delay circuit)

Claims (2)

[Claims] 1. A power MOS drive circuit comprising a drive circuit for driving a gate of a power MOS, comprising: a voltage change rate detection means for detecting a change rate of a gate voltage of the power MOS; and a voltage change rate detection means. Switching means for switching the drive circuit so as to reduce the gate drive force of the power MOS by a predetermined amount based on the detection result of the power MOS drive circuit. 2. After the detection result of the voltage change rate detecting means,
2. The power MOS drive circuit according to claim 1, further comprising a delay circuit for performing a switching operation of said switching means with a delay of a predetermined time.