JP2001042840A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a device in which the switching of a display system can be done by a set signal from the outside of the device in correspondence to a data input system by providing the device with an input terminal for inputting the signal processing system of an input selection circuit from the outside. SOLUTION: The liquid crystal display device 1 has the input selection circuit 11 for forming the same internal display data signal regardless of the input systems by selecting the signal processing method within the circuit according to the display data signal input system so that the display data signal input system of the device can deal with either case of the two pixel system for every one clock or a single pixel system for every one clock. The device has the input terminal for inputting the set signal for selecting the signal processing method of the input selection circuit 11 from outside. For example, the terminal for an ST signal is connected to the input terminal for inputting to the liquid crystal display device 1 to input the ST signal from outside. There is, therefore, no need for changing the setting within the liquid crystal display device 1 according as the input signal is a two pixel system for every one clock or a single pixel system for every one clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to switching of a display data signal input system in a liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram of a conventional active matrix type liquid crystal display device using a TFT (thin film transistor) as a switching element. 1 is a liquid crystal display device, 10 is a digital control circuit, 11 is an input selection circuit inside 10, 12 is a drive IC control signal generation circuit inside 10, 13 is an analog signal generation circuit, 21 is a liquid crystal cell , 22 are a source drive IC, and 23 is a gate drive I
C.

In the liquid crystal cell, a plurality of parallel source lines 3 are provided.
1. A gate wiring 32 is provided and driven by a source driving IC 22 and a gate driving IC 23, respectively. A display pixel 30 is provided at each intersection of the source wiring 31 and the gate wiring 32, and each pixel is provided with a TFT as a switching element 33. As described above, in a plurality of display pixels of the liquid crystal cell, the liquid crystal is driven by each TFT to suppress the transmittance of the liquid crystal layer, and further, the transmitted light of the backlight under the liquid crystal cell as a light source is controlled to display an image. Perform A source and a gate wiring are connected to each TFT, and a terminal (drain) opposite to the source wiring is connected to a liquid crystal capacitor 34 and a storage capacitor 35. The liquid crystal capacitor 34 and the storage capacitor 35 are connected to a common line 36 in the liquid crystal cell.

RO, GO, BO are input display data signals to the odd-numbered liquid crystal display device 1, RE, GE, BE are input display data signals to the even-numbered liquid crystal display device 1, and CLK is to the liquid crystal display device 1. , An input clock signal DENA, an input display enable signal for transmitting a display data period to the liquid crystal display device 1, HD an input horizontal synchronization signal to the liquid crystal display device 1,
VDD is an input vertical synchronizing signal to the liquid crystal display device 1, and VDD is an input power supply voltage to the liquid crystal display device 1. Where RO,
RE is an input red display data signal, GO and GE are input green display data signals, BO and BE are input blue display data signals, and the number of bits changes according to the number of display colors. In this case, since 8 bits are assumed, each display data signal is 8 lines. The numeral 8 and the diagonal lines added to the wiring indicate that it is 8 bits.

[0005] RO1, GO1, BO1, RE1, GE
1, BE1 is a display data signal selected by the input selection circuit 11, and CLK1 is a clock signal selected by the input selection circuit 11.

[0006] RO2, GO2, BO2, RE2, GE
2, BE2 is a display data signal input to the source drive IC 22, SD is a control signal input to the source drive IC 22, GD is a control signal input to the gate drive IC 23,
AD is a control signal input to the analog signal generation circuit 13, AS is an analog signal input to the source drive IC 22, AG is an analog signal input to the gate drive IC 23, and AC is an analog signal input to the common wiring 36. is there.

As for the input method of the input display data signal, the R, G, and B 8-bit data strings are divided into odd and even rows as described above, and two data are inputted in parallel in one clock cycle. There is a method in which only one data is input in one clock cycle without division. FIG. 4 (a),
(B) shows the timing of both types of display data signals.
The former is two pixels per clock, the latter is one per clock
This is called a pixel method. Since the clock frequency can be halved in the two-pixel-per-clock system, when the signal frequency is increased in a high-definition liquid crystal display device, the clock frequency is reduced to suppress electromagnetic radiation, thereby causing a circuit sampling error due to signal distortion. This is effective for reducing display noise due to For example, if the number of display pixels is 1024 ×
In general, a liquid crystal display device of the XGA specification of 768
The clock frequency in the 1 pixel system per clock is 65M
Although the frequency is in Hz, the clock frequency can be reduced to 32.5 MHz by adopting the two-pixel method per clock. Meanwhile, 1
In the one-pixel-per-clock system, the number of input signals per clock is one.
Since the number can be reduced to half of the 2-pixel system per clock, the cost can be reduced by reducing the number of poles of the connector and the cable. As described above, since both types have advantages and disadvantages, in general, both the two-pixel system for each clock and the one-pixel system for each clock are used for the form of a signal input from the signal source device to the liquid crystal display device. ing.

In order to make the liquid crystal display device versatile, it is necessary to be able to input both types of display data signals. For example, in the case of a two-pixel-per-clock system, the odd-numbered column input display data signals are output from RO, GO, B
O, an even column input display data signal is input to RE, GE, and BE, respectively. On the other hand, in the case of the one-pixel-per-clock system, a serial input display data signal that is not separated into odd columns and even columns is input to RO, GO, BO, and RE,
No signal is input to GE and BE.

Here, each of R, G, B input from the digital control circuit 10 to the source drive IC 22 in the liquid crystal display device.
With respect to an 8-bit data string, due to the limitation of the operating frequency of the driving IC, in the case of the above-mentioned XGA specification, a two-pixel method per clock is generally applied. Therefore, the processing method is selected in the circuit according to the display data input method, and the same RO is always output from the input selection circuit 11 regardless of the input method.
1, GO1, BO1, RE1, GE1, BE1 signals must be output.

FIG. 6 is a circuit diagram illustrating the inside of the input selection circuit 11. As shown in FIG. 101 is a data buffer circuit, 10
Reference numeral 2 denotes a clock control circuit that divides CLK, adjusts the phase, and generates a clock for each circuit. ROS, GOS, BO
S is RO, GO, B by the data buffer circuit 101
This is a signal in which the phase and voltage of O are adjusted. In the case of the two-pixel system per clock, the data signal becomes an odd column data signal as it is. On the other hand, in the case of the one pixel method per one clock, an odd number,
It becomes a serial data signal that is not separated into even columns.

RES, GES, and BES are signals in which the phases and voltages of RE, GE, and BE are adjusted by the data buffer circuit 101. In the case of the two-pixel system for each clock, the signals become data signals of even columns. On the other hand, nothing is input in the case of the one-pixel-per-clock system.

Reference numeral 103 denotes a serial / parallel conversion circuit that divides a serial data signal that is not separated into odd and even columns to generate an odd column signal, and 104 denotes a serial data signal that is not separated into odd and even columns. , A serial / parallel conversion circuit for generating an even-numbered column signal, ROPO, GO
PO and BOPO are the odd-numbered column data signals generated at 103, ROPE, GOPE, and BOPE are the even-numbered data signals generated at 104, CLKPO is generated at 102, and the clock signal CL used for frequency division at 103.
The KPE is a clock signal generated at 102 and used for frequency division at 104.

Reference numeral 105 denotes a data input method of 2 for each clock.
ROPO, GOPO, BOP depending on whether the pixel system is used or the one-pixel system is used for each clock.
O is an odd-number column switching circuit that selects ROS, GOS, and BOS when the two-pixel system is used, and outputs RO, GO1, and BO1 in any case. ROPE, GOPE, B
OPE, RES, GES, BES for 2-pixel system
, And an even-numbered column switching circuit CLKSL which is output as RE1, GE1, BE1 is generated at 102 and is a clock signal for switching at 105, 106.

CLK1P is a clock signal corresponding to one pixel system per one clock only by adjusting the phase and voltage of CLK, and CLK2P is a clock corresponding to two pixel system per one clock whose frequency and frequency are adjusted by dividing CLK by two. Traffic light, 10
Reference numeral 7 denotes a clock switching circuit that selects CLK1P or CLK2P in accordance with a display data input method of two pixels per clock or one pixel per clock and outputs it as CLK1.

Here, the switching states of 105, 106 and 107 are controlled by the ST signal input to the input selection circuit 11. In the conventional liquid crystal display device, the ST signal is switched by switching the ST signal switch 40. When the input display data is a two-pixel system per clock, the ST terminal is connected to VDD and the input display data is switched. In this case, the ST terminal is connected to the ground side in the case of the one pixel system per one clock.

[0016]

In the conventional liquid crystal display device, it is necessary to change the voltage setting of the ST signal according to the one-pixel system per clock or the two-pixel system per clock. Setting change is not possible.
Therefore, it is necessary to separately produce two types of liquid crystal display devices and manage the inventory. Therefore, there is a problem that the product cost increases. Further, the display method is not switched during the operation of the liquid crystal display device.

The present invention has been made to solve the above-mentioned problems of the prior art, and provides a liquid crystal display device in which a display system can be switched by a setting signal from outside the device in correspondence with a data input system. The purpose is to: It is another object of the present invention to provide a liquid crystal display device which automatically determines an input signal and switches a display method without requiring an external setting signal.

[0018]

According to a first aspect of the present invention, there is provided a liquid crystal display device in which a display data signal input method to the liquid crystal display device is a two-pixel method per clock or a one-pixel signal per clock.
An input selection circuit that selects a signal processing method in the circuit according to the display data signal input method and generates the same internal display data signal regardless of the input method so as to support any of the pixel methods. And an input terminal for externally inputting a setting signal for selecting a signal processing method of the input selection circuit.

The liquid crystal display device according to the second configuration of the present invention can cope with either a two-pixel system for one clock or a one-pixel system for one clock as a display data signal input method to the liquid crystal display device. An input selection circuit for selecting a signal processing method in the circuit according to the display data signal input method and generating the same internal display data signal regardless of the input method, wherein the input selection circuit includes one horizontal synchronization signal. By counting clock signals during the input display enable signal period during the period, it is automatically determined whether the display data signal input method to the liquid crystal display device is the two-pixel method per clock or the one-pixel method per clock. To select the signal processing method in the circuit according to the display data signal input method and generate the same internal display data signal regardless of the input method. In which was to so that.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of an active matrix type liquid crystal display device according to a first embodiment of the present invention. Here, the internal configuration of the input selection circuit 11 is the same as that of FIG.
In the present embodiment, the ST signal terminal is connected to an input terminal for inputting to the liquid crystal display device, so that the ST signal is externally input. Therefore, it is not necessary to change the setting inside the liquid crystal display device depending on whether the input method of the display data is the one-pixel method per clock or the two-pixel method per clock. In this case, in the signal source device connected to the liquid crystal display device, for example, when the input method of the display data is the two-pixel method for each clock, the input terminal for the ST signal is connected to VDD, and the input display data is output for one clock. In the case of the pixel system, it may be connected to the ground side. Alternatively, in a cable connecting between a signal source device connected to the liquid crystal display device and the liquid crystal display device, for example, to VDD when input display data is a two-pixel system per clock,
If the input display data is of the one-pixel type per one clock, S
T may be connected to the ground side.

If it is necessary to switch the display mode during the operation of the liquid crystal display device, the data format of the input signal and the ST terminal input signal may be changed simultaneously in the signal source device.

As a result, it is not necessary to change the setting inside the liquid crystal display device according to the one pixel system per one clock or the two pixel system per one clock. Can respond to. Therefore,
The production and inventory management of the liquid crystal display device becomes easy, and as a result, the product cost can be reduced. Further, it is possible to switch the display method during the operation of the liquid crystal display device, and it is possible to flexibly respond to the situation.

Embodiment 2 FIG. 2 is a circuit diagram of an active matrix type liquid crystal display device according to a second embodiment of the present invention. Here, reference numeral 51 denotes a data input method determination circuit that determines whether the data input method of the input signal is the one-pixel method or the two-pixel method for each clock. VDD, DE
NA, CLK, and HD are input, and a setting signal STO corresponding to a one-pixel system per clock or a two-pixel system per clock is output.

FIG. 3 is a circuit diagram of the inside of the judgment circuit 51. 201 is a counter circuit, and 202 is a judgment output circuit. In the counter circuit 201, DENA, CLK, HD, V
DD is input, and HD and VDD are input to the determination output circuit 202.

FIG. 4 shows that the number of display pixels is 1024 (horizontal direction).
FIG. 4 is a signal timing diagram of DENA, display data, CLK, and HD in a 1 pixel system per clock or a 2 pixel system per clock in the XGA specification of × 768 (vertical direction). Here, t _CLK is a clock cycle, and t _H is one horizontal synchronization period. All the signals in the figure are digital signals. For example, the upper side is a power supply (VDD) voltage and is called a high state, and the lower side is a ground voltage and is called a low state. Therefore, t _WDH is the period when DENA is in the high state.

First, the two-pixel system per clock will be described. Here, as the display data, the odd-numbered column display data RO and the even-numbered column display data RE for red display are shown, but the same applies to other green and blue display data. The numbers (1, 2, 3, 4, 5、４1) shown in the display data
021, 1022, 1023, and 1024) are numbers indicating the number of display pixels to be input to the display pixels arranged in the horizontal direction of the liquid crystal display device, each of which is data input to each display pixel. Corresponds to the occurrence period. Therefore, 1 corresponds to the first data, and 1024 corresponds to the last data. As described above, the DENA signal is a signal for transmitting the display data period in the t _H period.
That is, the RO shifts from the low state to the high state in synchronism with the start of the first data and the RE starts the second data, and the RO ends the 1023th data and the RE ends the 1024th data. Transitions from the high state to the low state. Further, the generation period of each display data signal and _tCLK are synchronized. Therefore, 2 per clock
In the pixel system, the following relationship holds. t _WDH / t _CLK = 512

Next, the one-pixel-per-clock system will be described. Here, R for red display is shown as display data, but the same applies to other green and blue display data.
Also, the numbers (1, 2, 3, 4, 5, 5) shown in the display data
# 1023, 1024) are numbers indicating the number of display pixels of the data input to the display pixels arranged in the horizontal direction of the liquid crystal display device. It corresponds to the occurrence period. Therefore, 1 corresponds to the first data, and 1024 corresponds to the last data. As described above, the DENA signal is a signal for transmitting the display data period in the t _H period. That is, R is 1
In synchronization with the start of the data, DENA transitions from the low state to the high state, and R ends the 1024th data, and at the same time, DENA transitions from the high state to the low state. Further, the generation period of each display data signal and _tCLK are synchronized. Therefore, the following relationship is established in the one-pixel-per-clock system. t _WDH / t _CLK = 1024

As described above, by detecting the timing relationship between t _WDH and t _CLK , it is possible to automatically determine the one-pixel system per one clock or the two-pixel system per clock.

The determination method will be described with reference to FIG. The counter circuit 201 counts the number of clocks during the t _WDH period in the DENA signal using the CLK signal in synchronization with HD. The count result is transmitted to the determination output circuit 202 as Count. Inside 202, it is determined whether the number is 512 or 1024, and STO is output based on the determination result. For example, in the case of 512, VDD may be output, and in the case of 1024, the ground voltage may be output.

By making the above determination in each HD cycle, it is possible to automatically cope with a case where the input signal changes from one pixel per clock to two pixels per clock during the operation of the liquid crystal display device. Can be displayed normally.

As a result, it is not necessary to change the setting inside the liquid crystal display device according to the one-pixel system for one clock or the two-pixel system for one clock. Can respond to. Therefore,
The production and inventory management of the liquid crystal display device becomes easy, and as a result, the product cost can be reduced. Further, it is possible to switch the display method during the operation of the liquid crystal display device, and it is possible to flexibly respond to the situation.

Embodiment 3 In the above embodiment, it is assumed that the result of the judgment is as calculated. However, the value may not actually be as calculated due to the influence of noise or the like. In such a case, the same effect can be realized by widening the range of the determination standard.

For example, the following determination is used in the two-pixel system per clock. 0 <t _WDH / t _CLK <767

For example, the following determination is used in the one-pixel-per-clock system. 768 <t _WDH / t _CLK

Embodiment 4 In the above embodiment, the number of display pixels is 1024.
The case of the XGA specification of (horizontal direction) × 768 (vertical direction) has been described.
The present invention can be applied to all display specifications including (horizontal direction) × 1024 (vertical direction). In such a case, the above-mentioned determination formula where the number of display pixels in the horizontal direction is generally n is as follows.

In the case of a two-pixel system per one clock. t _WDH / t _CLK = n / 2

In the case of one pixel system per one clock. t _WDH / t _CLK = n

Embodiment 5 In the above embodiment, an active matrix type liquid crystal display device using a TFT as a switching element has been described. However, other liquid crystal displays such as a passive matrix type liquid crystal display device having no switching element have been described. The present invention is similarly effective when the present invention is applied to a display device.

[0039]

According to the present invention, the setting signal of the input selection circuit in the liquid crystal display device is set in accordance with whether the display data signal input method is the one pixel method per clock or the two pixel method per clock. Is externally input or is automatically determined and set based on an input signal, so that it is not necessary to change the setting inside the liquid crystal display device according to the one-pixel system per one clock or the two-pixel system per clock. So
One type of liquid crystal display device can respond to the above two types of signal inputs. Therefore, production and inventory management of the liquid crystal display device are facilitated, and as a result, product cost can be reduced. Also, when the input signal changes from the one-pixel system per clock to the two-pixel system per clock while the liquid crystal display device is operating, a normal display can always be performed.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an active matrix type liquid crystal display device for explaining a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of an active matrix type liquid crystal display device for explaining a second embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating the inside of a determination circuit 51 of FIG. 2;

FIG. 4 shows a display pixel number of 1024 (horizontal direction) × 768.
1 per clock in XGA specification (vertical direction)
DEN in pixel system and 2-pixel system per clock
FIG. 3 is a signal timing diagram of A, display data, CLK, and HD.

FIG. 5 is a circuit configuration diagram of a conventional active matrix type liquid crystal display device.

FIG. 6 is a circuit configuration diagram illustrating the inside of the input selection circuit 11 of FIGS. 5 and 1;

[Name of code]

 Reference Signs List 1 liquid crystal display device 10 digital control circuit 11 input selection circuit 12 drive IC control circuit 13 analog signal generation circuit 21 liquid crystal cell 22 source drive IC 23 gate drive IC 30 display pixel 31 source wiring 32 gate wiring 33 switching element 34 liquid crystal capacitance 35 holding Capacitance 36 Common wiring 40 ST signal changeover switch 51 Judgment circuit 101 Data buffer circuit 102 Clock control circuit 103, 104 Serial / parallel conversion circuit 105 Odd column switching circuit 106 Even column switching circuit 107 Clock switching circuit 201 Counter circuit 202 Judgment output circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA43 NA61 NC27 ND50 NF05 5C006 AA02 AA03 AA16 AC21 AF43 AF45 BB16 BC12 BC23 BF24 FA04 5C080 AA10 BB05 DD21 EE26 EE29 FF11 GG02 GG09 JJ02 JJ04

Claims (2)

[Claims] 1. A circuit according to a display data signal input method so that a display data signal input method to a liquid crystal display device can correspond to either a two-pixel method for one clock or a one-pixel method for one clock. An input selection circuit for selecting a signal processing method within the circuit and generating the same internal display data signal irrespective of the input method, and for externally inputting a setting signal for selecting a signal processing method of the input selection circuit. Liquid crystal display device provided with an input terminal. 2. A circuit according to the display data signal input method so that the display data signal input method to the liquid crystal display device can be applied to either a two-pixel method for one clock or a one-pixel method for one clock. And an input selection circuit for generating the same internal display data signal irrespective of the input method, the input selection circuit comprising a clock during the input display enable signal period in one horizontal synchronization signal period. By counting the signals, it is automatically detected whether the display data signal input method to the liquid crystal display device is the two-pixel method for one clock or the one-pixel method for one clock, and the display data signal input method is changed to the display data signal input method. A liquid crystal display device that selects a signal processing method in a circuit according to the signal and generates the same internal display data signal regardless of the input method.