CN100386789C - Display panel - Google Patents
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- CN100386789C CN100386789C CNB2005100734379A CN200510073437A CN100386789C CN 100386789 C CN100386789 C CN 100386789C CN B2005100734379 A CNB2005100734379 A CN B2005100734379A CN 200510073437 A CN200510073437 A CN 200510073437A CN 100386789 C CN100386789 C CN 100386789C
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- display panel
- signal
- source electrode
- time schedule
- schedule controller
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- 230000005540 biological transmission Effects 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000009877 rendering Methods 0.000 claims description 16
- 230000001360 synchronised effect Effects 0.000 claims description 3
- GJWAPAVRQYYSTK-UHFFFAOYSA-N [(dimethyl-$l^{3}-silanyl)amino]-dimethylsilicon Chemical compound C[Si](C)N[Si](C)C GJWAPAVRQYYSTK-UHFFFAOYSA-N 0.000 abstract 1
- 208000013586 Complex regional pain syndrome type 1 Diseases 0.000 description 2
- 101100272974 Panax ginseng CYP716A47 gene Proteins 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention relates to a display panel, particularly to a display panel frame for a panel display. The display panel comprises a time schedule controller and a plurality of source electrode drivers, wherein the time schedule controller is used for receiving a low pressure differential motion signal (TMDS/DVI) to generate a plurality of image signals and a synchronization signal, and the source electrode driver comprises at least one channel which is directly connected with the time schedule controller and is used for receiving a corresponding image signal, wherein the time schedule controller comprises a time schedule line which is coupled with the source electrode driver and is used for transmitting the synchronization signal. Each image signal comprises image data corresponding to the pixels of the display panel, and the image signals are transmitted by a transistor logic (TTL) signal format in a serial mode.
Description
Technical field
A kind of flat-panel screens that relates to of the present invention especially relates to the display panel framework that is used for flat-panel screens.
Background technology
Fig. 1 is existing first generation display panel framework, comprise time schedule controller 102 and comprise LVDS (Low Voltage Differential Signal)/TMDS (TransitionMinimized Differential Signaling)/DVI (Digital Video Interface) signal in order to receive differential wave, and two groups of buses, each 104 of multiple source driver by correspondence couples jointly, for example odd number source electrode driver 104 is shared a bus, and coupling is counted source electrode driver 104 and shared another bus.Being six with GTG is example, and each source electrode driver 104 needs RGB totally ten eight transmission lines, and two groups of buses of then described time schedule controller 102 have been used 36 transmission lines altogether.In like manner, if GTG is eight, then need 48 lines altogether.Described time schedule controller 102 receives after the LVDS/TMDS/DVI signal, utilizes described transmission line to transfer data to described source electrode driver 104 with transistor logic signal (TTL) 3.3V or 5V.Character used in proper names and in rendering some foreign names agate reference voltage table 106 item is to be used to provide character used in proper names and in rendering some foreign names agate correction parameter.
Fig. 2 is existing Improvement type display panel framework.Time schedule controller 202 comprises one group of bus, and adds terminal impedance 208 at two ends.And all source electrode drivers 204 couple this group bus jointly.Employed number of transmission lines has been saved half compared with the framework of Fig. 1, and being six with GTG is example, and described time schedule controller 202 couples whole source electrode drivers 204 with 18 transmission lines.Described time schedule controller 202 has received after the LVDS/TMDS/DVI signal, utilizes described transmission line to transfer data to described source electrode driver 204 with small size swing differential signal (RSDS).Character used in proper names and in rendering some foreign names agate reference voltage table 206 item is to be used to provide character used in proper names and in rendering some foreign names agate correction parameter.
Fig. 3 is existing point-to-point display panel framework.Time schedule controller 302 is to linking with exclusive transmission line between each source electrode driver 304, and described transmission line is with the PPDS signal conveys data.Because of transmission line has specificity, need on same bus, not share clock pulse, so transfer rate increases, only need the minority transmission line just can transmit red bluish-green data, or even extra control signal.Character used in proper names and in rendering some foreign names agate reference voltage table 306 item is to be used to provide character used in proper names and in rendering some foreign names agate correction parameter.
Though PPDS has reduced needed number of transmission lines, reduce the laminate cost of manufacture, but still need extra Dc bias electric current, therefore be not suitable on the Portable low power consumption product.In addition, logic voltage makes the reality of differential wave make difficulty more along with technical progress is reduced to 1.8V/1.5V from 5V.
Summary of the invention
The invention provides a kind of display panel framework of flat-panel screens.In one embodiment, described display panel comprises time schedule controller, in order to receive a differential wave (LVDS/TMDS/DVI) to produce a plurality of picture signals and a synchronous signal, and multiple source driver, described source electrode driver respectively comprises at least one passage and directly connects described time schedule controller, in order to receive a corresponding picture signal.Wherein said time schedule controller comprises a sequential line, couples described source electrode driver, in order to transmit described synchronizing signal.Each picture signal comprises the view data of respective pixel in the described display panel, and described picture signal transmits with transistor logic (TTL) signal format string type ground; The frequency of each transistor logic signal is decided according to following formula:
(the clock pulse speed of described time schedule controller * described GTG figure place)/(number of described source electrode driver * 2).
Described passage respectively comprises three transmission lines, and each is in order to transmit a first transistor logical signal, a transistor seconds logical signal and one the 3rd transistor logic signal.Described the first transistor logical signal transmits red data serially, and described transistor seconds logical signal transmits green data serially, and described the 3rd transistor logic signal transmits blue data serially.Described first, second and third transistor logic signal does not need Dc bias.
Beneficial effect of the present invention is that the present invention has saved the wiring number of display panel, and has reduced current drain.
Description of drawings
Fig. 1 is existing first generation display panel framework;
Fig. 2 is existing Improvement type display panel framework;
Fig. 3 is existing point-to-point display panel framework;
Fig. 4 a is the display panel framework map of one of embodiment of the invention;
Fig. 4 b is the display panel framework map of another embodiment of the present invention;
Fig. 5 is the graph of a relation of transfer rate and resolution.
Symbol description:
102～time schedule controller, 104～source electrode driver
106～character used in proper names and in rendering some foreign names agate reference voltage table 202～time schedule controller
204～source electrode driver, 206～character used in proper names and in rendering some foreign names agate reference voltage table
208～terminal impedance, 302～time schedule controller
304～source electrode driver, 306～character used in proper names and in rendering some foreign names agate reference voltage table
308～terminal impedance, 402～time schedule controller
404～source electrode driver, 406～character used in proper names and in rendering some foreign names agate reference voltage table
408～source electrode driver
Embodiment
Fig. 4 a is the display panel framework map of one of embodiment of the invention.There is exclusive transmission line to connect between each source electrode driver 404 and the time schedule controller 402, i.e. R1, G1, B1R8, G8, B8, each transmission line distinctly transmits redness, green or blue signal.Described time schedule controller 402 comprises a CLK in addition and connects each source electrode driver 404, in order to synchronous clock signal to be provided.Described display panel still comprises a character used in proper names and in rendering some foreign names agate reference voltage table 406, connects each source electrode driver 404, in order to character used in proper names and in rendering some foreign names agate correction parameter to be provided.Time schedule controller 402 has used 8 * 3 transmission lines altogether in the present embodiment, and grey exponent number can not be limited to six.In addition, the TTL signal between time schedule controller 402 and the source electrode driver 404 can be CMOS (Complementary Metal Oxide Semiconductor) (CMOS) signal, compared to the RSDS signal, can reduce current drain.Wherein said R, G, B line do not limit and only transmit R-G-B signals, therefore described character used in proper names and in rendering some foreign names agate reference voltage table 406 not necessarily will independently exist, can produce character used in proper names and in rendering some foreign names agate correction signal by time schedule controller 402, be sent to source electrode driver 404 through described exclusive R, G, B line.
Fig. 4 b is the display panel framework map of another embodiment of the present invention.Wherein comprise four source electrode drivers 408, each source electrode driver 408 respectively comprises two groups of R, G, the B transmission line connects time schedule controller 402.Therefore compared to the framework of 4a, the source electrode driver number of use has been saved half.Two source electrode drivers 404 that are equivalent among Fig. 4 a at this source electrode driver 408 combine.
Fig. 5 is the graph of a relation of transfer rate and resolution.Because each source electrode driver only depends on R, G, B transmission line, so the size of data volume has determined transfer rate.For a TCON, the rapid pulse rate is different with resolution at that time, under the XGA of 60Hz pattern, be 65MHz for example, the GTG of each color has six, the source electrode driver number is 8, and the rising edge of TCON clock pulse and drop edge all can be used to trigger pip, so the speed on each transmission line can be calculated and obtain 24.375MHz with following formula:
(clock pulse of time schedule controller * GTG figure place)/(number of source electrode driver * 2)
In sum, because the TTL transmission signals does not need to apply extra Dc bias, with respect to differential wave, easier being applied to hanged down in the system of logic voltage (for example 1.8V).The present invention has saved the wiring number of display panel, and has reduced current drain.
The embodiment that more than provides has highlighted many characteristics of the present invention.Though the present invention discloses as above with preferred embodiment, it is not in order to limiting scope of the present invention, and any those skilled in the art without departing from the spirit and scope of the present invention, can do various changes and retouching.The branch section header carried according to regulation of this instructions is not used in and limits that to carry in its content described scope, the especially background technology may not be the known invention that has disclosed in addition, and invention description is also non-in order to limit technical characterictic of the present invention.Protection scope of the present invention should be as the criterion with the scope that claims are asked for protection.
Claims (6)
1. a display panel is used for flat-panel screens, it is characterized in that comprising:
Time schedule controller is in order to receive a differential wave, to produce a plurality of picture signals and a synchronous signal; And
Multiple source driver, described source electrode driver respectively comprise at least one passage and directly connect described time schedule controller, in order to receive a corresponding picture signal; Wherein
Described time schedule controller comprises a sequential line, couples described source electrode driver, in order to transmit described synchronizing signal;
Each picture signal comprises the view data of respective pixel in the described display panel; And
Described picture signal transmits on described passage with transistor logic signal format string type ground;
The frequency of each transistor logic signal is decided according to following formula:
(the clock pulse speed of described time schedule controller * described GTG figure place)/(number of described source electrode driver * 2).
2. display panel according to claim 1 is characterized in that:
Described picture signal comprises red data, green data and blue data; And
Described passage respectively comprises three transmission lines, and each is in order to transmit a first transistor logical signal, a transistor seconds logical signal and one the 3rd transistor logic signal.
3. display panel according to claim 1 is characterized in that:
Described the first transistor logical signal transmits red data serially;
Described transistor seconds logical signal transmits green data serially; And
Described the 3rd transistor logic signal transmits blue data serially.
4. display panel according to claim 1 is characterized in that: also further comprise a character used in proper names and in rendering some foreign names agate reference voltage table, couple described source electrode driver, in order to character used in proper names and in rendering some foreign names agate correction parameter to be provided.
5. display panel according to claim 1 is characterized in that:
The Dc bias of described first, second and third transistor logic signal is zero.
6. display panel according to claim 1 is characterized in that:
Each source electrode driver comprises two groups of passages and directly connects described time schedule controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100734379A CN100386789C (en) | 2005-05-24 | 2005-05-24 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100734379A CN100386789C (en) | 2005-05-24 | 2005-05-24 | Display panel |
Publications (2)
| Publication Number | Publication Date |
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| CN1725277A CN1725277A (en) | 2006-01-25 |
| CN100386789C true CN100386789C (en) | 2008-05-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005100734379A Expired - Fee Related CN100386789C (en) | 2005-05-24 | 2005-05-24 | Display panel |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8421722B2 (en) * | 2006-12-04 | 2013-04-16 | Himax Technologies Limited | Method of transmitting data from timing controller to source driving device in LCD |
| CN101246670B (en) * | 2007-02-17 | 2010-06-16 | 联詠科技股份有限公司 | Serial data transmission method and correlated device used for display device |
| CN101441857B (en) * | 2007-11-20 | 2011-02-02 | 联咏科技股份有限公司 | Circuit apparatus capable of improving electromagnetic interference and correlation (related) method thereof |
| CN101572047B (en) * | 2008-05-04 | 2011-05-18 | 联咏科技股份有限公司 | Data synchronization method for display and correlative device |
| CN101609652B (en) * | 2008-06-17 | 2012-12-19 | 联咏科技股份有限公司 | Transmission interface and method for reducing power consumption and electromagnetic interference effect |
| CN107507576B (en) * | 2017-09-05 | 2019-10-11 | 深圳市华星光电半导体显示技术有限公司 | The sensing system and its analog-to-digital conversion error calibration method of oled panel |
| KR102577236B1 (en) * | 2018-06-05 | 2023-09-12 | 삼성전자주식회사 | Display apparatus and interface operation thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001134241A (en) * | 1999-11-08 | 2001-05-18 | Kyocera Corp | Liquid crystal display device |
| US20020008682A1 (en) * | 2000-07-18 | 2002-01-24 | Park Jin-Ho | Flat panel display with an enhanced data transmission |
| US20020084972A1 (en) * | 2000-12-28 | 2002-07-04 | Kim Jong Dae | Liquid crystal display device and method for driving the same |
| US20030122761A1 (en) * | 2001-12-31 | 2003-07-03 | Hyung-Ki Hong | Driving device of liquid crystal display device and driving method thereof |
| JP2004101805A (en) * | 2002-09-09 | 2004-04-02 | Nec Micro Systems Ltd | Liquid crystal display and method of driving the same |
| US20050001801A1 (en) * | 2003-06-05 | 2005-01-06 | Kim Ki Duk | Method and apparatus for driving liquid crystal display device |
| CN1604172A (en) * | 2003-10-02 | 2005-04-06 | Lg.菲利浦Lcd株式会社 | Apparatus and method for driving liquid crystal display |
-
2005
- 2005-05-24 CN CNB2005100734379A patent/CN100386789C/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001134241A (en) * | 1999-11-08 | 2001-05-18 | Kyocera Corp | Liquid crystal display device |
| US20020008682A1 (en) * | 2000-07-18 | 2002-01-24 | Park Jin-Ho | Flat panel display with an enhanced data transmission |
| US20020084972A1 (en) * | 2000-12-28 | 2002-07-04 | Kim Jong Dae | Liquid crystal display device and method for driving the same |
| US20030122761A1 (en) * | 2001-12-31 | 2003-07-03 | Hyung-Ki Hong | Driving device of liquid crystal display device and driving method thereof |
| JP2004101805A (en) * | 2002-09-09 | 2004-04-02 | Nec Micro Systems Ltd | Liquid crystal display and method of driving the same |
| US20050001801A1 (en) * | 2003-06-05 | 2005-01-06 | Kim Ki Duk | Method and apparatus for driving liquid crystal display device |
| CN1604172A (en) * | 2003-10-02 | 2005-04-06 | Lg.菲利浦Lcd株式会社 | Apparatus and method for driving liquid crystal display |
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| Publication number | Publication date |
|---|---|
| CN1725277A (en) | 2006-01-25 |
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| ASS | Succession or assignment of patent right |
Owner name: YOUDA PHOTOELECTRIC CO., LTD. Free format text: FORMER OWNER: GUANGHUI ELECTRONIC CO., LTD. Effective date: 20071130 |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20071130 Address after: Hsinchu city of Taiwan Province Applicant after: AU OPTRONICS Corp. Address before: Taoyuan County of Taiwan Province Applicant before: QUANTA DISPLAY INCORPORATION |
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Granted publication date: 20080507 |