CN100386789C - Display panel - Google Patents

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CN100386789C
CN100386789C CN 200510073437 CN200510073437A CN100386789C CN 100386789 C CN100386789 C CN 100386789C CN 200510073437 CN200510073437 CN 200510073437 CN 200510073437 A CN200510073437 A CN 200510073437A CN 100386789 C CN100386789 C CN 100386789C
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signal
timing controller
source driver
display panel
image
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CN 200510073437
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CN1725277A (en
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易建宇
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友达光电股份有限公司
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Abstract

本发明涉及显示面板,尤其是涉及用于平面显示器的显示面板构架。 The present invention relates to a display panel, and more particularly to a display panel for a flat display frame. 所述显示面板包含一时序控制器,用以接收一差动信号(LVDS/TMDS/DVI)以产生多个图像信号以及一同步信号,以及多个源极驱动器,所述源极驱动器各包含至少一通道直接连接所述时序控制器,用以接收对应的一图像信号。 The display panel includes a timing controller for receiving a differential signal (LVDS / TMDS / DVI) to generate a plurality of image signal and a synchronizing signal, and a plurality of source driver, the source driver each comprise at least a channel connected directly to the timing controller for receiving a signal corresponding to the image. 其中所述时序控制器包含一时序线,耦接所述源极驱动器,用以传送所述同步信号。 Wherein the timing controller comprises a timing line, coupled to the source driver, for transmitting the synchronization signal. 每一图像信号包含所述显示面板中对应像素的图像数据,所述图像信号以晶体管逻辑信号格式串行式地传送。 Each pixel in the image signal including image data corresponding to the display panel, the image signal transistor logic serial signal format transmitted.

Description

显示面板 Display panel

技术领域 FIELD

本发明一种涉及平面显示器,尤其是涉及用于平面显示器的显示面;^构架。 The present invention relates to one kind of flat panel display, particularly relates to a display surface of the flat panel display; ^ framework. 背景技术 Background technique

图1为现有的第一代显示面板构架,包含一时序控制器102用以接收差动信号包括LVDS (Low Voltage Differential Signal) /TMDS (Transition Minimized Differential Signaling) /DVI (Digital Video Interface)信号,以及两組总线,各由对应的多个源极驱动器104所共同耦接,例如奇数源极驱动器104共享一总线,耦数源极驱动器104共享另一总线,以灰阶为六位为例,每一源极驱动器104需要红绿蓝共十八条传输线,则所述时序控制器102的两组总线共使用了三十六条传输线。 FIG 1 is a conventional display panel of the first generation architecture, comprising a timing controller 102 for receiving a signal comprising differential signal LVDS (Low Voltage Differential Signal) / TMDS (Transition Minimized Differential Signaling) / DVI (Digital Video Interface), and two sets of buses, each being coupled together by a corresponding plurality of source drivers 104, for example, odd-numbered source driver 104, a shared bus, the number of source driver coupled to the shared another bus 104, to six grayscale example, each source driver 104 requires a total of eighteen RGB transmission lines, the timing controller 102 of the two groups were used thirty-six bus transmission line. 同理,如果灰阶为八位,则总共需要四十八条线。 Similarly, if the gray scale is eight, then a total of forty-eight line. 所述时序控制器102接收LVDS/TMDS/DVI信号之后, 利用所述传输线以晶体管逻辑信号(TTL) 3. 3V或5V来传输数据至所述源极驱动器104。 After the timing controller 102 receives the LVDS / TMDS / DVI signals, the transmission data signal to transistor logic (TTL) 3. 3V to 5V or to the source driver 104 using the transmission line. 迦玛参考电压表106则是用来提供迦玛校正参数。 Gamma reference voltage table 106 is used to provide gamma correction parameter.

图2为现有的改良式显示面板构架。 FIG 2 is a modified conventional display panel frame. 时序控制器202包含一组总线,并在两端加上终端阻抗208。 The timing controller 202 includes a set of bus termination impedance 208 and coupled at both ends. 而所有的源极驱动器204共同耦接这组总线。 And all of the source driver 204 are coupled together this group of buses. 所使用的传输线数目比起图1的构架节省了一半,以灰阶为六位为例,所述时序控制器202以十八条传输线耦接全部源极驱动器204。 The number of transmission lines than the frame used for cutting in half of FIG. 1, an example grayscale is six, the timing controller 202 to the transmission line is coupled eighteen entire source driver 204. 所述时序控制器202接收了LVDS/TMDS/DVI信号之后,利用所述传输线以小幅摆动差动信号(RSDS) 来传输数据至所述源极驱动器204。 After the timing controller 202 receives the LVDS / TMDS / DVI signal using the transmission line to wobble slightly differential signal (the RSDS) to transmit data to the source driver 204. 迦玛参考电压表206则是用来提供迦玛校正参数。 Gamma reference voltage meter 206 is used to provide gamma correction parameter.

图3为现有的点对点显示面板构架。 Figure 3 shows the architecture of an existing ad hoc panel. 时序控制器302至每个源极驱动器304之间以专属的传输线连结,所述传输线以PPDS信号传送数据。 The timing controller 302 to each of the source driver 304 between the dedicated transmission line connecting said transmission line to transmit data signals PPDS. 因传输线具有专属性,不需要在同一总线上分享时脉,所以传输速率增高,仅需要少数传输线便可以传送红蓝绿的数据,甚至是额外的控制信号。 Transmission line has exclusive because, when not required to share the same bus clock, the transmission rate is increased, it requires only a small number of transmission lines can transmit data of red, blue, green, or even additional control signal. 迎玛参考电压 Ma Ying-reference voltage

表306则是用来提供迦玛校正参数。 Table 306 is used to provide gamma correction parameter.

PPDS虽然减少了所需要的传输线数目,降低层板制作成本,但仍然需要额外的直流偏压电流,因此不适用于可携式低耗电产品上。 PPDS while reducing the number of transmission lines required to reduce the manufacturing cost laminates, but still requires an additional DC bias current, therefore not suitable for low power consumption in a portable product. 此外,逻辑电压随着技术进步从5V降至1. 8V/L 5V,使得差动信号的实作更加困难。 Further, as the technology advances from logic voltage 5V down to 1. 8V / L 5V, such as real differential signals more difficult. 发明内容 SUMMARY

本发明提供一种平面显示器的显示面板构架。 The present invention provides a flat display panel of a display frame. 在一实施例中,所述显示面板包含一时序控制器,用以接收一差动信号(LVDS/TMDS/DVI)以产生多个图像信号以及一同步信号,以及多个源极驱动器,所述源极驱动器各包含至少一通道直接连接所述时序控制器,用以接收对应的一图像信号。 In one embodiment, the display panel includes a timing controller for receiving a differential signal (LVDS / TMDS / DVI) to generate a plurality of image signal and a synchronizing signal, and a plurality of source drivers, said the source driver comprises at least one channel each directly connected to the timing controller for receiving a signal corresponding to the image. 其中所述时序控制器包含一时序线,耦接所述源极驱动器,用以传送所述同步信号。 Wherein the timing controller comprises a timing line, coupled to the source driver, for transmitting the synchronization signal. 每一图像信号包含所述显示面板中对应像素的图像数据,所述图像信号以晶体管逻辑(TTL)信号格式串行式地传送;每一晶体管逻辑信号的频率根据下列公式而定: Each image signal including the display panel corresponding to the pixels in the image data of the image signal to transistor logic (TTL) signals transmitted serial format; frequency of each transistor logic signal depends on the following formula:

(所述时序控制器的时脉速率x所述灰阶位数)/(所述源极驱动器的数目x 2 )。 (Clock rate of the timing controller of the gray scale bits x) / (the number of source driver x 2).

所述通道各包含三条传输线,各用以传送一第一晶体管逻辑信号、 一第二晶体管逻辑信号以及一第三晶体管逻辑信号。 Each of said channels comprises three transmission lines, each of the first transistor for transmitting a logic signal, a second logic signal and a third transistor transistor logic signal. 所述第一晶体管逻辑信号串行地传输红色数据,所述第二晶体管逻辑信号串行地传输绿色数据,以及所述第三晶体管逻辑信号串行地传输蓝色数据。 The first transistor logic red data signal serially transmitted, said second transistor logic signals transmitted serially green data, and the third transistor logic blue data signals transmitted serially. 所述第一、第二及第三晶体管逻辑信号不需要直流偏压。 Said first, second and third logic transistor does not need a DC bias signal.

本发明的有益效果在于,本发明节省了显示面板的布线数目,并降低了 Advantageous effects of the present invention, the present invention saves the number of wirings of the display panel, and reduces the

电流消耗。 Current consumption. 附图说明 BRIEF DESCRIPTION

图1为现有的第一代显示面板构架; 图2为现有的改良式显示面板构架; 图3为现有的点对点显示面板构架; FIG 1 is a conventional first-generation display panel frame; FIG. 2 is a modified conventional frame display panel; FIG. 3 is a conventional point-frame display panel;

图4a为本发明实施例之一的显示面板构架图; Figure 4a shows a view of one embodiment of the frame panel embodiment of the present invention;

图4b为本发明另一实施例的显示面板构架图; The display panel according to another embodiment of the frame of FIG. FIG. 4b of the present invention;

图5为传输速率与分辨率的关系图。 FIG 5 is a relationship between the transmission rate and the resolution in FIG.

符号说明: Symbol Description:

104~源极驱动器202 ~时序控制器206 ~迦玛参考电压表302~时序控制器306 -迦玛参考电压表402 ~时序控制器406〜迦玛参考电压表 The source driver 104 to the timing controller 206 ~ 202 ~ 302 ~ voltmeter gamma reference timing controller 306-- ~ gamma reference voltage timing controller table 402 406~ gamma reference voltage meter

102~时序控制器106-迎玛参考电压表204 ~源极驱动器208 ~终端阻抗304~源极驱动器308 ~终端阻抗404 -源极驱动器408 -源极驱动器具体实施方式 The timing controller 102 to the reference voltage meter Ma Ying 106- 204 ~ 208 ~ source driver termination impedance of the source driver 304 and the termination impedance 308 ~ 404 - source driver 408-- source driver DETAILED DESCRIPTION

图4a为本发明实施例之一的显示面板构架图。 Figure 4a shows a view of one embodiment of the frame panel of the present embodiment of the invention. 每一源极驱动器404和时序控制器402之间有专属的传输线连接,即R1、 Gl、 B1到R8、 G8、 B8,每一传输线各别传送红色、绿色或蓝色信号。 Each of the source drivers and a timing controller 404 has a dedicated connection between the transmission line 402, i.e. R1, Gl, B1 to R8, G8, B8, each individual transmission line transfer of red, green or blue signals. 所述时序控制器402另包含一条CLK 连接每一源极驱动器404,用以提供同步时脉信号。 The timing controller 402 further comprises a CLK connecting each source driver 404 for providing a clock signal synchronization. 所述显示面板尚包含一迦玛参考电压表406,连接每一源极驱动器404,用以提供迦玛校正参数。 The display panel comprises a gamma reference voltage still table 406, each connected to a source driver 404 for providing gamma correction parameter. 在本实施例中时序控制器402总共使用了8 x 3条传输线,灰阶数可以不限定在六位。 In the present embodiment, the timing controller 402 uses a total of 8 x 3 transmission lines, the number of gray scale may not be limited to six. 此外,时序控制器402和源极驱动器404之间的TTL信号可为互补式金属氧化物半导体(CMOS)信号,相较于RSDS信号,可降低电流消耗。 Further, the timing controller 402 and the source driver 404 between TTL signal may be a complementary metal-oxide semiconductor (CMOS) signal, compared to the RSDS signal, current consumption can be reduced. 其中所述R、 G、 B线并不限定只传送红绿蓝信号,因此所述迦玛参考电压表406不一定要独立存在,可以由时序控制器402产生迦玛校正信号,透过所述专属的R、 G、 B线传送至源极驱动器404。 Wherein the R, G, B lines is not limited to only transmit RGB signals, the gamma reference voltage table 406 does not have to exist independently, gamma correction signals may be generated by the timing controller 402, through the Exclusive of R, G, B transmitted to the source line driver 404.

图4b为本发明另一实施例的显示面板构架图。 The display panel of FIG. 4b architecture diagram of another embodiment of the present invention. 其中包含四个源极驱动器408,每个源极驱动器408各包含两组R、 G、 B传输线连接时序控制器402。 Wherein the driver comprises four source 408, each source driver 408 each include two sets of R, G, B of the transmission line 402 connected to the timing controller. 因此相较于4a的构架,使用的源极驱动器数目节省了一半。 Thus compared to the framework 4a, the number of source driver used to save half. 在此源极驱动器408相当于图4a中的两个源极驱动器404合并在一起。 In two source driver 4a in this source driver 408 corresponds to the combined 404 in FIG.

图5为传输速率与分辨率的关系图。 FIG 5 is a relationship between the transmission rate and the resolution in FIG. 由于每一源极驱动器仅靠R、 G、 B 传输线,因此数据量的大小决定了传输速率。 Since each source driver alone R, G, B of the transmission line, so the amount of data determines the size of the transmission rate. 对于一TCON而言,其时脉速率随分辨率而异,例如在60Hz的XGA模式下为65MHz,每一颜色的灰阶有六位, 源极驱动器数目为8,而且TCON时脉的上升边缘和下降边缘都可用来触发信号,因此每一传输线上的速率可以用下式推算而得到24. 375MHz: For a TCON, its clock rate varies with the resolution, for example, at 60Hz, XGA modes are six of 65MHz, each color of gray, the number of source driver 8, and the rising edge of clock TCON and a falling edge can be used to trigger signal, so the rate of each transmission line can be calculated by the following formula to give 24. 375MHz:

(时序控制器的时脉x灰阶位数)/ (源极驱动器的数目x 2 ) (X clock timing controller grayscale bits) / (the number of source driver x 2)

综上所述,由于TTL传输信号不需要施加额外的直流偏压,相对于差动信号,更易应用于低逻辑电压(例如1.8V)的系统中。 In summary, the TTL signal transmission does not require additional DC bias is applied, with respect to the differential signal, a low logic voltage applied more (e.g., 1.8V) system. 本发明节省了显示面板的布线数目,并降4氐了电流消耗。 The present invention saves the number of wirings of the display panel, and reduce the current consumption Di 4.

以上提供的实施例已突出显示了本发明的诸多特色。 Example embodiments provided above highlighted many features of the invention. 本发明虽以较佳实施例揭露如上,但其并非用以限定本发明的范围,任何本领域的技术人员, 在不脱离本发明的精神和范围内,可做各种的更动与润饰。 While the invention has been described by the preferred embodiments, but not intended to limit the scope of the present invention, anyone skilled in the art, without departing from the spirit and scope of the present invention, that various alterations and modifications. 此外本说明书依照规定所提的分段标题并不用于限定其内容所述的范围,尤其是背景技术中所提未必是已揭露的公知发明,发明说明也非用以限定本发明的技术特征。 In addition, pursuant to the present description mentioned section headings are not intended to limit the scope of the contents thereof, in particular, may not be mentioned in the background art have been disclosed in the known invention, description of the invention is also not intended to limit the technical features of the present invention. 本发明的保护范围应当以权利要求书请求保护的范围为准。 The scope of the invention should be requested scope of the appended claims and their equivalents.

Claims (7)

1.一显示面板,用于平面显示器,其特征在于包含: 一时序控制器,用以接收一差动信号,以产生多个图像信号以及一同步信号;以及多个源极驱动器,所述源极驱动器各包含至少一通道直接连接所述时序控制器,用以接收对应的一图像信号;其中所述时序控制器包含一时序线,耦接所述源极驱动器,用以传送所述同步信号; 每一图像信号包含所述显示面板中对应像素的图像数据;以及所述图像信号以晶体管逻辑信号格式串行式地在所述通道上传送; 每一晶体管逻辑信号的频率根据下列公式而定: (所述时序控制器的时脉速率×所述灰阶位数)/(所述源极驱动器的数目×2)。 1. A display panel for a flat display, characterized by comprising: a timing controller for receiving a differential signal to generate a plurality of image signals and a synchronization signal; and a plurality of source driver, the source each driver comprises at least one passage is directly connected to the timing controller for receiving a signal corresponding to the image; wherein the timing controller comprises a timing line, coupled to the source driver, for transmitting the synchronization signal ; each pixel of the display image signal including image data corresponding to the panel; and a serial format to transfer the image signal to the transistor on the logic signal path; frequency of each transistor logic signal depends on the following formula : (the clock rate of the timing controller × grayscale bits) / (the number of source driver × 2).
1. 一显示面板,用于平面显示器,其特征在于包含: 一时序控制器,用以接收一差动信号,以产生多个图像信号以及一同步信号;以及多个源极驱动器,所述源极驱动器各包含至少一通道直接连接所述时序控制器,用以接收对应的一图像信号;其中所述时序控制器包—时序线,^所述源极驱动器,用以传送所述同步信号; 每一图像信号包含所述显示面板中对应像素的图像数据;以及所述图像信号以晶体管逻辑信号格式串行式地在所述通道上传送; 每一晶体管逻辑信号的频率根据下列公式而定: (所述时序控制器的时脉速率x所述灰阶位数)/(所述源极驱动器的数目x 2 )。 1. A display panel for a flat display, characterized by comprising: a timing controller for receiving a differential signal to generate a plurality of image signals and a synchronization signal; and a plurality of source driver, the source each driver comprises at least one passage is directly connected to the timing controller for receiving a signal corresponding to the image; wherein the timing controller packet - a timing line, ^ the source driver, for transmitting said synchronization signal; each pixel of the display image signal includes image data corresponding to the panel; and the image signal transmitted in serial format transistor logic signal on said channel; logic signal frequency of each transistor depends on the following formula: (clock rate of the timing controller of the gray scale bits x) / (the number of source driver x 2).
2. 根据权利要求1所述的显示面板,其特征在于: 所述图像信号包含红色数据、绿色数据以及蓝色数据;以及所述通道各包含三条传输线,各用以传送一第一晶体管逻辑信号、 一第二晶体管逻辑信号以及一第三晶体管逻辑信号。 2. The display panel according to claim 1, wherein: the image signal comprises red data, green data, and blue data; and each of said channels comprises three transmission lines, each of the first transistor for transmitting a logic signal a second logic signal and a third transistor transistor logic signal.
3. 根据权利要求1所述的显示面板,其特征在于: 所述第一晶体管逻辑信号串行地传输红色数据; 所述第二晶体管逻辑信号串行地传输绿色数据;以及所述第三晶体管逻辑信号串行地传输蓝色数据。 3. The display panel according to claim 1, wherein: said first transistor logic red data signal transmitted serially; said second transistor logic data signals transmitted serially green; and the third transistor logic signals transmitted serially blue data.
4. 根据权利要求1所述的显示面板,其特征在于:还进一步包含一迦玛参考电压表,耦接所述源极驱动器,用以提供迦玛校正参数。 4. The display panel of claim 1, characterized in that: further comprising a gamma reference voltage meter, coupled to the source driver, for providing a gamma correction parameter.
5. 根据权利要求1所述的显示面板,其特征在于: 所述第一、第二及第三晶体管逻辑信号的直流偏压为零。 The display panel according to claim 1, wherein: said first, second and third DC bias transistor logic zero signal.
6. 根据权利要求1所述的显示面板,其特征在于: 每一源极驱动器包含二组通道直接连接所述时序控制器。 The display panel according to claim 1, wherein: each source driver comprises a second set of channels is directly connected to the timing controller. 2 2
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US20050001801A1 (en) 2003-06-05 2005-01-06 Kim Ki Duk Method and apparatus for driving liquid crystal display device
CN1604172A (en) 2003-10-02 2005-04-06 Lg.菲利浦Lcd株式会社 Apparatus and method for driving liquid crystal display

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US20020008682A1 (en) 2000-07-18 2002-01-24 Park Jin-Ho Flat panel display with an enhanced data transmission
US20020084972A1 (en) 2000-12-28 2002-07-04 Kim Jong Dae Liquid crystal display device and method for driving the same
US20030122761A1 (en) 2001-12-31 2003-07-03 Hyung-Ki Hong Driving device of liquid crystal display device and driving method thereof
US20050001801A1 (en) 2003-06-05 2005-01-06 Kim Ki Duk Method and apparatus for driving liquid crystal display device
CN1604172A (en) 2003-10-02 2005-04-06 Lg.菲利浦Lcd株式会社 Apparatus and method for driving liquid crystal display

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